William J. Dally

273 papers A* 62A 21B 16C 14Misc 2Journal 98Unranked 54

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. IEEE J. Solid State Circuits Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray
2024	—	`conf`	Leveraging Micro-Bump Pitch Scaling to Accelerate Interposer Link Bandwidths for Future High-Performance Compute Applications. CICC Walker J. Turner, John W. Poulton, Yoshinori Nishi, Xi Chen, Brian Zimmer, Sanquan Song, John M. Wilson, William J. Dally, C. Thomas Gray
2023	—	`conf`	A 0.190-pJ/bit 25.2-Gb/s/wire Inverter-Based AC-Coupled Transceiver for Short-Reach Die-to-Die Interfaces in 5-nm CMOS. VLSI Technology and Circuits Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray
2023	J	`jnl`	A 0.297-pJ/Bit 50.4-Gb/s/Wire Inverter-Based Short-Reach Simultaneous Bi-Directional Transceiver for Die-to-Die Interface in 5-nm CMOS. IEEE J. Solid State Circuits Yoshinori Nishi, John W. Poulton, Walker J. Turner, Xi Chen, Sanquan Song, Brian Zimmer, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray
2023	J	`jnl`	A 95.6-TOPS/W Deep Learning Inference Accelerator With Per-Vector Scaled 4-bit Quantization in 5 nm. IEEE J. Solid State Circuits Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, Charbel Sakr, William J. Dally, C. Thomas Gray, Brucek Khailany
2023	J	`jnl`	A Novel High-Efficiency Three-Phase Multilevel PV Inverter With Reduced DC-Link Capacitance. IEEE Trans. Ind. Electron. Tuofei Chen, Lei Gu, William J. Dally, Juan Rivas-Davila, John D. Fox
2023	—	`conf`	GPU-Initiated On-Demand High-Throughput Storage Access in the BaM System Architecture. ASPLOS (2) Zaid Qureshi, Vikram Sharma Mailthody, Isaac Gelado, Seungwon Min, Amna Masood, Jeongmin Brian Park, Jinjun Xiong, Chris J. Newburn, Dmitri Vainbrand, I-Hsin Chung, Michael Garland, William J. Dally, Wen-mei W. Hwu
2023	J	`jnl`	Retrospective: EIE: Efficient Inference Engine on Sparse and Compressed Neural Network. CoRR Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally
2023	J	`jnl`	SatIn: Hardware for Boolean Satisfiability Inference. CoRR Chenzhuo Zhu, Alexander C. Rucker, Yawen Wang, William J. Dally
2022	—	`conf`	A 0.297-pJ/bit 50.4-Gb/s/wire Inverter-Based Short-Reach Simultaneous Bidirectional Transceiver for Die-to-Die Interface in 5nm CMOS. VLSI Technology and Circuits Yoshinori Nishi, John W. Poulton, Xi Chen, Sanquan Song, Brian Zimmer, Walker J. Turner, Stephen G. Tell, Nikola Nedovic, John M. Wilson, William J. Dally, C. Thomas Gray
2022	—	`conf`	A 17-95.6 TOPS/W Deep Learning Inference Accelerator with Per-Vector Scaled 4-bit Quantization for Transformers in 5nm. VLSI Technology and Circuits Ben Keller, Rangharajan Venkatesan, Steve Dai, Stephen G. Tell, Brian Zimmer, William J. Dally, C. Thomas Gray, Brucek Khailany
2022	J	`jnl`	BaM: A Case for Enabling Fine-grain High Throughput GPU-Orchestrated Access to Storage. CoRR Zaid Qureshi, Vikram Sharma Mailthody, Isaac Gelado, Seungwon Min, Amna Masood, Jeongmin Brian Park, Jinjun Xiong, Chris J. Newburn, Dmitri Vainbrand, I-Hsin Chung, Michael Garland, William J. Dally, Wen-mei W. Hwu
2022	—	`conf`	Frontier vs the Exascale Report: Why so long? and Are We Really There Yet? PMBS@SC Peter M. Kogge, William J. Dally
2022	J	`jnl`	LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update. IEEE Trans. Computers Jiawei Zhao, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, Mustafa Fayez Ali, Ming-Yu Liu, Brucek Khailany, William J. Dally, Anima Anandkumar
2022	J	`jnl`	On the model of computation: point. Commun. ACM William J. Dally
2022	A*	`conf`	Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training. ICML Charbel Sakr, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, William J. Dally, Brucek Khailany
2022	J	`jnl`	Optimal Clipping and Magnitude-aware Differentiation for Improved Quantization-aware Training. CoRR Charbel Sakr, Steve Dai, Rangharajan Venkatesan, Brian Zimmer, William J. Dally, Brucek Khailany
2021	J	`jnl`	Evolution of the Graphics Processing Unit (GPU). IEEE Micro William J. Dally, Stephen W. Keckler, David Blair Kirk
2021	J	`jnl`	OP-VENT: A Low-Cost, Easily Assembled, Open-Source Medical Ventilator. GetMobile Mob. Comput. Commun. William J. Dally
2021	J	`jnl`	PatchNet - Short-range Template Matching for Efficient Video Processing. CoRR Huizi Mao, Sibo Zhu, Song Han, William J. Dally
2021	B	`conf`	SPAA'21 Panel Paper: Architecture-Friendly Algorithms versus Algorithm-Friendly Architectures. SPAA Guy E. Blelloch, William J. Dally, Margaret Martonosi, Uzi Vishkin, Katherine A. Yelick
2021	J	`jnl`	Simba: scaling deep-learning inference with chiplet-based architecture. Commun. ACM Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler
2021	—	`conf`	VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. MLSys Steve Dai, Rangharajan Venkatesan, Mark Ren, Brian Zimmer, William J. Dally, Brucek Khailany
2021	J	`jnl`	VS-Quant: Per-vector Scaled Quantization for Accurate Low-Precision Neural Network Inference. CoRR Steve Dai, Rangharajan Venkatesan, Haoxing Ren, Brian Zimmer, William J. Dally, Brucek Khailany
2020	J	`jnl`	A 0.32-128 TOPS, Scalable Multi-Chip-Module-Based Deep Neural Network Inference Accelerator With Ground-Referenced Signaling in 16 nm. IEEE J. Solid State Circuits Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
2020	J	`jnl`	Accelerating Chip Design With Machine Learning. IEEE Micro Brucek Khailany, Haoxing Ren, Steve Dai, Saad Godil, Ben Keller, Robert Kirby, Alicia Klinefelter, Rangharajan Venkatesan, Yanqing Zhang, Bryan Catanzaro, William J. Dally
2020	J	`jnl`	Domain-specific hardware accelerators. Commun. ACM William J. Dally, Yatish Turakhia, Song Han
2020	J	`jnl`	Energy Efficient On-Demand Dynamic Branch Prediction Models. IEEE Trans. Computers Milad Mohammadi, Song Han, Ehsan Atoofian, Amirali Baniasadi, Tor M. Aamodt, William J. Dally
2020	C	`conf`	Optimal Operation of a Plug-in Hybrid Vehicle with Battery Thermal and Degradation Model. ACC Jongho Kim, Youngsuk Park, John D. Fox, Stephen P. Boyd, William J. Dally
2020	A*	`conf`	SpArch: Efficient Architecture for Sparse Matrix Multiplication. HPCA Zhekai Zhang, Hanrui Wang, Song Han, William J. Dally
2020	J	`jnl`	SpArch: Efficient Architecture for Sparse Matrix Multiplication. CoRR Zhekai Zhang, Hanrui Wang, Song Han, William J. Dally
2019	—	`conf`	A 0.11 PJ/OP, 0.32-128 Tops, Scalable Multi-Chip-Module-Based Deep Neural Network Accelerator Designed with A High-Productivity vlsi Methodology. Hot Chips Symposium Rangharajan Venkatesan, Yakun Sophia Shao, Brian Zimmer, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
2019	—	`conf`	A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep Neural Network Accelerator with Ground-Reference Signaling in 16nm. VLSI Circuits Brian Zimmer, Rangharajan Venkatesan, Yakun Sophia Shao, Jason Clemons, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Stephen W. Keckler, Brucek Khailany
2019	J	`jnl`	A 1.17-pJ/b, 25-Gb/s/pin Ground-Referenced Single-Ended Serial Link for Off- and On-Package Communication Using a Process- and Temperature-Adaptive Voltage Regulator. IEEE J. Solid State Circuits John W. Poulton, John M. Wilson, Walker J. Turner, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally
2019	—	`conf`	A 2-to-20 GHz Multi-Phase Clock Generator with Phase Interpolators Using Injection-Locked Oscillation Buffers for High-Speed IOs in 16nm FinFET. CICC Sanquan Song, John Poulton, Xi Chen, Brian Zimmer, Stephen G. Tell, Walker J. Turner, Sudhir S. Kudva, Nikola Nedovic, John M. Wilson, C. Thomas Gray, William J. Dally
2019	J	`jnl`	A Delay Metric for Video Object Detection: What Average Precision Fails to Tell. CoRR Huizi Mao, Xiaodong Yang, William J. Dally
2019	—	`conf`	A Fine-Grained GALS SoC with Pausible Adaptive Clocking in 16 nm FinFET. ASYNC Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Stephen G. Tell, Brian Zimmer, Tezaswi Raja, Kevin Zhou, William J. Dally, Brucek Khailany
2019	A*	`conf`	Analog/Mixed-Signal Hardware Error Modeling for Deep Learning Inference. DAC Angad S. Rekhi, Brian Zimmer, Nikola Nedovic, Ningxi Liu, Rangharajan Venkatesan, Miaorong Wang, Brucek Khailany, William J. Dally, C. Thomas Gray
2019	A*	`conf`	Darwin-WGA: A Co-processor Provides Increased Sensitivity in Whole Genome Alignments with High Speedup. HPCA Yatish Turakhia, Sneha D. Goenka, Gill Bejerano, William J. Dally
2019	—	`conf`	Darwin: A Genomics Co-processor Provides up to 15, 000X Acceleration on Long Read Assembly. USENIX ATC Yatish Turakhia, Gill Bejerano, William J. Dally
2019	J	`jnl`	Darwin: A Genomics Coprocessor. IEEE Micro Yatish Turakhia, Gill Bejerano, William J. Dally
2019	A	`conf`	MAGNet: A Modular Accelerator Generator for Neural Networks. ICCAD Rangharajan Venkatesan, Yakun Sophia Shao, Miaorong Wang, Jason Clemons, Steve Dai, Matthew Fojtik, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Yanqing Zhang, Brian Zimmer, William J. Dally, Joel S. Emer, Stephen W. Keckler, Brucek Khailany
2019	A*	`conf`	Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture. MICRO Yakun Sophia Shao, Jason Clemons, Rangharajan Venkatesan, Brian Zimmer, Matthew Fojtik, Nan Jiang, Ben Keller, Alicia Klinefelter, Nathaniel Ross Pinckney, Priyanka Raina, Stephen G. Tell, Yanqing Zhang, William J. Dally, Joel S. Emer, C. Thomas Gray, Brucek Khailany, Stephen W. Keckler
2018	—	`conf`	A 1.17pJ/b 25Gb/s/pin ground-referenced single-ended serial link for off- and on-package communication in 16nm CMOS using a process- and temperature-adaptive voltage regulator. ISSCC John M. Wilson, Walker J. Turner, John W. Poulton, Brian Zimmer, Xi Chen, Sudhir S. Kudva, Sanquan Song, Stephen G. Tell, Nikola Nedovic, Wenxu Zhao, Sunil R. Sudhakaran, C. Thomas Gray, William J. Dally
2018	A*	`conf`	Bandwidth-efficient deep learning. DAC Song Han, William J. Dally
2018	J	`jnl`	CaTDet: Cascaded Tracked Detector for Efficient Object Detection from Video. CoRR Huizi Mao, Taeyoung Kong, William J. Dally
2018	A*	`conf`	Darwin: A Genomics Co-processor Provides up to 15, 000X Acceleration on Long Read Assembly. ASPLOS Yatish Turakhia, Gill Bejerano, William J. Dally
2018	—	`conf`	Efficient Sparse-Winograd Convolutional Neural Networks. ICLR (Poster) Xingyu Liu, Jeff Pool, Song Han, William J. Dally
2018	J	`jnl`	Efficient Sparse-Winograd Convolutional Neural Networks. CoRR Xingyu Liu, Jeff Pool, Song Han, William J. Dally
2018	—	`conf`	Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects. CICC Walker J. Turner, John W. Poulton, John M. Wilson, Xi Chen, Stephen G. Tell, Matthew Fojtik, Thomas H. Greer, Brian Zimmer, Sanquan Song, Nikola Nedovic, Sudhir S. Kudva, Sunil R. Sudhakaran, Rizwan Bashirullah, Wenxu Zhao, William J. Dally, C. Thomas Gray
2018	—	`conf`	Hardware-Enabled Artificial Intelligence. VLSI Circuits William J. Dally, C. Thomas Gray, John Poulton, Brucek Khailany, John M. Wilson, Larry R. Dennison
2018	J	`jnl`	Optimal Operation of a Plug-In Hybrid Vehicle. IEEE Trans. Veh. Technol. Jason A. Platt, Nicholas Moehle, John D. Fox, William J. Dally
2017	A*	`conf`	Architecting an Energy-Efficient DRAM System for GPUs. HPCA Niladrish Chatterjee, Mike O'Connor, Donghyuk Lee, Daniel R. Johnson, Stephen W. Keckler, Minsoo Rhu, William J. Dally
2017	J	`jnl`	CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution Near In-Order Energy with Near Out-of-Order Performance. ACM Trans. Archit. Code Optim. Milad Mohammadi, Tor M. Aamodt, William J. Dally
2017	—	`conf`	DSD: Dense-Sparse-Dense Training for Deep Neural Networks. ICLR (Poster) Song Han, Jeff Pool, Sharan Narang, Huizi Mao, Enhao Gong, Shijian Tang, Erich Elsen, Peter Vajda, Manohar Paluri, John Tran, Bryan Catanzaro, William J. Dally
2017	J	`jnl`	Deep Generative Adversarial Networks for Compressed Sensing Automates MRI. CoRR Morteza Mardani, Enhao Gong, Joseph Y. Cheng, Shreyas Vasanawala, Greg Zaharchuk, Marcus T. Alley, Neil Thakur, Song Han, William J. Dally, John M. Pauly, Lei Xing
2017	J	`jnl`	Deep Gradient Compression: Reducing the Communication Bandwidth for Distributed Training. CoRR Yujun Lin, Song Han, Huizi Mao, Yu Wang, William J. Dally
2017	—	`conf`	Efficient Sparse-Winograd Convolutional Neural Networks. ICLR (Workshop) Xingyu Liu, Song Han, Huizi Mao, William J. Dally
2017	—	`conf`	Exploring the Granularity of Sparsity in Convolutional Neural Networks. CVPR Workshops Huizi Mao, Song Han, Jeff Pool, Wenshuo Li, Xingyu Liu, Yu Wang, William J. Dally
2017	J	`jnl`	Exploring the Regularity of Sparse Structure in Convolutional Neural Networks. CoRR Huizi Mao, Song Han, Jeff Pool, Wenshuo Li, Xingyu Liu, Yu Wang, William J. Dally
2017	A*	`conf`	Fine-grained DRAM: energy-efficient DRAM for extreme bandwidth systems. MICRO Mike O'Connor, Niladrish Chatterjee, Donghyuk Lee, John M. Wilson, Aditya Agrawal, Stephen W. Keckler, William J. Dally
2017	J	`jnl`	HoLiSwap: Reducing Wire Energy in L1 Caches. CoRR Yatish Turakhia, Subhasis Das, Tor M. Aamodt, William J. Dally
2017	A*	`conf`	SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. ISCA Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally
2017	J	`jnl`	SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks. CoRR Angshuman Parashar, Minsoo Rhu, Anurag Mukkara, Antonio Puglielli, Rangharajan Venkatesan, Brucek Khailany, Joel S. Emer, Stephen W. Keckler, William J. Dally
2017	—	`conf`	Trained Ternary Quantization. ICLR (Poster) Chenzhuo Zhu, Song Han, Huizi Mao, William J. Dally
2016	—	`conf`	8.6 A 6.5-to-23.3fJ/b/mm balanced charge-recycling bus in 16nm FinFET CMOS at 1.7-to-2.6Gb/s/wire with clock forwarding and low-crosstalk contraflow wiring. ISSCC John M. Wilson, Matthew R. Fojtik, John W. Poulton, Xi Chen, Stephen G. Tell, Thomas H. Greer, C. Thomas Gray, William J. Dally
2016	J	`jnl`	A 28 nm 2 Mbit 6 T SRAM With Highly Configurable Low-Voltage Write-Ability Assist Implementation and Capacitor-Based Sense-Amplifier Input Offset Compensation. IEEE J. Solid State Circuits Mahmut E. Sinangil, John W. Poulton, Matthew R. Fojtik, Thomas H. Greer, Stephen G. Tell, Andreas J. Gotterba, Jesse Wang, Jason Golbus, Brian Zimmer, William J. Dally, C. Thomas Gray
2016	J	`jnl`	CG-OoO: Energy-Efficient Coarse-Grain Out-of-Order Execution. CoRR Milad Mohammadi, Tor M. Aamodt, William J. Dally
2016	J	`jnl`	DSD: Regularizing Deep Neural Networks with Dense-Sparse-Dense Training Flow. CoRR Song Han, Jeff Pool, Sharan Narang, Huizi Mao, Shijian Tang, Erich Elsen, Bryan Catanzaro, John Tran, William J. Dally
2016	A*	`conf`	Deep Compression: Compressing Deep Neural Network with Pruning, Trained Quantization and Huffman Coding. ICLR Song Han, Huizi Mao, William J. Dally
2016	A*	`conf`	EIE: Efficient Inference Engine on Compressed Deep Neural Network. ISCA Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally
2016	J	`jnl`	EIE: Efficient Inference Engine on Compressed Deep Neural Network. CoRR Song Han, Xingyu Liu, Huizi Mao, Jing Pu, Ardavan Pedram, Mark A. Horowitz, William J. Dally
2016	J	`jnl`	ESE: Efficient Speech Recognition Engine with Compressed LSTM on FPGA. CoRR Song Han, Junlong Kang, Huizi Mao, Yiming Hu, Xin Li, Yubin Li, Dongliang Xie, Hong Luo, Song Yao, Yu Wang, Huazhong Yang, William J. Dally
2016	J	`jnl`	Reuse Distance-Based Probabilistic Cache Replacement. ACM Trans. Archit. Code Optim. Subhasis Das, Tor M. Aamodt, William J. Dally
2016	J	`jnl`	SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and <1MB model size. CoRR Forrest N. Iandola, Matthew W. Moskewicz, Khalid Ashraf, Song Han, William J. Dally, Kurt Keutzer
2016	J	`jnl`	Trained Ternary Quantization. CoRR Chenzhuo Zhu, Song Han, Huizi Mao, William J. Dally
2015	—	`conf`	Learning both Weights and Connections for Efficient Neural Network. NIPS Song Han, Jeff Pool, John Tran, William J. Dally
2015	J	`jnl`	Learning both Weights and Connections for Efficient Neural Networks. CoRR Song Han, Jeff Pool, John Tran, William J. Dally
2015	A	`conf`	Network endpoint congestion control for fine-grained communication. SC Nan Jiang, Larry R. Dennison, William J. Dally
2015	J	`jnl`	On-Chip Active Messages for Speed, Scalability, and Efficiency. IEEE Trans. Parallel Distributed Syst. R. Curtis Harting, William J. Dally
2015	J	`jnl`	On-Demand Dynamic Branch Prediction. IEEE Comput. Archit. Lett. Milad Mohammadi, Song Han, Tor M. Aamodt, William J. Dally
2015	A*	`conf`	SLIP: reducing wire energy in the memory hierarchy. ISCA Subhasis Das, Tor M. Aamodt, William J. Dally
2014	—	`conf`	Author retrospective for design tradeoffs for tiled CMP on-chip networks. ICS 25th Anniversary William J. Dally, James D. Balfour
2014	A	`conf`	Scaling the Power Wall: A Path to Exascale. SC Oreste Villa, Daniel R. Johnson, Mike O'Connor, Evgeny Bolotin, David W. Nellans, Justin Luitjens, Nikolai Sakharnykh, Peng Wang, Paulius Micikevicius, Anthony Scudiero, Stephen W. Keckler, William J. Dally
2013	A*	`conf`	21st century digital design tools. DAC William J. Dally, Chris Malachowsky, Stephen W. Keckler
2013	J	`jnl`	A 0.54 pJ/b 20 Gb/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications. IEEE J. Solid State Circuits John W. Poulton, William J. Dally, Xi Chen, John G. Eyles, Thomas H. Greer, Stephen G. Tell, John M. Wilson, C. Thomas Gray
2013	—	`conf`	A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications. ISSCC John W. Poulton, William J. Dally, Xi Chen, John G. Eyles, Thomas H. Greer, Stephen G. Tell, C. Thomas Gray
2013	B	`conf`	A detailed and flexible cycle-accurate Network-on-Chip simulator. ISPASS Nan Jiang, Daniel U. Becker, George Michelogiannakis, James D. Balfour, Brian Towles, David E. Shaw, John Kim, William J. Dally
2013	A	`conf`	Channel reservation protocol for over-subscribed channels and destinations. SC George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally
2013	J	`jnl`	Elastic Buffer Flow Control for On-Chip Networks. IEEE Trans. Computers George Michelogiannakis, William J. Dally
2012	J	`jnl`	A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors. ACM Trans. Comput. Syst. Mark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron
2012	C	`conf`	Adaptive Backpressure: Efficient buffer management for on-chip networks. ICCD Daniel U. Becker, Nan Jiang, George Michelogiannakis, William J. Dally
2012	A*	`conf`	Network congestion avoidance through Speculative Reservation. HPCA Nan Jiang, Daniel U. Becker, George Michelogiannakis, William J. Dally
2012	A*	`conf`	Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor. MICRO Mark Gebhart, Stephen W. Keckler, Brucek Khailany, Ronny Krashinsky, William J. Dally
2011	A*	`conf`	A compile-time managed multi-level register file hierarchy. MICRO Mark Gebhart, Stephen W. Keckler, William J. Dally
2011	A*	`conf`	Energy-efficient mechanisms for managing thread context in throughput processors. ISCA Mark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron
2011	J	`jnl`	Evaluating Elastic Buffer and Wormhole Flow Control. IEEE Trans. Computers George Michelogiannakis, Daniel Becker, William J. Dally
2011	J	`jnl`	GPUs and the Future of Parallel Computing. IEEE Micro Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco
2011	J	`jnl`	Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks. IEEE Comput. Archit. Lett. George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally
2011	A*	`conf`	Packet chaining: efficient single-cycle allocation for on-chip networks. MICRO George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally
2011	A	`conf`	Panel Statement. IPDPS Yves Robert, William J. Dally, Jack J. Dongarra, Satoshi Matsuoka, Robert Schreiber, Horst D. Simon, Uzi Vishkin
2011	—	`conf`	The utility of fast active messages on many-core chips: Efficient supercomputing project. Hot Chips Symposium R. Curtis Harting, Vishal Parikh, William J. Dally
2010	B	`conf`	Block-Parallel Programming for Real-Time Embedded Applications. ICPP David Black-Schaffer, William J. Dally
2010	B	`conf`	Buffer-space efficient and deadlock-free scheduling of stream applications on multi-core architectures. SPAA Jongsoo Park, William J. Dally
2010	—	`conf`	Evaluating Bufferless Flow Control for On-chip Networks. NOCS George Michelogiannakis, Daniel Sánchez, William J. Dally, Christos Kozyrakis
2010	Misc	`conf`	Fine-grain dynamic instruction placement for L0 scratch-pad memory. CASES Jongsoo Park, James D. Balfour, William J. Dally
2010	A*	`conf`	Moving the needle, computer architecture research in academe and industry. ISCA William J. Dally
2010	—	`conf`	The Even/Odd Synchronizer: A Fast, All-Digital, Periodic Synchronizer. ASYNC William J. Dally, Stephen G. Tell
2010	J	`jnl`	The GPU Computing Era. IEEE Micro John Nickolls, William J. Dally
2010	A	`conf`	Throughput computing. ICS William J. Dally
2009	A	`conf`	Allocator implementations for network-on-chip routers. SC Daniel U. Becker, William J. Dally
2009	J	`jnl`	Cost-Efficient Dragonfly Topology for Large-Scale Systems. IEEE Micro John Kim, William J. Dally, Steve Scott, Dennis Abts
2009	A*	`conf`	Elastic-buffer flow control for on-chip networks. HPCA George Michelogiannakis, James D. Balfour, William J. Dally
2009	A*	`conf`	Indirect adaptive routing on large scale interconnection networks. ISCA Nan Jiang, John Kim, William J. Dally
2009	J	`jnl`	Operand Registers and Explicit Operand Forwarding. IEEE Comput. Archit. Lett. James D. Balfour, R. C. Halting, William J. Dally
2009	A	`conf`	Router designs for elastic buffer on-chip networks. SC George Michelogiannakis, William J. Dally
2009	—	`ch.`	Stream Processors. Multicore Processors and Systems Mattan Erez, William J. Dally
2008	J	`jnl`	A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing. IEEE J. Solid State Circuits Brucek Khailany, Ted Williams, Jim Lin, Eileen Peters Long, Mark Rygh, DeForest Tovey, William J. Dally
2008	B	`conf`	A portable runtime interface for multi-level memory hierarchies. PPoPP Mike Houston, Ji Young Park, Manman Ren, Timothy J. Knight, Kayvon Fatahalian, Alex Aiken, William J. Dally, Pat Hanrahan
2008	B	`conf`	A tuning framework for software-managed memory hierarchies. PACT Manman Ren, Ji Young Park, Mike Houston, Alex Aiken, William J. Dally
2008	J	`jnl`	An Energy-Efficient Processor Architecture for Embedded Systems. IEEE Comput. Archit. Lett. James D. Balfour, William J. Dally, David Black-Schaffer, Vishal Parikh, Jongsoo Park
2008	J	`jnl`	Efficient Embedded Computing. Computer William J. Dally, James D. Balfour, David Black-Schaffer, James Chen, R. Curtis Harting, Vishal Parikh, Jongsoo Park, David Sheffield
2008	J	`jnl`	Hierarchical Instruction Register Organization. IEEE Comput. Archit. Lett. David Black-Schaffer, James D. Balfour, William J. Dally, Vishal Parikh, Jongsoo Park
2008	—	`conf`	Stream Scheduling: A Framework to Manage Bulk Operations in Memory Hierarchies. Euro-Par Abhishek Das, William J. Dally
2008	A*	`conf`	Technology-Driven, Highly-Scalable Dragonfly Topology. ISCA John Kim, William J. Dally, Steve Scott, Dennis Abts
2007	J	`jnl`	A 14-mW 6.25-Gb/s Transceiver in 90-nm CMOS. IEEE J. Solid State Circuits John Poulton, Robert Palmer, Andrew M. Fuller, Trey Greer, John G. Eyles, William J. Dally, Mark Horowitz
2007	—	`conf`	A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications. ISSCC Robert Palmer, John Poulton, William J. Dally, John G. Eyles, Andrew M. Fuller, Trey Greer, Mark Horowitz, Mark Kellam, F. Quan, F. Zarkeshvari
2007	—	`conf`	A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing. ISSCC Brucek Khailany, Ted Williams, Jim Lin, Eileen Long, Mark Rygh, DeForest Tovey, William J. Dally
2007	B	`conf`	Architectural Support for the Stream Execution Model on General-Purpose Processors. PACT Jayanth Gummaraju, Mattan Erez, Joel Coburn, Mendel Rosenblum, William J. Dally
2007	B	`conf`	Compilation for explicitly managed memory hierarchies. PPoPP Timothy J. Knight, Ji Young Park, Manman Ren, Mike Houston, Mattan Erez, Kayvon Fatahalian, Alex Aiken, William J. Dally, Pat Hanrahan
2007	—	`conf`	Enabling Technology for On-Chip Interconnection Networks. NOCS William J. Dally
2007	A	`conf`	Executing irregular scientific applications on stream architectures. ICS Mattan Erez, Jung Ho Ahn, Jayanth Gummaraju, Mendel Rosenblum, William J. Dally
2007	A*	`conf`	Flattened Butterfly Topology for On-Chip Networks. MICRO John Kim, James D. Balfour, William J. Dally
2007	J	`jnl`	Flattened Butterfly Topology for On-Chip Networks. IEEE Comput. Archit. Lett. John Kim, James D. Balfour, William J. Dally
2007	A*	`conf`	Flattened butterfly: a cost-efficient topology for high-radix networks. ISCA John Kim, William J. Dally, Dennis Abts
2007	A	`conf`	Future of on-chip interconnection architectures. ISLPED Shekhar Borkar, William J. Dally
2007	A*	`conf`	Interconnect-Centric Computing. HPCA William J. Dally
2007	A	`conf`	Register pointer architecture for efficient embedded processors. DATE Jongsoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally
2007	J	`jnl`	Research Challenges for On-Chip Interconnection Networks. IEEE Micro John D. Owens, William J. Dally, Ron Ho, Doddaballapur Narasimha-Murthy Jayasimha, Stephen W. Keckler, Li-Shiuan Peh
2007	B	`conf`	Stream Scheduling: A Framework to Manage Bulk Operations in a Memory Hierarchy. PACT Abhishek Das, William J. Dally
2007	A	`conf`	Tradeoff between data-, instruction-, and thread-level parallelism in stream processors. ICS Jung Ho Ahn, Mattan Erez, William J. Dally
2006	A	`conf`	Architecture - The design space of data-parallel memory systems. SC Jung Ho Ahn, Mattan Erez, William J. Dally
2006	B	`conf`	Compiling for stream processing. PACT Abhishek Das, William J. Dally, Peter R. Mattson
2006	C	`conf`	Computer Architecture in the Many-Core Era. ICCD William J. Dally
2006	J	`jnl`	Data parallel address architecture. IEEE Comput. Archit. Lett. Jung Ho Ahn, William J. Dally
2006	A	`conf`	Design tradeoffs for tiled CMP on-chip networks. ICS James D. Balfour, William J. Dally
2006	A	`conf`	Interconnect routing and scheduling - Adaptive routing in high-radix clos network. SC John Kim, William J. Dally, Dennis Abts
2006	A	`conf`	Multi-core issues - Multi-Core for HPC: breakthrough or breakdown? SC Thomas L. Sterling, Peter M. Kogge, William J. Dally, Steve Scott, William Gropp, David E. Keyes, Peter H. Beckman
2006	—	`conf`	Pulsenet - A Parallel Flash Sampler and Digital Processor IC for Optical SETI. CICC Andrew W. Howard, Gu-Yeon Wei, William J. Dally, Paul Horowitz
2006	A	`conf`	Sequoia: programming the memory hierarchy. SC Kayvon Fatahalian, Daniel Reiter Horn, Timothy J. Knight, Larkhoon Leem, Mike Houston, Ji Young Park, Mattan Erez, Manman Ren, Alex Aiken, William J. Dally, Pat Hanrahan
2006	A*	`conf`	The BlackWidow High-Radix Clos Network. ISCA Steve Scott, Dennis Abts, John Kim, William J. Dally
2006	J	`jnl`	Topology optimization of interconnection networks. IEEE Comput. Archit. Lett. Amit K. Gupta, William J. Dally
2005	J	`jnl`	A 20-Gb/s 0.13-μm CMOS serial link transmitter using an LC-PLL to directly drive the output multiplexer. IEEE J. Solid State Circuits Patrick Chiang, William J. Dally, Ming-Ju Edward Lee, Ramesh Senthinathan, Yangjin Oh, Mark A. Horowitz
2005	A*	`conf`	Explaining the gap between ASIC and custom power: a custom perspective. DAC Andrew Chang, William J. Dally
2005	A	`conf`	Fault Tolerance Techniques for the Merrimac Streaming Supercomputer. SC Mattan Erez, Nuwan Jayasena, Timothy J. Knight, William J. Dally
2005	J	`jnl`	Hot Chips 16: Power, Parallelism, and Memory Performance. IEEE Micro William J. Dally, Keith Diefendorff
2005	A*	`conf`	Microarchitecture of a High-Radix Router. ISCA John Kim, William J. Dally, Brian Towles, Amit K. Gupta
2005	A*	`conf`	Scatter-Add in Data Parallel Architectures. HPCA Jung Ho Ahn, Mattan Erez, William J. Dally
2004	J	`jnl`	A 33-mW 8-Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. IEEE J. Solid State Circuits Ramin Farjad-Rad, Anhtuyet Nguyen, James Tran, Trey Greer, John Poulton, William J. Dally, John H. Edmondson, Ramesh Senthinathan, Rohit Rathi, Ming-Ju Edward Lee, Hiok-Tiaq Ng
2004	B	`conf`	Adaptive channel queue routing on k-ary n-cubes. SPAA Arjun Singh, William J. Dally, Amit K. Gupta, Brian Towles
2004	A	`conf`	Analysis and Performance Results of a Molecular Modeling Application on Merrimac. SC Mattan Erez, Jung Ho Ahn, Ankit Garg, William J. Dally, Eric Darve
2004	J	`jnl`	Buffer and Delay Bounds in High Radix Interconnection Networks. IEEE Comput. Archit. Lett. Arjun Singh, William J. Dally
2004	A*	`conf`	Evaluating the Imagine Stream Architecture. ISCA Jung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, Abhishek Das
2004	J	`jnl`	Globally Adaptive Load-Balanced Routing on Tori. IEEE Comput. Archit. Lett. Arjun Singh, William J. Dally, Brian Towles, Amit K. Gupta
2004	J	`jnl`	Stream Processors: Progammability and Efficiency. ACM Queue William J. Dally, Ujval J. Kapasi, Brucek Khailany, Jung Ho Ahn, Abhishek Das
2004	A*	`conf`	Stream Register Files with Indexed Access. HPCA Nuwan Jayasena, Mattan Erez, Jung Ho Ahn, William J. Dally
2004	Misc	`conf`	The case for broader computer architecture education: keynote address. WCAE William J. Dally
2003	—	`conf`	A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os. CICC Hiok-Tiaq Ng, Ming-Ju Edward Lee, Ramin Farjad-Rad, Ramesh Senthinathan, William J. Dally, Anhtuyet Nguyen, Rohit Rathi, Trey Greer, John Poulton, John H. Edmondson, James Tran
2003	J	`jnl`	A second-order semidigital clock recovery circuit based on injection locking. IEEE J. Solid State Circuits Hiok-Tiaq Ng, Ramin Farjad-Rad, Ming-Ju Edward Lee, William J. Dally, Trey Greer, John Poulton, John H. Edmondson, Rohit Rathi, Ramesh Senthinathan
2003	C	`conf`	CMOS High-Speed I/Os - Present and Future. ICCD Ming-Ju Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John W. Poulton
2003	A*	`conf`	Exploring the VLSI Scalability of Stream Processors. HPCA Brucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens, Brian Towles
2003	A*	`conf`	GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks. ISCA Arjun Singh, William J. Dally, Amit K. Gupta, Brian Towles
2003	J	`jnl`	Guaranteed scheduling for switches with configuration overhead. IEEE/ACM Trans. Netw. Brian Towles, William J. Dally
2003	J	`jnl`	Jitter transfer characteristics of delay-locked loops - theories and design techniques. IEEE J. Solid State Circuits Ming-Ju Edward Lee, William J. Dally, Trey Greer, Hiok-Tiaq Ng, Ramin Farjad-Rad, John Poulton, Ramesh Senthinathan
2003	A	`conf`	Merrimac: Supercomputing with Streams. SC William J. Dally, Francois Labonte, Abhishek Das, Pat Hanrahan, Jung Ho Ahn, Jayanth Gummaraju, Mattan Erez, Nuwan Jayasena, Ian Buck, Timothy J. Knight, Ujval J. Kapasi
2003	J	`jnl`	Programmable Stream Processors. Computer Ujval J. Kapasi, Scott Rixner, William J. Dally, Brucek Khailany, Jung Ho Ahn, Peter R. Mattson, John D. Owens
2003	B	`conf`	Throughput-centric routing algorithm design. SPAA Brian Towles, William J. Dally, Stephen P. Boyd
2002	C	`conf`	A Stream Processor Development Platform. ICCD Ben Serebrin, John D. Owens, Chen H. Chen, Stephen P. Crago, Ujval J. Kapasi, Peter R. Mattson, Jinyung Namkoong, Scott Rixner, William J. Dally
2002	J	`jnl`	A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips. IEEE J. Solid State Circuits Ramin Farjad-Rad, William J. Dally, Hiok-Tiaq Ng, Ramesh Senthinathan, Ming-Ju Edward Lee, Rohit Rathi, John Poulton
2002	—	`conf`	Comparing Reyes and OpenGL on a Stream Architecture. Graphics Hardware John D. Owens, Brucek Khailany, Brian Towles, William J. Dally
2002	A*	`conf`	Guaranteed Scheduling for Switches with Configuration Overhead. INFOCOM Brian Towles, William J. Dally
2002	B	`conf`	Locality-preserving randomized oblivious routing on torus networks. SPAA Arjun Singh, William J. Dally, Brian Towles, Amit K. Gupta
2002	C	`conf`	Media Processing Applications on the Imagine Stream Processor. ICCD John D. Owens, Scott Rixner, Ujval J. Kapasi, Peter R. Mattson, Brian Towles, Ben Serebrin, William J. Dally
2002	J	`jnl`	Migration in Single Chip Multiprocessors. IEEE Comput. Archit. Lett. Kelly A. Shaw, William J. Dally
2002	—	`conf`	Scalable Opto-Electronic Network (SOENet). Hot Interconnects Amit K. Gupta, William J. Dally, Arjun Singh, Brian Towles
2002	C	`conf`	The Imagine Stream Processor. ICCD Ujval J. Kapasi, William J. Dally, Scott Rixner, John D. Owens, Brucek Khailany
2002	C	`conf`	VLSI Design and Verification of the Imagine Processor. ICCD Brucek Khailany, William J. Dally, Andrew Chang, Ujval J. Kapasi, Jinyung Namkoong, Brian Towles
2002	J	`jnl`	Worst-case Traffic for Oblivious Routing Functions. IEEE Comput. Archit. Lett. Brian Towles, William J. Dally
2002	B	`conf`	Worst-case traffic for oblivious routing functions. SPAA Brian Towles, William J. Dally
2001	A*	`conf`	A Delay Model and Speculative Architecture for Pipelined Routers. HPCA Li-Shiuan Peh, William J. Dally
2001	J	`jnl`	A Delay Model for Router Microarchitectures. IEEE Micro Li-Shiuan Peh, William J. Dally
2001	—	`book`	Digital systems engineering. William J. Dally, John W. Poulton
2001	J	`jnl`	Guest Editors' Introduction: Hot Chips 12. IEEE Micro William J. Dally, Marc Tremblay, Allen J. Baum
2001	J	`jnl`	Imagine: Media Processing with Streams. IEEE Micro Brucek Khailany, William J. Dally, Ujval J. Kapasi, Peter R. Mattson, Jinyung Namkoong, John D. Owens, Brian Towles, Andrew Chang, Scott Rixner
2001	—	`conf`	Monolithic chaotic communications system. ISCAS (3) Patrick Chiang, William J. Dally, Ming-Ju Edward Lee
2001	A*	`conf`	Route Packets, Not Wires: On-Chip Interconnection Networks. DAC William J. Dally, Brian Towles
2000	A*	`conf`	Communication Scheduling. ASPLOS Peter R. Mattson, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens
2000	A*	`conf`	Efficient conditional operations for data-parallel architectures. MICRO Ujval J. Kapasi, William J. Dally, Scott Rixner, Peter R. Mattson, John D. Owens, Brucek Khailany
2000	A*	`conf`	Flit-Reservation Flow Control. HPCA Li-Shiuan Peh, William J. Dally
2000	J	`jnl`	Low-power area-efficient high-speed I/O circuit techniques. IEEE J. Solid State Circuits Ming-Ju Edward Lee, William J. Dally, Patrick Chiang
2000	A*	`conf`	Memory access scheduling. ISCA Scott Rixner, William J. Dally, Ujval J. Kapasi, Peter R. Mattson, John D. Owens
2000	—	`conf`	Polygon Rendering on a Stream Architecture. Workshop on Graphics Hardware John D. Owens, William J. Dally, Ujval J. Kapasi, Scott Rixner, Peter R. Mattson, Ben Mowery
2000	—	`conf`	Processor Mechanisms for Software Shared Memory. ISHPC Nicholas P. Carter, William J. Dally, Whay Sing Lee, Stephen W. Keckler, Andrew Chang
2000	A*	`conf`	Register Organization for Media Processing. HPCA Scott Rixner, William J. Dally, Brucek Khailany, Peter R. Mattson, Ujval J. Kapasi, John D. Owens
2000	A*	`conf`	Smart Memories: a modular reconfigurable architecture. ISCA Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, Mark Horowitz
2000	A*	`conf`	The role of custom design in ASIC Chips. DAC William J. Dally, Andrew Chang
1999	J	`jnl`	Concurrent Event Handling through Multithreading. IEEE Trans. Computers Stephen W. Keckler, Andrew Chang, Whay Sing Lee, Sandeep Chatterjee, William J. Dally
1999	A*	`ed.`	Proceedings of the 26th Annual International Symposium on Computer Architecture, ISCA 1999, Atlanta, Georgia, USA, May 2-4, 1999 ISCA Allan Gottlieb, William J. Dally
1999	—	`conf`	VLSI Architecture: Past, Present, and Future. ARVLSI William J. Dally, Steve Lacy
1998	A*	`conf`	A Bandwidth-efficient Architecture for Media Processing. MICRO Scott Rixner, William J. Dally, Ujval J. Kapasi, Brucek Khailany, Abelardo López-Lagunas, Peter R. Mattson, John D. Owens
1998	J	`jnl`	A tracking clock recovery receiver for 4-Gbps signaling. IEEE Micro John Poulton, William J. Dally, Steve Tell
1998	J	`jnl`	An Efficient, Protected Message Interface. Computer Whay Sing Lee, William J. Dally, Stephen W. Keckler, Nicholas P. Carter, Andrew Chang
1998	—	`conf`	Architecture of a Message-Driven Processor. 25 Years ISCA: Retrospectives and Reprints William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills
1998	A*	`conf`	Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor. ISCA Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, Whay Sing Lee
1998	—	`conf`	Point Sample Rendering. Rendering Techniques J. P. Grossman, William J. Dally
1998	—	`conf`	Retrospective: the J-machine. 25 Years ISCA: Retrospectives and Reprints William J. Dally, Andrew A. Chien, Stuart Fiske, Waldemar Horwat, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, Ellen Spertus, Deborah A. Wallach, D. Scott Wills, Andrew Chang, John S. Keen
1998	J	`jnl`	The bleeding edge. IEEE Micro Randall Rettberg, William J. Dally, David E. Culler
1998	C	`conf`	The effects of explicitly parallel mechanisms on the multi-ALU processor cluster pipeline. ICCD Andrew Chang, William J. Dally, Stephen W. Keckler, Nicholas P. Carter, Whay Sing Lee
1997	J	`jnl`	Extended Ehemeral Logging: Log Storage Management for Applications with Long Lived Transactions. ACM Trans. Database Syst. John S. Keen, William J. Dally
1997	J	`jnl`	The M-machine multicomputer. Int. J. Parallel Program. Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, Whay Sing Lee
1997	J	`jnl`	Transmitter equalization for 4-Gbps signaling. IEEE Micro William J. Dally, John W. Poulton
1995	B	`conf`	Evaluating the Locality Benefits of Active Messages. PPoPP Ellen Spertus, William J. Dally
1995	—	`conf`	Low-latency plesiochronous data retiming. ARVLSI Larry R. Dennison, William J. Dally, Thucydides Xanthopoulos
1995	A*	`conf`	The M-Machine multicomputer. MICRO Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, Whay Sing Lee
1995	A*	`conf`	The Named-State Register File: Implementation and Performance. HPCA Peter R. Nuth, William J. Dally
1995	A*	`conf`	Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors. HPCA Stuart Fiske, William J. Dally
1995	J	`jnl`	Thread prioritization: A thread scheduling mechanism for multiple-context parallel processors. Future Gener. Comput. Syst. Stuart Fiske, William J. Dally
1994	—	`conf`	Architecture and implementation of the reliable router. Hot Interconnects William J. Dally, Larry R. Dennison, David Money Harris, Kinhong Kan, Thucydides Xanthopoulos
1994	A*	`conf`	Hardware Support for Fast Capability-based Addressing. ASPLOS Nicholas P. Carter, Stephen W. Keckler, William J. Dally
1994	—	`ch.`	Issues in the Design and Implementation of Instruction Processors for Multicomputers (Position Statement). Multithreaded Computer Architecture William J. Dally
1994	—	`ch.`	Named State and Efficient Context Switching. Multithreaded Computer Architecture Peter R. Nuth, William J. Dally
1994	—	`ch.`	Subspace Optimizations. Automatic Parallelization Kathleen Knobe, William J. Dally
1994	—	`conf`	The Reliable Router: A Reliable and High-Performance Communication Substrate for Parallel Computers. PCRCW William J. Dally, Larry R. Dennison, David Money Harris, Kinhong Kan, Thucydides Xanthopoulos
1994	A	`conf`	XEL: Extended Ephemeral Logging for Log Storage Management. CIKM John S. Keen, William J. Dally
1993	J	`jnl`	A Universal Parallel Computer Architecture. New Gener. Comput. William J. Dally
1993	J	`jnl`	Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels. IEEE Trans. Parallel Distributed Syst. William J. Dally, Hiromichi Aoki
1993	A*	`conf`	Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5. ISCA Ellen Spertus, Seth Copen Goldstein, Klaus E. Schauser, Thorsten von Eicken, David E. Culler, William J. Dally
1993	—	`conf`	Performance Evaluation of Ephemeral Logging. SIGMOD Conference John S. Keen, William J. Dally
1993	A*	`conf`	The J-Machine Multicomputer: An Architectural Evaluation. ISCA Michael D. Noakes, Deborah A. Wallach, William J. Dally
1992	J	`jnl`	A Fast Translation Method for Paging on top of Segmentation. IEEE Trans. Computers William J. Dally
1992	—	`conf`	A Universal Parallel Computer Architecture. FGCS William J. Dally
1992	C	`conf`	MDP Design Tools and Methods. ICCD Richard A. Lethin, William J. Dally
1992	A*	`conf`	Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism. ISCA Stephen W. Keckler, William J. Dally
1992	C	`conf`	The J-Machine Network. ICCD Peter R. Nuth, William J. Dally
1992	C	`conf`	The Message Driven Processor: An Integrated Multicomputer Processing Element. ICCD William J. Dally, Andrew A. Chien, Stuart Fiske, Gregory A. Fyler, Waldemar Horwat, John S. Keen, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, D. Scott Wills
1992	J	`jnl`	The message-driven processor: a multicomputer processing node with efficient mechanisms. IEEE Micro William J. Dally, Stuart Fiske, John S. Keen, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, Roy E. Davison, Gregory A. Fyler
1992	J	`jnl`	Virtual-Channel Flow Control. IEEE Trans. Parallel Distributed Syst. William J. Dally
1991	C	`conf`	A Mechanism for Efficient Context Switching. ICCD Peter R. Nuth, William J. Dally
1991	—	`conf`	Experiences Implementing Dataflow on a General-Purpose Parallel Computer. ICPP (2) Ellen Spertus, William J. Dally
1991	J	`jnl`	Express Cubes: Improving the Performance of k-Ary n-Cube Interconnection Networks. IEEE Trans. Computers William J. Dally
1990	J	`jnl`	A hardware logic simulation system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Prathima Agrawal, William J. Dally
1990	B	`conf`	Concurrent Aggregates (CA). PPoPP Andrew A. Chien, William J. Dally
1990	J	`jnl`	Performance Analysis of k-Ary n-Cube Interconnection Networks. IEEE Trans. Computers William J. Dally
1990	C	`conf`	Simultaneous bidirectional signalling for IC systems. ICCD Kevin Lam, Larry R. Dennison, William J. Dally
1990	A*	`conf`	Virtual-Channel Flow Control. ISCA William J. Dally
1989	A*	`conf`	Algorithms for Accuracy Enhancement in a Hardware Logic Simulator. DAC Prathima Agrawal, Raffi Tutundjian, William J. Dally
1989	A*	`conf`	Experience with CST: Programming and Implementation. PLDI Waldemar Horwat, Andrew A. Chien, William J. Dally
1989	A*	`conf`	Micro-Optimization of Floating Point Operations. ASPLOS William J. Dally
1989	—	`conf`	The J-Machine: A Fine-Gain Concurrent Computer. IFIP Congress William J. Dally, Andrew A. Chien, Stuart Fiske, Waldemar Horwat, John S. Keen, Michael Larivee, Richard A. Lethin, Peter R. Nuth, D. Scott Wills
1989	—	`conf`	Universal Mechanisms for Concurrency. PARLE (1) William J. Dally, D. Scott Wills
1988	—	`conf`	Finite-grain message passing concurrent computers. C³P William J. Dally
1988	—	`conf`	Mechanisms for Concurrent Computing. FGCS William J. Dally
1988	—	`conf`	Object-oriented concurrent programming in CST. C³P William J. Dally, Andrew A. Chien
1988	—	`conf`	Object-oriented concurrent programming in CST. OOPSLA/ECOOP Workshop on Object-based Concurrent Programming William J. Dally, Andrew A. Chien
1988	A*	`conf`	The Reconfigurable Arithmetic Processor. ISCA Stuart Fiske, William J. Dally
1987	A*	`conf`	Architecture and Design of the MARS Hardware Accelerator. DAC Prathima Agrawal, William J. Dally, Ahmed K. Ezzat, W. C. Fischer, H. V. Jagadish, A. S. Krishnakumar
1987	A*	`conf`	Architecture of a Message-Driven Processor. ISCA William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills
1987	J	`jnl`	Deadlock-Free Message Routing in Multiprocessor Interconnection Networks. IEEE Trans. Computers William J. Dally, Charles L. Seitz
1987	J	`jnl`	MARS: A Multiprocessor-Based Programmable Accelerator. IEEE Des. Test Prathima Agrawal, William J. Dally, W. C. Fischer, H. V. Jagadish, A. S. Krishnakumar, Raffi Tutundjian
1986	—	`—`	A VLSI Architecture for Concurrent Data Structures. William J. Dally
1986	J	`jnl`	The Torus Routing Chip. Distributed Comput. William J. Dally, Charles L. Seitz
1985	J	`jnl`	A Hardware Architecture for Switch-Level Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. William J. Dally, Randal E. Bryant
1985	A*	`conf`	An Object Oriented Architecture. ISCA William J. Dally, James T. Kajiya