William Andrew Simon

26 papers A* 2A 2B 2C 4Misc 1Journal 8Unranked 7
YearRankTypeTitle / Venue / Authors
2025 — conf
Analog-AI Hardware Accelerators for Low-Latency Transformer-Based Language Models (Invited).
CICC
Geoffrey W. Burr, H. Tsai, Irem Boybat, William Andrew Simon, Julian Büchel, Athanasios Vasilopoulos, Pritish Narayanan, Andrea Fasoli, Kohji Hosokawa, Manuel Le Gallo, M. Ishii, Yasuteru Kohda, Atsuya Okazaki, A. Chen, Charles Mackin, Elena Ferro, Kaoutar El Maghraoui, Hadjer Benmeziane, T. Philicelli, Corey Lammie, Alexander M. Friz, Jose Luquin, S. Jain, Abu Sebastian, V. Narayanan
2025 J jnl
CiMBA: Accelerating Genome Sequencing Through On-Device Basecalling via Compute-in-Memory.
IEEE Trans. Parallel Distributed Syst.
William Andrew Simon, Irem Boybat, Riselda Kodra, Elena Ferro, Gagandeep Singh, Mohammed Alser, Shubham Jain, Hsinyu Tsai, Geoffrey W. Burr, Onur Mutlu, Abu Sebastian
2025 J jnl
CiMBA: Accelerating Genome Sequencing through On-Device Basecalling via Compute-in-Memory.
CoRR
William Andrew Simon, Irem Boybat, Riselda Kodra, Elena Ferro, Gagandeep Singh, Mohammed Alser, Shubham Jain, Hsinyu Tsai, Geoffrey W. Burr, Onur Mutlu, Abu Sebastian
2025 J jnl
Efficient scaling of large language models with mixture of experts and 3D analog in-memory computing.
Nat. Comput. Sci.
Julian Büchel, Athanasios Vasilopoulos, William Andrew Simon, Irem Boybat, Hsinyu Tsai, Geoffrey W. Burr, Hernan Castro, Bill Filipiak, Manuel Le Gallo, Abbas Rahimi, Vijay Narayanan, Abu Sebastian
2025 J jnl
Enhancing Downstream Analysis in Genome Sequencing: Species Classification While Basecalling.
CoRR
Riselda Kodra, Hadjer Benmeziane, Irem Boybat, William Andrew Simon
2025 Misc conf
Hardware-Aware Compilation and Simulation for In-Memory Computing.
CASES
Asif Ali Khan, Hadjer Benmeziane, Hamid Farzaneh, João Paulo C. de Lima, William Andrew Simon, Yiyu Shi, Zheyu Yan, Abu Sebastian, X. Sharon Hu, Jerónimo Castrillón, Corey Lammie
2025 C conf
Live Demonstration: Automated DNN Deployment on the IBM HERMES Project Chip.
ISCAS
Corey Lammie, Julian Büchel, Athanasios Vasilopoulos, Giacomo Camposampiero, Lionel Noussi, William Andrew Simon, Manuel Le Gallo, Abu Sebastian
2025 J jnl
Processing-in-memory for genomics workloads.
CoRR
William Andrew Simon, Leonid Yavits, Konstantina Koliogeorgi, Yann Falevoz, Yoshihiro Shibuya, Dominique Lavenier, Irem Boybat, Klea Zambaku, Berkan Sahin, Mohammad Sadrosadati, Onur Mutlu, Abu Sebastian, Rayan Chikhi, The BioPIM Consortium, Can Alkan
2022 A conf
HDTorch: Accelerating Hyperdimensional Computing with GP-GPUs for Design Space Exploration.
ICCAD
William Andrew Simon, Una Pale, Tomás Teijeiro, David Atienza
2022 J jnl
HDTorch: Accelerating Hyperdimensional Computing with GP-GPUs for Design Space Exploration.
CoRR
William Andrew Simon, Una Pale, Tomás Teijeiro, David Atienza
2021 A* conf
Exact Neural Networks from Inexact Multipliers via Fibonacci Weight Encoding.
DAC
William Andrew Simon, Valérian Ray, Alexandre Levisse, Giovanni Ansaloni, Marina Zapater, David Atienza
2021 J jnl
Gem5-X: A Many-core Heterogeneous Simulation Platform for Architectural Exploration and Optimization.
ACM Trans. Archit. Code Optim.
Yasir Mahmood Qureshi, William Andrew Simon, Marina Zapater, Katzalin Olcoz, David Atienza
2020 C conf
A Hybrid Cache HW/SW Stack for Optimizing Neural Network Runtime, Power and Endurance.
VLSI-SOC
William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza
2020 J jnl
BLADE: An in-Cache Computing Architecture for Edge Devices.
IEEE Trans. Computers
William Andrew Simon, Yasir Mahmood Qureshi, Marco Rios, Alexandre Levisse, Marina Zapater, David Atienza
2019 A* conf
A Fast, Reliable and Wide-Voltage-Range In-Memory Computing Architecture.
DAC
William Andrew Simon, Juan Galicia, Alexandre Levisse, Marina Zapater, David Atienza
2019 C conf
An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication.
VLSI-SoC
Marco Rios, William Andrew Simon, Alexandre Levisse, Marina Zapater, David Atienza
2019 — conf
BLADE: A BitLine Accelerator for Devices on the Edge.
ACM Great Lakes Symposium on VLSI
William Andrew Simon, Yasir Mahmood Qureshi, Alexandre Levisse, Marina Zapater, David Atienza
2019 — conf
Functionality Enhanced Memories for Edge-AI Embedded Systems.
NVMTS
Alexandre Levisse, Marco Rios, William Andrew Simon, Pierre-Emmanuel Gaillardon, David Atienza
2019 — conf
Gem5-X: A Gem5-Based System Level Simulation Framework to Optimize Many-Core Platforms.
SpringSim
Yasir Mahmood Qureshi, William Andrew Simon, Marina Zapater, David Atienza, Katzalin Olcoz
2018 C conf
A Machine Learning-Based Strategy for Efficient Resource Management of Video Encoding on Heterogeneous MPSoCs.
ISCAS
Arman Iranfar, William Andrew Simon, Marina Zapater, David Atienza
2017 A conf
1024-Channel 3D ultrasound digital beamformer in a single 5W FPGA.
DATE
Federico Angiolini, Aya Ibrahim, William Andrew Simon, Ahmet Caner Yuzuguler, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli
2017 — conf
Single-FPGA complete 3D and 2D medical ultrasound imager.
DASIP
Aya Ibrahim, William Andrew Simon, Damien Doy, Eliéva Pignat, Federico Angiolini, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli
2017 — conf
Thermal characterization of next-generation workloads on heterogeneous MPSoCs.
SAMOS
Arman Iranfar, Federico Terraneo, William Andrew Simon, Leon Dragic, Igor Piljic, Marina Zapater, William Fornaciari, Mario Kovac, David Atienza
2016 — conf
Demo: Efficient delay and apodization for on-FPGA 3D ultrasound.
DASIP
Ahmet Caner Yuzuguler, William Andrew Simon, Aya Ibrahim, Federico Angiolini, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli
2016 B conf
Single-FPGA 3D ultrasound beamformer.
FPL
Ahmet Caner Yuzuguler, William Andrew Simon, Aya Ibrahim, Federico Angiolini, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli
2016 B conf
Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer.
FPL
William Andrew Simon, Ahmet Caner Yuzuguler, Aya Ibrahim, Federico Angiolini, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli