William A. Rogers

18 papers A* 1A 6C 2Misc 1Journal 6Unranked 1
YearRankTypeTitle / Venue / Authors
1999 J jnl
A cost-effective design for testability: clock line control and test generation using selective clocking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sanghyeon Baeg, William A. Rogers
1994 C conf
A New Test Generation Methodology Using Selective Clocking for the Clock Line Controlled Circuits.
ICCD
Sanghyeon Baeg, William A. Rogers
1994 A conf
Hybrid Design for Testability Combining Scan and Clock Line Control and Method for Test Generation.
ITC
Sanghyeon Baeg, William A. Rogers
1993 J jnl
Hierarchical test pattern generation: a cost model and implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hyoung B. Min, Hwei-Tsu Ann Luh, William A. Rogers
1992 C conf
A Synthesis Algorithm for Two-Level XOR Based Circuits.
ICCD
Mark A. Heap, William A. Rogers, M. Ray Mercer
1992 J jnl
A test methodology for finite state machines using partial scan design.
J. Electron. Test.
Hyoung B. Min, William A. Rogers
1991 Misc conf
STarS: a target switching algorithm for sequential test generation.
VTS
Mark A. Heap, William A. Rogers, William B. Burns
1991 A conf
The Impedance Fault Model and Design for Robust Impedance Fault Testability.
ICCAD
Mark D. Sloan, William A. Rogers, Srihari Shoroff
1990 J jnl
Search strategy switching: A cost model and an analysis of backtracking.
J. Electron. Test.
Hyoung B. Min, William A. Rogers
1989 A conf
FANHAT: fanout oriented hierarchical automatic test generation system.
ICCAD
Hyoung B. Min, William A. Rogers, Hwei-Tsu Ann Luh
1989 J jnl
Generating Single-Stuck-Fault Coverage from a Collapsed-Fault Set.
Computer
Mark A. Heap, William A. Rogers
1989 A conf
Search Strategy Switching: An Alternative to Increased Backtracking.
ITC
Hyoung B. Min, William A. Rogers
1988 A* conf
Fault Simulation in a Distributed Environment.
DAC
Patrick A. Duba, Rabindra K. Roy, Jacob A. Abraham, William A. Rogers
1988 — —
The Use of Hierarchy in Test Generation, Fault Simulation, and Testability Analysis Algorithms
William A. Rogers
1987 J jnl
Concurrent Hierarchical Fault Simulation: A Performance Model and Two Optimizations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
William A. Rogers, John F. Guzolek, Jacob A. Abraham
1986 A conf
Structured Functional Level Test Generation Using Binary Decision Diagrams.
ITC
Hongtao P. Chang, William A. Rogers, Jacob A. Abraham
1985 A conf
CHIEFS : A Concurrent, Hierarchical and Extensible Fault Simulator.
ITC
William A. Rogers, Jacob A. Abraham
1985 — conf
High level hierarchical fault simulation techniques.
ACM Conference on Computer Science
William A. Rogers, Jacob A. Abraham