Werner Grollitsch

16 papers C 3Journal 4Unranked 9
YearRankTypeTitle / Venue / Authors
2025 C conf
A -44dB PSRR Analog Nested Digital Low Dropout Regulator for SoC applications in CMOS 28nm.
ISCAS
Stefano Bonomi, Werner Grollitsch, Sie Boo Chiang, Roberto Nonis
2023 J jnl
A Time-Domain Simulation Framework for the Modeling of Jitter in High-Speed Serial Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap.
Alessio Cortiula, Davide Menin, Andrea Bandiziol, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri
2020 C conf
Analysis of Spurs Impact in PLL-Based FMCW Radar Systems.
ISCAS
Luigi Grimaldi, Dmytro Cherniak, Werner Grollitsch, Roberto Nonis
2020 J jnl
Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Davide Menin, Andrea Bandiziol, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri
2019 — conf
A simple and fast tool for the modelling of inter-symbol interference and equalization in high-speed chip-to-chip interfaces.
MIPRO
Alessio Cortiula, Martino Dazzi, Mattia Marcon, Davide Menin, Marco Scapol, Andrea Bandiziol, Andrea Cristofoli, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri
2019 — conf
Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers.
APCCAS
Dylan D'Ampolo, Andrea Bandiziol, Davide Menin, Werner Grollitsch, Roberto Nonis, Pierpaolo Palestri
2018 J jnl
Design and Characterization of a 9.2-Gb/s Transceiver for Automotive Microcontroller Applications With 8-Taps FFE and 1-Tap Unrolled/4-Taps DFE.
IEEE Trans. Circuits Syst. II Express Briefs
Andrea Bandiziol, Werner Grollitsch, Giovanni Steffan, Roberto Nonis, Pierpaolo Palestri
2018 C conf
Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm.
ISCAS
Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Matteo Bassi, Roberto Nonis, Pierpaolo Palestri
2016 — conf
A fractional-N, all-digital injection-locked PLL with wide tuning range digitally controlled ring oscillator and Bang-Bang phase detection for temperature tracking in 40nm CMOS.
ESSCIRC
Werner Grollitsch, Roberto Nonis
2016 — conf
Design of a 8-taps, 10Gbps transmitter for automotive micro-controllers.
APCCAS
Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Roberto Nonis, Pierpaolo Palestri
2016 — conf
Design of a transmitter for high-speed serial interfaces in automotive micro-controller.
MIPRO
Andrea Bandiziol, Werner Grollitsch, Francesco Brandonisio, Roberto Nonis, Pierpaolo Palestri
2015 — conf
Design, characterization and signal integrity analysis of a 2.5 Gb/s High-Speed Serial Interface for automotive applications overarching the chip/PCB wall.
RTSI
Andrea Cossettini, Andrea Cristofoli, Werner Grollitsch, Lino Alves, Roberto Nonis, Luca Della Ricca, Pierpaolo Palestri, Luca Selmi
2013 — conf
A 2.4psrms-jitter digital PLL with Multi-Output Bang-Bang Phase Detector and phase-interpolator-based fractional-N divider.
ISSCC
Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt
2013 — conf
An all-digital PLL using random modulation for SSC generation in 65nm CMOS.
ISSCC
Nicola Da Dalt, Peter Pridnig, Werner Grollitsch
2013 J jnl
digPLL-Lite: A Low-Complexity, Low-Jitter Fractional-N Digital PLL Architecture.
IEEE J. Solid State Circuits
Roberto Nonis, Werner Grollitsch, Thomas Santa, Dmytro Cherniak, Nicola Da Dalt
2010 — conf
A 1.4psrms-period-jitter TDC-less fractional-N digital PLL with digitally controlled ring oscillator in 65nm CMOS.
ISSCC
Werner Grollitsch, Roberto Nonis, Nicola Da Dalt