Werner Geurts

16 papers A* 2A 1Journal 6Unranked 7
YearRankTypeTitle / Venue / Authors
2015 J jnl
ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces.
Future Gener. Comput. Syst.
Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Werner Geurts, Gert Goossens, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci, Davide Rossetti, Francesco Simula, Laura Tosoratto, Piero Vicini
2013 J jnl
A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II, 2012 technical report.
CoRR
Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Werner Geurts, Gert Goossens, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci, Davide Rossetti, Francesco Simula, Laura Tosoratto, Piero Vicini
2006 — conf
Design of ASIPs in multi-processor SoCs using the Chess/Checkers retargetable tool suite.
SoC
Gert Goossens, Dirk Lanneer, Werner Geurts, Johan Van Praet
2001 J jnl
Processor modeling and code selection for retargetable compilation.
ACM Trans. Design Autom. Electr. Syst.
Johan Van Praet, Dirk Lanneer, Werner Geurts, Gert Goossens
2001 — conf
Solving large scale assignment problems in high-level synthesis by approximative quadratic programming.
ACM Great Lakes Symposium on VLSI
Florin Balasa, Werner Geurts, Francky Catthoor, Hugo De Man
1997 J jnl
Embedded software in real-time signal processing systems: design technologies.
Proc. IEEE
Gert Goossens, Johan Van Praet, Dirk Lanneer, Werner Geurts, Augusli Kifli, Clifford Liem, Pierre G. Paulin
1996 — conf
A Graph Based Processor Model for Retargetable Code Generation.
ED&TC
Johan Van Praet, Dirk Lanneer, Gert Goossens, Werner Geurts, Hugo De Man
1995 J jnl
Quadratic zero-one programming-based synthesis of application-specific data paths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Werner Geurts, Francky Catthoor, Hugo De Man
1994 — conf
Chess: retargetable code generation for embedded DSP processors.
Code Generation for Embedded Processors
Dirk Lanneer, Johan Van Praet, Augusli Kifli, Koen Schoofs, Werner Geurts, Filip Thoen, Gert Goossens
1994 — conf
Loop transformation methodology for fixed-rate video, image and telecom processing applications.
ASAP
Francky Catthoor, Werner Geurts, Hugo De Man
1994 — conf
Optimal Scheduling and Software Pipelining of Repetitive Signal Flow Graphs with Delay Line Optimization.
EDAC-ETC-EUROASIC
Francis Depuydt, Werner Geurts, Gert Goossens, Hugo De Man
1993 A conf
Quadratic zero-one programming based synthesis of application specific data paths.
ICCAD
Werner Geurts, Francky Catthoor, Hugo De Man
1993 J jnl
Testability analysis in high level data path synthesis.
J. Electron. Test.
Johannes Steensma, Werner Geurts, Francky Catthoor, Hugo De Man
1992 A* conf
Time Constrained Allocation and Assignment Techniques for High Throughput Signal Processing.
DAC
Werner Geurts, Francky Catthoor, Hugo De Man
1991 A* conf
Cathedral-III: Architecture-Driven High-level Synthesis for High Throughput DSP Applications.
DAC
Stefaan Note, Werner Geurts, Francky Catthoor, Hugo De Man
1991 — conf
Partitioning-Based Allocation of Dedicated Data-Paths in the Architectural Synthesis for High Throughput Applications.
VLSI
Werner Geurts, Stefaan Note, Francky Catthoor, Hugo De Man