Wenji Fang

36 papers A* 7A 3Journal 22Unranked 4
YearRankTypeTitle / Venue / Authors
2026 J jnl
A New Benchmark for the Appropriate Evaluation of RTL Code Optimization.
CoRR
Yao Lu, Shang Liu, Hangan Zhou, Wenji Fang, Qijun Zhang, Zhiyao Xie
2025 — conf
A Self-Supervised, Pre-Trained, and Cross-Stage-Aligned Circuit Encoder Provides a Foundation for Various Design Tasks.
ASP-DAC
Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie
2025 J jnl
A Survey of Circuit Foundation Model: Foundation AI Models for VLSI Circuit Design and EDA.
CoRR
Wenji Fang, Jing Wang, Yao Lu, Shang Liu, Yuchao Wu, Yuzhe Ma, Zhiyao Xie
2025 A* conf
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis.
DAC
Wenkai Li, Yao Lu, Wenji Fang, Jing Wang, Qijun Zhang, Zhiyao Xie
2025 J jnl
ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis.
CoRR
Wenkai Li, Yao Lu, Wenji Fang, Jing Wang, Qijun Zhang, Zhiyao Xie
2025 — conf
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs.
ASP-DAC
Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang
2025 A* conf
CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design.
ICLR
Wenji Fang, Shang Liu, Jing Wang, Zhiyao Xie
2025 J jnl
CircuitFusion: Multimodal Circuit Representation Learning for Agile Chip Design.
CoRR
Wenji Fang, Shang Liu, Jing Wang, Zhiyao Xie
2025 A conf
GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment.
ICCAD
Wenji Fang, Wang Jing, Yao Lu, Shang Liu, Zhiyao Xie
2025 J jnl
GenEDA: Unleashing Generative Reasoning on Netlist via Multimodal Encoder-Decoder Aligned Foundation Model.
CoRR
Wenji Fang, Jing Wang, Yao Lu, Shang Liu, Zhiyao Xie
2025 A* conf
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph.
DAC
Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie
2025 J jnl
NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph.
CoRR
Wenji Fang, Wenkai Li, Shang Liu, Yao Lu, Hongce Zhang, Zhiyao Xie
2025 J jnl
OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation.
CoRR
Shang Liu, Yao Lu, Wenji Fang, Mengming Li, Zhiyao Xie
2025 A* conf
Profile-Guided Temporal Prefetching.
ISCA
Mengming Li, Qijun Zhang, Yichuan Gao, Wenji Fang, Yao Lu, Yongqing Ren, Zhiyao Xie
2025 J jnl
Profile-Guided Temporal Prefetching.
CoRR
Mengming Li, Qijun Zhang, Yichuan Gao, Wenji Fang, Yao Lu, Yongqing Ren, Zhiyao Xie
2025 J jnl
RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shang Liu, Wenji Fang, Yao Lu, Jing Wang, Qijun Zhang, Hongce Zhang, Zhiyao Xie
2025 A* conf
SynC-LLM: Generation of Large-Scale Synthetic Circuit Code with Hierarchical Language Models.
EMNLP
Shang Liu, Yao Lu, Wenji Fang, Jing Wang, Zhiyao Xie
2025 A* conf
SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits.
DAC
Shang Liu, Jing Wang, Wenji Fang, Zhiyao Xie
2025 J jnl
SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in Circuits.
CoRR
Shang Liu, Jing Wang, Wenji Fang, Zhiyao Xie
2025 — conf
Towards Big Data in AI for EDA Research: Generation of New Pseudo Circuits at RTL Stage.
ASP-DAC
Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Zhiyao Xie
2025 J jnl
Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie
2024 A* conf
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization.
DAC
Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie
2024 J jnl
Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization.
CoRR
Wenji Fang, Shang Liu, Hongce Zhang, Zhiyao Xie
2024 J jnl
AssertLLM: Generating Hardware Verification Assertions from Design Specifications via Multi-LLMs.
CoRR
Zhiyuan Yan, Wenji Fang, Mengming Li, Min Li, Shang Liu, Zhiyao Xie, Hongce Zhang
2024 J jnl
AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs.
CoRR
Wenji Fang, Mengming Li, Min Li, Zhiyuan Yan, Shang Liu, Hongce Zhang, Zhiyao Xie
2024 J jnl
Erratum to: Large circuit models: opportunities and challenges.
Sci. China Inf. Sci.
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024 J jnl
Large circuit models: opportunities and challenges.
Sci. China Inf. Sci.
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Ru Huang, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yu Li, Yun Liang, Jinwei Liu, Yi Liu, Yibo Lin, Guojie Luo, Hongyang Pan, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Junchi Yan, Jun Yang, Bei Yu, Mingxuan Yuan, Evangeline F. Y. Young, Xuan Zeng, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2024 A conf
OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation.
ICCAD
Shang Liu, Yao Lu, Wenji Fang, Mengming Li, Zhiyao Xie
2024 J jnl
SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model.
CoRR
Mengming Li, Wenji Fang, Qijun Zhang, Zhiyao Xie
2024 J jnl
TTNN: A Physically Guided Deep Learning Model for Focal Depth and Epicenter Distance Estimation Based on Multistation Waveforms.
IEEE Trans. Geosci. Remote. Sens.
Duofa Ji, Wenji Fang, Changhai Zhai, Zelin Cao, Yuhong Ma
2024 J jnl
The Dawn of AI-Native EDA: Promises and Challenges of Large Circuit Models.
CoRR
Lei Chen, Yiqi Chen, Zhufei Chu, Wenji Fang, Tsung-Yi Ho, Yu Huang, Sadaf Khan, Min Li, Xingquan Li, Yun Liang, Yibo Lin, Jinwei Liu, Yi Liu, Guojie Luo, Zhengyuan Shi, Guangyu Sun, Dimitrios Tsaras, Runsheng Wang, Ziyi Wang, Xinming Wei, Zhiyao Xie, Qiang Xu, Chenhao Xue, Evangeline F. Y. Young, Bei Yu, Mingxuan Yuan, Haoyi Zhang, Zuodong Zhang, Yuxiang Zhao, Hui-Ling Zhen, Ziyang Zheng, Binwu Zhu, Keren Zhu, Sunan Zou
2023 A conf
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design.
ICCAD
Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie
2023 J jnl
MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design.
CoRR
Wenji Fang, Yao Lu, Shang Liu, Qijun Zhang, Ceyu Xu, Lisa Wu Wills, Hongce Zhang, Zhiyao Xie
2023 J jnl
RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution.
CoRR
Shang Liu, Wenji Fang, Yao Lu, Qijun Zhang, Hongce Zhang, Zhiyao Xie
2023 — conf
WASIM: A Word-level Abstract Symbolic Simulation Framework for Hardware Formal Verification.
TACAS (2)
Wenji Fang, Hongce Zhang
2023 J jnl
r-map: Relating Implementation and Specification in Hardware Refinement Checking.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wenji Fang, Guangyu Hu, Hongce Zhang