Weng-Geng Ho

32 papers A 1C 14Journal 7Unranked 10
YearRankTypeTitle / Venue / Authors
2021 J jnl
A Power-Aware Toggling-Frequency Actuator in Data-Toggling SRAM for Secure Data Protection.
IEEE Trans. Circuits Syst. II Express Briefs
Weng-Geng Ho, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee
2021 J jnl
Dual-Hiding Side-Channel-Attack Resistant FPGA-Based Asynchronous-Logic AES: Design, Countermeasures and Evaluation.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Kwen-Siong Chong, Jun-Sheng Ng, Juncheng Chen, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Joseph Sylvester Chang, Bah-Hwee Gwee
2021 C conf
Normalized Differential Power Analysis - for Ghost Peaks Mitigation.
ISCAS
Juncheng Chen, Jun-Sheng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Zhiping Lin, Joseph Sylvester Chang, Bah-Hwee Gwee
2020 C conf
A DPA-Resistant Asynchronous-Logic NoC Router with Dual-Supply-Voltage-Scaling for Multicore Cryptographic Applications.
ISCAS
Weng-Geng Ho, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Jun-Sheng Ng, Juncheng Chen, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2020 C conf
A Highly Efficient Power Model for Correlation Power Analysis (CPA) of Pipelined Advanced Encryption Standard (AES).
ISCAS
Jun-Sheng Ng, Juncheng Chen, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee
2020 C conf
A Secure Data-Toggling SRAM for Confidential Data Protection.
ISCAS
Weng-Geng Ho, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee
2020 — conf
High Efficiency Early-Complete Brute Force Elimination Method for Security Analysis of Camouflage IC.
APCCAS
Weng-Geng Ho, Chuan-Seng Ng, Nay Aung Kyaw, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Bah-Hwee Gwee
2020 — conf
High Throughput and Secure Authentication-Encryption on Asynchronous Multicore Processor for Edge Computing IoT Applications.
ISOCC
Weng-Geng Ho, Ali Akbar Pammu, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Bah-Hwee Gwee
2019 J jnl
A High Throughput and Secure Authentication-Encryption AES-CCM Algorithm on Asynchronous Multicore Processor.
IEEE Trans. Inf. Forensics Secur.
Ali Akbar Pammu, Weng-Geng Ho, Ne Kyaw Zwa Lwin, Kwen-Siong Chong, Bah-Hwee Gwee
2019 J jnl
A Secure Data-Toggling SRAM for Confidential Data Protection.
IEEE Trans. Circuits Syst. I Regul. Pap.
Weng-Geng Ho, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee
2019 — conf
Reconfigurable Routing Paths As Noise Generators Using NoC Platform for Hardware Security Applications.
SoCC
Weng-Geng Ho, Ali Akbar Pammu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee
2019 — conf
Side-Channel-Attack Resistant Dual-Rail Asynchronous-Logic AES Accelerator Based on Standard Library Cells.
AsianHOST
Kwen-Siong Chong, Aparna Shreedhar, Ne Kyaw Zwa Lwin, Nay Aung Kyaw, Weng-Geng Ho, Chao Wang, Jun Zhou, Bah-Hwee Gwee, Joseph S. Chang
2018 — conf
A Comparative Analysis of 65nm CMOS SRAM and Commercial SRAMs in Security Vulnerability Evaluation.
DSP
Weng-Geng Ho, Zixian Zheng, Kwen-Siong Chong, Bah-Hwee Gwee
2018 J jnl
Asynchronous-Logic QDI Quad-Rail Sense-Amplifier Half-Buffer Approach for NoC Router Design.
IEEE Trans. Very Large Scale Integr. Syst.
Weng-Geng Ho, Kwen-Siong Chong, Kyaw Zwa Lwin Ne, Bah-Hwee Gwee, Joseph S. Chang
2017 C conf
DPA-resistant QDI dual-rail AES S-Box based on power-balanced weak-conditioned half-buffer.
ISCAS
James Lim, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee
2017 J jnl
Sense Amplifier Half-Buffer (SAHB) A Low-Power High-Performance Asynchronous Logic QDI Cell Template.
IEEE Trans. Very Large Scale Integr. Syst.
Kwen-Siong Chong, Weng-Geng Ho, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
2016 C conf
Area-efficient and low stand-by power 1k-byte transmission-gate-based non-imprinting high-speed erase (TNIHE) SRAM.
ISCAS
Weng-Geng Ho, Kyaw Zwa Lwin Ne, N. Prashanth Srinivas, Kwen-Siong Chong, Tony Tae-Hyoung Kim, Bah-Hwee Gwee
2016 C conf
High performance low overhead template-based Cell-Interleave Pipeline (TCIP) for asynchronous-logic QDI circuits.
ISCAS
Weng-Geng Ho, Nan Liu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang
2016 — conf
Interceptive side channel attack on AES-128 wireless communications for IoT applications.
APCCAS
Ali Akbar Pammu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee
2016 A conf
Low normalized energy derivation asynchronous circuit synthesis flow through fork-join slack matching for cryptographic applications.
DATE
Nan Liu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee, Joseph Sylvester Chang
2016 — conf
Security analysis of asynchronous-logic QDI cell approach for differential power analysis attack.
ISIC
Weng-Geng Ho, Ali Akbar Pammu, Nan Liu, Kyaw Zwa Lwin Ne, Kwen-Siong Chong, Bah-Hwee Gwee
2016 — conf
Success rate model for fully AES-128 in correlation power analysis.
APCCAS
Ali Akbar Pammu, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Weng-Geng Ho, Nan Liu, Bah-Hwee Gwee
2015 C conf
High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC).
ISCAS
Weng-Geng Ho, Kwen-Siong Chong, Ne Kyaw Zwa Lwin, Bah-Hwee Gwee, Joseph S. Chang
2015 J jnl
Low power sub-threshold asynchronous quasi-delay-insensitive 32-bit arithmetic and logic unit based on autonomous signal-validity half-buffer.
IET Circuits Devices Syst.
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2014 — conf
A dynamic-voltage-scaling 1kbyte×8-bit non-imprinting Master-Slave SRAM with high speed erase for low-power operation.
ISIC
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Ne Kyaw Zwa Lwin
2014 — conf
Low delay-variation sub-/near-threshold asynchronous-to-synchronous interface controller for GALS Network-on-Chips.
APCCAS
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2014 C conf
Synthesis of asynchronous QDI circuits using synchronous coding specifications.
ISCAS
Rong Zhou, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang, Weng-Geng Ho
2013 C conf
A dual-core 8051 microcontroller system based on synchronous-logic and asynchronous-logic.
ISCAS
Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2013 C conf
Low power sub-threshold asynchronous QDI Static Logic Transistor-level Implementation (SLTI) 32-bit ALU.
ISCAS
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2012 C conf
A comparative study on asynchronous Quasi-Delay-Insensitive templates.
ISCAS
Kok-Leong Chang, Tong Lin, Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph S. Chang
2012 C conf
Energy-delay efficient asynchronous-logic 16×16-bit pipelined multiplier based on Sense Amplifier-Based Pass Transistor Logic.
ISCAS
Weng-Geng Ho, Kwen-Siong Chong, Tong Lin, Bah-Hwee Gwee, Joseph S. Chang
2011 C conf
Improved asynchronous-logic dual-rail Sense Amplifier-based Pass Transistor Logic with high speed and low power operation.
ISCAS
Weng-Geng Ho, Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang, Yin Sun, Kok-Leong Chang