Wen Ching Wu

16 papers A* 1A 3Journal 6Unranked 6
YearRankTypeTitle / Venue / Authors
2011 J jnl
A Built-in Self-Diagnosis and Repair Design With Fail Pattern Identification for Memories.
IEEE Trans. Very Large Scale Integr. Syst.
Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Kun-Lun Luo, Wen Ching Wu
2010 — conf
CAD reference flow for 3D via-last integrated circuits.
ASP-DAC
Chang-Tzu Lin, Ding-Ming Kwai, Yung-Fa Chou, Ting-Sheng Chen, Wen Ching Wu
2010 J jnl
Diagnosis of MRAM Write Disturbance Fault.
IEEE Trans. Very Large Scale Integr. Syst.
Chin-Lung Su, Chih-Wea Tsai, Ching-Yi Chen, Wan-Yu Lo, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao
2008 J jnl
Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu
2007 J jnl
A Multilayer Data Copy Test Data Compression Scheme for Reducing Shifting-in Power for Multiple Scan Design.
IEEE Trans. Very Large Scale Integr. Syst.
Shih-Ping Lin, Chung-Len Lee, Jwu-E Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu
2007 A conf
Diagnosis for MRAM write disturbance fault.
ITC
Chin-Lung Su, Chih-Wea Tsai, Cheng-Wen Wu, Ji-Jan Chen, Wen Ching Wu, Chien-Chung Hung, Ming-Jer Kao
2006 A conf
A Multilayer Data Copy Scheme for Low Cost Test with Controlled Scan-In Power for Multiple Scan Chain Designs.
ITC
Shih Ping Lin, Chung-Len Lee, Jwu E. Chen, Ji-Jan Chen, Kun-Lun Luo, Wen Ching Wu
2005 — conf
Crosstalk Fault Detection for Interconnection Lines Based on Path Delay Inertia Principle.
Asian Test Symposium
Ming Shae Wu, Chung-Len Lee, Yeong-Jar Chang, Wen Ching Wu
2004 — conf
A Parallel Built-in Diagnostic Scheme for Multiple Embedded Memories.
MTDT
Li-Ming Denq, Rei-Fu Huang, Cheng-Wen Wu, Yeong-Jar Chang, Wen Ching Wu
2004 A conf
MRAM Defect Analysis and Fault Modeli.
ITC
Chin-Lung Su, Rei-Fu Huang, Cheng-Wen Wu, Chien-Chung Hung, Ming-Jer Kao, Yeong-Jar Chang, Wen Ching Wu
2000 J jnl
Oscillation Ring Delay Test for High Performance Microprocessors.
J. Electron. Test.
Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir
1998 J jnl
A Two-Phase Fault Simulation Scheme for Sequential Circuits.
J. Inf. Sci. Eng.
Wen Ching Wu, Chung-Len Lee, Jwu E. Chen
1997 — conf
Fault diagnosis of odd-even sorting networks.
Asian Test Symposium
Chih Wei Hu, Chung-Len Lee, Wen Ching Wu, Jwu E. Chen
1995 — conf
Identification of robust untestable path delay faults.
Asian Test Symposium
Wen Ching Wu, Chung-Len Lee, Jwu E. Chen
1994 — conf
Distributed Fault Simulation for Sequential Circuits by Pattern Partitioning.
EDAC-ETC-EUROASIC
Wen Ching Wu, Chung-Len Lee, Jwu E. Chen, Won Yih Lin
1991 A* conf
A Probabilistic Testability Measure for Delay Faults.
DAC
Wen Ching Wu, Chung-Len Lee