Wen-Zen Shen

25 papers A* 3A 6C 1Journal 8Unranked 7
YearRankTypeTitle / Venue / Authors
2001 — conf
A pattern compaction technique for power estimation based on power sensitivity information.
ISCAS (5)
Chih-Yang Hsu, Chaur-Wen Wei, Wen-Zen Shen
2001 — conf
Grouped input power sensitive transition an input sequence compaction technique for power estimation.
ISCAS (5)
Heng-Liang Huang, Yeong-Ren Chen, Jing-Yang Jou, Wen-Zen Shen
2000 — conf
A new method for constructing IP level power model based on power sensitivity.
ASP-DAC
Heng-Liang Huang, Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
2000 J jnl
ALTO: an iterative area/performance tradeoff algorithm for LUT-based FPGA technology mapping.
IEEE Trans. Very Large Scale Integr. Syst.
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
1999 J jnl
A structure-oriented power modeling technique for macrocells.
IEEE Trans. Very Large Scale Integr. Syst.
Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
1998 J jnl
On circuit clustering for area/delay tradeoff under capacity and pin constraints.
IEEE Trans. Very Large Scale Integr. Syst.
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen, Hsien-Ho Chuang
1997 A conf
A power modeling and characterization method for macrocells using structure information.
ICCAD
Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
1997 — conf
CB-Power: a hierarchical cell-based power characterization and estimation environment for static CMOS circuits.
ASP-DAC
Wen-Zen Shen, Jiing-Yuan Lin, Jyh-Ming Lu
1996 A conf
A power modeling and characterization method for the CMOS standard cell library.
ICCAD
Jiing-Yuan Lin, Wen-Zen Shen, Jing-Yang Jou
1996 A conf
An iterative area/performance trade-off algorithm for LUT-based FPGA technology mapping.
ICCAD
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
1995 A conf
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture.
ICCAD
Juinn-Dar Huang, Jing-Yang Jou, Wen-Zen Shen
1995 — conf
Fanout fault analysis for digital logic circuits.
Asian Test Symposium
Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen, Beyin Chen
1995 A* conf
Lambda Set Selection in Roth-Karp Decomposition for LUT-Based FPGA Technology Mapping.
DAC
Wen-Zen Shen, Juinn-Dar Huang, Shih-Min Chao
1995 — conf
Transistor reordering rules for power reduction in CMOS gates.
ASP-DAC
Wen-Zen Shen, Jiing-Yuan Lin, Fong-Wen Wang
1994 A conf
A cell-based power estimation in CMOS combinational circuits.
ICCAD
Jiing-Yuan Lin, Tai-Chien Liu, Wen-Zen Shen
1994 C conf
On the Reduction of Recorder Buffer Size for Discrete Fourier Transform Processor Design.
ISCAS
Wen-Zen Shen, Yi-Hsin Tao, Lan-Rong Dung
1993 J jnl
Design of Pseudoexhaustive Testable PLA with Low Overhead.
IEEE Trans. Computers
Wen-Zen Shen, Gwo-Haur Hwang, Wen-Jun Hsu, Yun-Jung Jan
1993 J jnl
Restructuring and logic minimization for testable PLA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Gwo-Haur Hwang, Wen-Zen Shen
1992 A* conf
Coalgebraic Division for Multilevel Logic Synthesis.
DAC
Wen-Jun Hsu, Wen-Zen Shen
1992 J jnl
MT-SIM a mixed-level transition fault simulator based on parallel patterns.
J. Electron. Test.
Chung Len Lee, Ching Ping Wu, Wen-Zen Shen, Tyh-Song Hwang, Shueng Dar Hwang
1992 — conf
SEESIM - a fast synchronous sequential circuit fault simulator with single event equivalence.
EURO-DAC
Ching Ping Wu, Chung Len Lee, Wen-Zen Shen
1991 J jnl
Checkpoints in irredundant two-level combinational circuits.
J. Electron. Test.
Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen
1991 J jnl
Single-fault fault-collapsing analysis in sequential logic circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen
1990 A* conf
A Parallel Pattern Mixed-Level Fault Simulator.
DAC
Tyh-Song Hwang, Chung Len Lee, Wen-Zen Shen, Ching Ping Wu
1990 A conf
Single-fault fault collapsing analysis in sequential logic circuits.
ITC
Jwu E. Chen, Chung-Len Lee, Wen-Zen Shen