Wen-Pin Tu

12 papers A 2C 1Journal 3Unranked 6
YearRankTypeTitle / Venue / Authors
2014 — conf
Abstract bus interface unit for ESL design from TLM 2.0 communications to the real bus protocol.
APCCAS
Hua-Hsin Yeh, Wen-Pin Tu, Jian-Zhi Shen, Tung-Hua Yen, Shih-Hsu Huang
2014 — conf
Self-adjusting mechanism to dynamically suppress the effect of PVT variations on clock skew.
APCCAS
Tsung-Tang Lin, Wen-Pin Tu, Shih-Hsu Huang
2013 A conf
Co-synthesis of data paths and clock control paths for minimum-period clock gating.
DATE
Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng
2013 J jnl
Low-power anti-aging zero skew clock gating.
ACM Trans. Design Autom. Electr. Syst.
Shih-Hsu Huang, Wen-Pin Tu, Chia-Ming Chang, Song-Bin Pan
2013 A conf
Low-power timing closure methodology for ultra-low voltage designs.
ICCAD
Wen-Pin Tu, Chung-Han Chou, Shih-Hsu Huang, Shih-Chieh Chang, Yow-Tyng Nieh, Chien-Yung Chou
2012 — conf
Clock period minimization with minimum area overhead in high-level synthesis of nonzero clock skew circuits.
ASP-DAC
Wen-Pin Tu, Shih-Hsu Huang, Chun-Hua Cheng
2012 J jnl
High-Level Synthesis for Minimum-Area Low-Power Clock Gating.
J. Inf. Sci. Eng.
Shih-Hsu Huang, Wen-Pin Tu, Bing-Hung Li
2012 C conf
NBTI-aware dual threshold voltage assignment for leakage power reduction.
ISCAS
Wen-Pin Tu, Shih-Wei Wu, Shih-Hsu Huang, Mely Chen Chi
2011 — conf
TSV sharing through multiplexing for TSV count minimization in high-level synthesis.
SoCC
Wen-Pin Tu, Yen-Hsin Lee, Shih-Hsu Huang
2011 — conf
Teaching three-dimensional system-in-package design automation in a semester course.
MSE
Shih-Hsu Huang, Wen-Pin Tu, Hua-Hsin Yeh, Chun-Hua Cheng
2010 — conf
Critical-PMOS-aware clock tree design methodology for anti-aging zero skew clock gating.
ASP-DAC
Shih-Hsu Huang, Chia-Ming Chang, Wen-Pin Tu, Song-Bin Pan
2008 J jnl
Module binding for low power clock gating.
IEICE Electron. Express
Chun-Hua Cheng, Shih-Hsu Huang, Wen-Pin Tu