Wen-Hao Liu - RankMe

48 papers A* 7A 9C 2Journal 8Unranked 22

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Parallel Delay-Driven Layer Assignment Leveraging Hierarchical Task Graph Modeling for Advanced Technology Nodes. IEEE Trans. Computers Zepeng Li, Zhen Zhuang, Genggeng Liu, Wen-Hao Liu, Tsung-Yi Ho, Ting-Chi Wang
2025	J	`jnl`	A Unified Deep Reinforcement Learning Approach for Constructing Rectilinear and Octilinear Steiner Minimum Tree. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Zhenkun Lin, Genggeng Liu, Xing Huang, Yibo Lin, Jixin Zhang, Wen-Hao Liu, Ting-Chi Wang
2025	A	`conf`	Invited Paper: 2025 ICCAD CAD Contest Problem C: Incremental Placement Optimization Beyond Detailed Placement: Simultaneous Gate Sizing, Buffering, and Cell Relocation. ICCAD Yi-Chen Lu, Rongjian Liang, Wen-Hao Liu, Haoxing Ren
2025	—	`conf`	Invited: ISPD 2025 Performance-Driven Large Scale Global Routing Contest. ISPD Rongjian Liang, Anthony Agnesina, Wen-Hao Liu, Matt Liberty, Hsin-Tzu Chang, Haoxing Ren
2025	A*	`conf`	Late Breaking Results: An Efficient and Scalable Track Assignment with GPU Parallelism. DAC Genggeng Liu, Pengcheng Huang, Zepeng Li, Wen-Hao Liu, Xing Huang, Wenzhong Guo
2025	A	`conf`	Leveraging GPU for Better Detailed Placement Quality. ICCAD Chen-Han Lu, Wen-Hao Liu, Haoxing Ren, Ting-Chi Wang
2025	—	`conf`	Paired-Spacing-Constrained Package Routing with Net Ordering Optimization. ASP-DAC Yi-Sian Ciou, Ying-Jie Jiang, Yi-Yu Liu, Shao-Yun Fang, Wen-Hao Liu
2025	A*	`conf`	Reinforcement Learning-Driven Window Selection for Enhanced Window-Based Rip-up and Reroute in Chip Detailed Routing. DAC Yu-Chan Keng, Yu-Chun Pai, Wen-Hao Liu, Haoxing Ren, Danny Liu, Rongjian Liang, Mark Ho, Anthony Agnesina, Yih-Lang Li
2024	—	`conf`	Challenges for Automating PCB Layout. ISPD Wen-Hao Liu, Anthony Agnesina, Haoxing Mark Ren
2024	—	`conf`	GPU/ML-Enhanced Large Scale Global Routing Contest. ISPD Rongjian Liang, Anthony Agnesina, Wen-Hao Liu, Haoxing Ren
2024	—	`conf`	ReLS: Retrieval Is Efficient Knowledge Transfer For Logic Synthesis. MLCAD Rongjian Liang, Chia-Tung Ho, Anthony Agnesina, Wen-Hao Liu, Haoxing Ren
2022	—	`conf`	Challenges for Automating Package Routing. ISPD Wen-Hao Liu, Bing Chen, Hua-Yu Chang, Gary Lin, Zi-Shen Lin
2022	J	`jnl`	In-Route Pin Access-Driven Placement Refinement for Improved Detailed Routing Convergence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrew B. Kahng, Jian Kuang, Wen-Hao Liu, Bangqi Xu
2022	C	`conf`	LA-SVR: A High-Performance Layer Assignment Algorithm with Slew Violations Reduction. VLSI-SoC Lieqiu Jiang, Zepeng Li, Chenpeng Bao, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang
2022	C	`conf`	SPTA: A Scalable Parallel ILP-Based Track Assignment Algorithm with Two-Stage Partition. VLSI-SoC Yidan Jing, Liliang Yang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Ting-Chi Wang
2022	J	`jnl`	Timing-Aware Layer Assignment for Advanced Process Technologies Considering via Pillars. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Genggeng Liu, Xinghai Zhang, Wenzhong Guo, Xing Huang, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang
2021	A	`conf`	ALIFRouter: A Practical Architecture-Level Inter-FPGA Router for Logic Verification. DATE Zhen Zhuang, Xing Huang, Genggeng Liu, Wenzhong Guo, Weikang Qian, Wen-Hao Liu
2020	—	`conf`	MSFRoute: Multi-Stage FPGA Routing for Timing Division Multiplexing Technique. ACM Great Lakes Symposium on VLSI Zhen Zhuang, Genggeng Liu, Xing Huang, Xiaotao Jia, Wen-Hao Liu, Wenzhong Guo
2020	A	`conf`	MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology Nodes. DATE Xinghai Zhang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Wenzhong Guo, Ting-Chi Wang
2019	—	`conf`	ISPD 2019 Initial Detailed Routing Contest and Benchmark with Advanced Routing Rules. ISPD Wen-Hao Liu, Stefanus Mantik, Wing-Kai Chow, Yixiao Ding, Amin Farshidi, Gracieli Posser
2019	—	`conf`	Latency constraint guided buffer sizing and layer assignment for clock trees with useful skew. ASP-DAC Necati Uysal, Wen-Hao Liu, Rickard Ewetz
2018	—	`conf`	ISPD 2018 Initial Detailed Routing Contest and Benchmarks. ISPD Stefanus Mantik, Gracieli Posser, Wing-Kai Chow, Yixiao Ding, Wen-Hao Liu
2018	J	`jnl`	MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells for Advanced Nodes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan
2017	—	`conf`	Delay-driven layer assignment for advanced technology nodes. ASP-DAC Szu-Yuan Han, Wen-Hao Liu, Rickard Ewetz, Cheng-Kok Koh, Kai-Yuan Chao, Ting-Chi Wang
2016	A	`conf`	MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes. ICCAD Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan
2016	—	`conf`	Negotiation-based track assignment considering local nets. ASP-DAC Man-Pan Wong, Wen-Hao Liu, Ting-Chi Wang
2015	J	`jnl`	Region-Based and Panel-Based Algorithms for Unroutable Placement Recognition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang
2014	A	`conf`	A resource-level parallel approach for global-routing-based routing congestion estimation and a method to quantify estimation accuracy. ICCAD Wen-Hao Liu, Zhen-Yu Peng, Ting-Chi Wang
2014	—	`conf`	A study on the use of parallel wiring techniques for sub-20nm designs. ACM Great Lakes Symposium on VLSI Rickard Ewetz, Wen-Hao Liu, Kai-Yuan Chao, Ting-Chi Wang, Cheng-Kok Koh
2014	—	`conf`	A study on unroutable placement recognition. ISPD Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang
2014	A*	`conf`	Density-aware Detailed Placement with Instant Legalization. DAC Sergiy Popovych, Hung-Hao Lai, Chieh-Min Wang, Yih-Lang Li, Wen-Hao Liu, Ting-Chi Wang
2014	A*	`conf`	Floorplanning and Signal Assignment for Silicon Interposer-based 3D ICs. DAC Wen-Hao Liu, Min-Sheng Chang, Ting-Chi Wang
2014	—	`conf`	ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement. ISPD Vladimir Yutsis, Ismail Bustany, David G. Chinnery, Joseph R. Shinnerl, Wen-Hao Liu
2014	A	`conf`	Metal layer planning for silicon interposers with consideration of routability and manufacturing cost. DATE Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang
2014	—	`conf`	Skillfully diminishing antenna effect in layer assignment stage. VLSI-DAT Chih-Chien Lin, Wen-Hao Liu, Yih-Lang Li
2013	—	`conf`	Case study for placement solutions in ispd11 and dac12 routability-driven placement contests. ISPD Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li
2013	J	`jnl`	NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao
2013	A*	`conf`	Optimization of placement solutions for routability. DAC Wen-Hao Liu, Cheng-Kok Koh, Yih-Lang Li
2013	A*	`conf`	Routing congestion estimation with real design constraints. DAC Wen-Hao Liu, Yaoguang Wei, Cliff C. N. Sze, Charles J. Alpert, Zhuo Li, Yih-Lang Li, Natarajan Viswanathan
2012	A	`conf`	A fast maze-free routing congestion estimator with hybrid unilateral monotonic routing. ICCAD Wen-Hao Liu, Yih-Lang Li, Cheng-Kok Koh
2012	J	`jnl`	NCTU-GR: Efficient Simulated Evolution-Based Rerouting and Congestion-Relaxed Layer Assignment on 3-D Global Routing. IEEE Trans. Very Large Scale Integr. Syst. Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li
2012	—	`conf`	Optimizing the antenna area and separators in layer assignment of multi-layer global routing. ISPD Wen-Hao Liu, Yih-Lang Li
2012	—	`conf`	Topology-aware buffer insertion and GPU-based massively parallel rerouting for ECO timing optimization. ASP-DAC Yen-Hung Lin, Yun-Jian Lo, Hian-Syun Tong, Wen-Hao Liu, Yih-Lang Li
2011	A	`conf`	High-quality global routing for multiple dynamic supply voltage designs. ICCAD Wen-Hao Liu, Yih-Lang Li, Kai-Yuan Chao
2011	—	`conf`	Negotiation-based layer assignment for via count and via overflow minimization. ASP-DAC Wen-Hao Liu, Yih-Lang Li
2010	—	`conf`	Minimizing clock latency range in robust clock tree synthesis. ASP-DAC Wen-Hao Liu, Yih-Lang Li, Hui-Chi Chen
2010	A*	`conf`	Multi-threaded collision-aware global routing with bounded-length maze routing. DAC Wen-Hao Liu, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao
2009	—	`conf`	Efficient simulated evolution based rerouting and congestion-relaxed layer assignment on 3-D global routing. ASP-DAC Ke-Ren Dai, Wen-Hao Liu, Yih-Lang Li