Wen-Ben Jone

118 papers A* 7A 14B 1C 5Misc 12Journal 55Unranked 24
YearRankTypeTitle / Venue / Authors
2018 J jnl
SERA: statistical error rate analysis for profit-oriented performance binning of resilient circuits.
Integr.
Qiang Han, Qiang Xu, Wen-Ben Jone
2017 J jnl
Leak Stopper: An Actively Revitalized Snoop Filter Architecture with Effective Generation Control.
ACM Trans. Design Autom. Electr. Syst.
Yin-Chi Peng, Chien-Chih Chen, Hsiang-Jen Tsai, Keng-Hao Yang, Pei-Zhe Huang, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen
2016 J jnl
High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols.
IEEE Trans. Very Large Scale Integr. Syst.
Hsuan-Ming Chou, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen
2015 — conf
On Resilient System Performance Binning.
ISPD
Qiang Han, Jianghao Guo, Qiang Xu, Wen-Ben Jone
2015 J jnl
Soft-Error-Tolerant Design Methodology for Balancing Performance, Power, and Reliability.
IEEE Trans. Very Large Scale Integr. Syst.
Hsuan-Ming Chou, Ming-Yi Hsiao, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Chiao-Ling Lung, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen
2014 — conf
On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield.
ACM Great Lakes Symposium on VLSI
Tak-Kei Lam, Xing Wei, Wen-Ben Jone, Yi Diao, Yu-Liang Wu
2013 — conf
A configurable bus-tracer for error reproduction in post-silicon validation.
VLSI-DAT
Shing-Yu Chen, Ming-Yi Hsiao, Wen-Ben Jone, Tien-Fu Chen
2013 — conf
A cross-layer fault-tolerant design method for high manufacturing yield and system reliability.
DFTS
Jianghao Guo, Qiang Han, Wen-Ben Jone, Yu-Liang Wu
2013 A* conf
On testing timing-speculative circuits.
DAC
Feng Yuan, Yannan Liu, Wen-Ben Jone, Qiang Xu
2013 — conf
Path delay testing in resilient system.
MWSCAS
Qiang Han, Jianghao Guo, Wen-Ben Jone, Qiang Xu
2013 A* conf
Post-placement voltage island generation for timing-speculative circuits.
DAC
Rong Ye, Feng Yuan, Zelong Sun, Wen-Ben Jone, Qiang Xu
2013 J jnl
Testing of Synchronizers in Asynchronous FIFO.
J. Electron. Test.
Hyoung-Kook Kim, Laung-Terng Wang, Yu-Liang Wu, Wen-Ben Jone
2012 — conf
IMITATOR: A deterministic multicore replay system with refining techniques.
VLSI-DAT
Shing-Yu Chen, Chi-Neng Wen, Geng-Hau Yang, Wen-Ben Jone, Tien-Fu Chen
2012 J jnl
Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.
ACM Trans. Design Autom. Electr. Syst.
Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Wen-Ben Jone, Michael S. Hsiao, Fangfang Li, James Chien-Mo Li, Jiun-Lang Huang
2011 J jnl
Aggressive Runtime Leakage Control Through Adaptive Light-Weight V
IEEE Trans. Very Large Scale Integr. Syst.
Hao Xu, Wen-Ben Jone, Ranga Vemuri
2011 J jnl
Dynamic Characteristics of Power Gating During Mode Transition.
IEEE Trans. Very Large Scale Integr. Syst.
Hao Xu, Ranga Vemuri, Wen-Ben Jone
2011 J jnl
Location Cache Design and Performance Analysis for Chip Multiprocessors.
IEEE Trans. Very Large Scale Integr. Syst.
Jason Nemeth, Rui Min, Wen-Ben Jone, Yiming Hu
2011 J jnl
Using Launch-on-Capture for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shianling Wu, Laung-Terng Wang, Xiaoqing Wen, Zhigang Jiang, Lang Tan, Yu Zhang, Yu Hu, Wen-Ben Jone, Michael S. Hsiao, James Chien-Mo Li, Jiun-Lang Huang, Lizhen Yu
2010 A conf
Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs.
ICCAD
Hao Xu, Ranga Vemuri, Wen-Ben Jone
2010 J jnl
Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer.
J. Electron. Test.
Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang
2010 — conf
Logic BIST Architecture Using Staggered Launch-on-Shift for Testing Designs Containing Asynchronous Clock Domains.
DFT
Shianling Wu, Laung-Terng Wang, Lizhen Yu, Hiroshi Furukawa, Xiaoqing Wen, Wen-Ben Jone, Nur A. Touba, Feifei Zhao, Jinsong Liu, Hao-Jan Chao, Fangfang Li, Zhigang Jiang
2010 Misc conf
Novel Vth Hopping Techniques for Aggressive Runtime Leakage Control.
VLSI Design
Hao Xu, Wen-Ben Jone, Ranga Vemuri
2010 A conf
Stretching the limit of microarchitectural level leakage control with Adaptive Light-Weight Vth Hopping.
ICCAD
Hao Xu, Wen-Ben Jone, Ranga Vemuri
2010 J jnl
Tuning
J. Low Power Electron.
Hao Xu, Wen-Ben Jone, Ranga Vemuri
2010 J jnl
Using Launch-on-Capture for Testing BIST Designs Containing Synchronous and Asynchronous Clock Domains.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Laung-Terng Wang, Xiaoqing Wen, Shianling Wu, Hiroshi Furukawa, Hao-Jan Chao, Boryau Sheu, Jianghao Guo, Wen-Ben Jone
2009 — conf
Analysis of Resistive Bridging Defects in a Synchronizer.
Asian Test Symposium
Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang, Shianling Wu
2009 — conf
Analysis of Resistive Open Defects in a Synchronizer.
DFT
Hyoung-Kook Kim, Wen-Ben Jone, Laung-Terng Wang
2009 A conf
Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage.
DATE
Hao Xu, Ranga Vemuri, Wen-Ben Jone
2009 A conf
Temporal and spatial idleness exploitation for optimal-grained leakage control.
ICCAD
Hao Xu, Ranga Vemuri, Wen-Ben Jone
2009 J jnl
Turbo1500: Core-Based Design for Test and Diagnosis.
IEEE Des. Test Comput.
Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Wen-Ben Jone, Jianghao Guo, Kuen-Jong Lee, Wei-Shin Wang, Xiaoqing Wen, Hao-Jan Chao, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li
2008 A conf
Accurate energy breakeven time estimation for run-time power gating.
ICCAD
Hao Xu, Wen-Ben Jone, Ranga Vemuri
2008 — conf
Control Circuitry for Self-Repairable MEMS Accelerometers.
EIAT/IETA
Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
2008 A conf
Dynamic virtual ground voltage estimation for power gating.
ISLPED
Hao Xu, Ranga Vemuri, Wen-Ben Jone
2008 — conf
Material Fatigue and Reliability of MEMS Accelerometers.
DFT
Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
2008 J jnl
On a New Graph Theory Approach to Designing Zero-Aliasing Space Compressors for Built-In Self-Testing.
IEEE Trans. Instrum. Meas.
Sunil R. Das, Altaf Hossain, Satyendra Biswas, Emil M. Petriu, Mansour H. Assaf, Wen-Ben Jone, Mehmet Sahinoglu
2008 C conf
Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW.
ICCD
Hao Xu, Ranga Vemuri, Wen-Ben Jone
2008 A conf
Turbo1500: Toward Core-Based Design for Test and Diagnosis Using the IEEE 1500 Standard.
ITC
Laung-Terng Wang, Ravi Apte, Shianling Wu, Boryau Sheu, Kuen-Jong Lee, Xiaoqing Wen, Wen-Ben Jone, Chia-Hsien Yeh, Wei-Shin Wang, Hao-Jan Chao, Jianghao Guo, Jinsong Liu, Yanlong Niu, Yi-Chih Sung, Chi-Chun Wang, Fangfang Li
2007 C conf
An efficient routing method for pseudo-exhaustive built-in self-testing of high-speed interconnects.
ICCD
Jianxun Liu, Wen-Ben Jone
2007 J jnl
Fault Modeling and Detection for Drowsy SRAM Caches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wei Pei, Wen-Ben Jone, Yiming Hu
2007 J jnl
Testing Analog and Mixed-Signal Circuits With Built-In Hardware - A New Approach.
IEEE Trans. Instrum. Meas.
Sunil R. Das, Jila Zakizadeh, Satyendra Biswas, Mansour H. Assaf, Amiya Nayak, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu
2006 — conf
An Efficient Wrapper Scan Chain Configuration Method for Network-on-Chip Testing.
ISVLSI
Ming Li, Wen-Ben Jone, Qing-An Zeng
2006 J jnl
Crosstalk test pattern generation for dynamic programmable logic arrays.
IEEE Trans. Instrum. Meas.
Jianxun Liu, Wen-Ben Jone, Sunil R. Das
2006 A* conf
DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip.
DAC
Ming Li, Qing-An Zeng, Wen-Ben Jone
2006 A conf
Fault Modeling and Detection for Drowsy SRAM Caches.
ITC
Wei Pei, Wen-Ben Jone, Yiming Hu
2006 — conf
Reliability Analysis of Self-Repairable MEMS Accelerometer.
DFT
Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
2005 J jnl
A built-in self-testing method for embedded multiport memory arrays.
IEEE Trans. Instrum. Meas.
Vinod Narayanan, Swaroop Ghosh, Wen-Ben Jone, Sunil R. Das
2005 J jnl
A dual-mode built-in self-test technique for capacitive MEMS devices.
IEEE Trans. Instrum. Meas.
Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
2005 — conf
Design and Analysis of Self-Repairable MEMS Accelerometer.
DFT
Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
2005 — conf
Design and design automation of rectification logic for engineering change.
ASP-DAC
Cheng-Hung Lin, Yung-Chang Huang, Shih-Chieh Chang, Wen-Ben Jone
2005 J jnl
Fault simulation and response compaction in full scan circuits using HOPE.
IEEE Trans. Instrum. Meas.
Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu
2005 J jnl
Revisiting response compaction in space for full-scan circuits with nonexhaustive test sets using concept of sequence characterization.
IEEE Trans. Instrum. Meas.
Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Mehmet Sahinoglu
2004 Misc conf
A Dual-Mode Built-In Self-Test Technique for Capacitive MEMS Devices.
VTS
Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
2004 J jnl
A parallel built-in self-diagnostic method for nontraditional faults of embedded memory arrays.
IEEE Trans. Instrum. Meas.
Vikram Arora, Wen-Ben Jone, Der-Cheng Huang, Sunil R. Das
2004 A conf
Location cache: a low-power L2 cache system.
ISLPED
Rui Min, Wen-Ben Jone, Yiming Hu
2004 Misc conf
Partial Tag Comparison: A New Technology for Power-Efficient Set-Associative Cache Designs.
VLSI Design
Rui Min, Zhiyong Xu, Yiming Hu, Wen-Ben Jone
2004 — conf
Phased tag cache: an efficient low power cache system.
ISCAS (2)
Rui Min, Wen-Ben Jone, Yiming Hu
2004 — conf
Scan Chain Fault Identification Using Weight-Based Codes for SoC Circuits.
Asian Test Symposium
Swaroop Ghosh, K. W. Lai, Wen-Ben Jone, Shih-Chieh Chang
2003 J jnl
An efficient BIST method for non-traditional faults of embedded memory arrays.
IEEE Trans. Instrum. Meas.
Wen-Ben Jone, Der-Cheng Huang, Sunil R. Das
2003 J jnl
Design theory and implementation for low-power segmented bus systems.
ACM Trans. Design Autom. Electr. Syst.
Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen
2003 J jnl
Embedded core test generation using broadcast test architecture and netlist scrambling.
IEEE Trans. Reliab.
J. H. Jiang, Wen-Ben Jone, Shih-Chieh Chang, Swaroop Ghosh
2003 J jnl
Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets.
IEEE Trans. Instrum. Meas.
Sunil R. Das, Made Sudarma, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone, Krishnendu Chakrabarty, Mehmet Sahinoglu
2002 J jnl
A parallel built-in self-diagnostic method for embedded memoryarrays.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Der-Cheng Huang, Wen-Ben Jone
2002 J jnl
A parallel transparent BIST method for embedded memory arrays bytolerating redundant operations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Der-Cheng Huang, Wen-Ben Jone
2002 J jnl
An efficient BIST method for distributed small buffers.
IEEE Trans. Very Large Scale Integr. Syst.
Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee
2002 J jnl
Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering.
IEEE Trans. Instrum. Meas.
Sunil R. Das, Jing Yi Liang, Emil M. Petriu, Mansour H. Assaf, Wen-Ben Jone, Krishnendu Chakrabarty
2001 Misc conf
A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers.
VLSI Design
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
2001 Misc conf
An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers.
VLSI Design
Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das
2001 J jnl
An adaptive path selection method for delay testing.
IEEE Trans. Instrum. Meas.
Wen-Ben Jone, Wu-Sung Yeh, Chingwei Yeh, Sunil R. Das
2001 J jnl
Charge-sharing alleviation and detection for CMOS domino circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shih-Chieh Chang, Ching-Hwa Cheng, Wen-Ben Jone, Shin-De Lee, Jinn-Shyan Wang
2001 J jnl
Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis.
VLSI Design
Wen-Ben Jone, Der-Cheng Huang, Shih-Chieh Chang, Sunil R. Das
2001 — conf
Embedded Core Testing Using Broadcast Test Architecture.
DFT
J. H. Jiang, Shih-Chieh Chang, Wen-Ben Jone
2001 J jnl
Fault tolerance in systems design in VLSI using data compression under constraints of failure probabilities.
IEEE Trans. Instrum. Meas.
Sunil R. Das, Chittoor V. Ramamoorthy, Mansour H. Assaf, Emil M. Petriu, Wen-Ben Jone
2001 J jnl
Random Pattern Testability Enhancement by Circuit Rewiring.
VLSI Design
Shih-Chieh Chang, Kwen-Yo Chen, Ching-Hsiang Cheng, Wen-Ben Jone, Sunil R. Das
2000 — conf
An efficient parallel transparent diagnostic BIST.
Asian Test Symposium
Der-Cheng Huang, Wen-Ben Jone
2000 — conf
Charge Sharing Fault Analysis and Testing for CMOS Domino Logic Circuits.
LATW
Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone
2000 — conf
Charge sharing fault analysis and testing for CMOS domino logic circuits.
Asian Test Symposium
Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang
2000 — conf
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits.
DFT
Ching-Hwa Cheng, Jinn-Shyan Wang, Shih-Chieh Chang, Wen-Ben Jone
2000 A conf
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation.
ICCAD
Ching-Hwa Cheng, Shih-Chieh Chang, Shin-De Li, Wen-Ben Jone, Jinn-Shyan Wang
2000 J jnl
TAIR: testability analysis by implication reasoning.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shih-Chieh Chang, Wen-Ben Jone, Shi-Sen Chang
1999 Misc conf
An Efficient BIST Method for Small Buffers.
VTS
Wen-Ben Jone, Der-Cheng Huang, S. C. Wu, Kuen-Jong Lee
1999 — conf
Charge Sharing Fault Detection for CMOS Domino Logic Circuits.
DFT
Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone
1999 A* conf
Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications.
DAC
Ching-Wei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone
1999 — conf
Power reduction through iterative gate sizing and voltage scaling.
ISCAS (1)
Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone
1999 J jnl
Segmented bus design for low-power systems.
IEEE Trans. Very Large Scale Integr. Syst.
J.-Y. Chen, Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, Tien-Fu Chen
1998 Misc conf
A Stochastic Method for Defect Level Analysis of Pseudorandom Testing.
VLSI Design
Wen-Ben Jone, Sunil R. Das
1998 A conf
A novel combinational testability analysis by considering signal correlation.
ITC
Shih-Chieh Chang, Shi-Sen Chang, Wen-Ben Jone, Chien-Chung Tsai
1998 A conf
A tree-structured LFSR synthesis scheme for pseudo-exhaustive testing of VLSI circuits.
ITC
Wen-Ben Jone, Jiann-Chyi Rau, Shih-Chieh Chang, Yu-Liang Wu
1998 J jnl
Confidence analysis for defect-level estimation of VLSI random testing.
ACM Trans. Design Autom. Electr. Syst.
Wen-Ben Jone, K. S. Tsai
1998 J jnl
Syndrome Signature in Output Compaction for VLSI Built-in Self-Test.
VLSI Design
Sunil R. Das, Nita Goel, Wen-Ben Jone, Amiya R. Nayak
1997 Misc conf
Delay Fault Coverage Enhancement Using Multiple Test Observation Times.
VLSI Design
Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das
1997 J jnl
Delay Fault Coverage Enhancement Using Variable Observation Times.
J. Electron. Test.
Wen-Ben Jone, Yun-Pan Ho, Sunil R. Das
1996 J jnl
PGEN: A Novel Approach to Sequential Circuit Test Generation.
VLSI Design
Wen-Ben Jone, Nigam Shah, Anita Gleason, Sunil R. Das
1996 J jnl
Pseudorandom test-length analysis using differential solutions.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dan Li, Wen-Ben Jone
1996 Misc conf
Syndrome signature in output compaction for VLSI BIST.
VLSI Design
Sunil R. Das, Nishith Goel, Wen-Ben Jone, Amiya R. Nayak
1995 J jnl
A coordinated circuit partitioning and test generation method for pseudo-exhaustive testing of VLSI circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wen-Ben Jone, Christos A. Papachristou
1995 Misc conf
An improved output compaction technique for built-in self-test in VLSI circuits.
VLSI Design
Sunil R. Das, H. T. Ho, Wen-Ben Jone, Amiya R. Nayak
1995 J jnl
CACOP-a random pattern testability analyzer.
IEEE Trans. Syst. Man Cybern.
Wen-Ben Jone, Sunil R. Das
1995 J jnl
On testing of sequential machines using circuit decomposition and stochastic modeling.
IEEE Trans. Syst. Man Cybern.
Sunil R. Das, Wen-Ben Jone, Amiya R. Nayak, Ian Choi
1995 J jnl
Realizing a high measure of confidence for defect level analysis of random testing [VLSI].
IEEE Trans. Very Large Scale Integr. Syst.
Wen-Ben Jone, Paresh Gondalia, Allan Gutjahr
1995 J jnl
Timing optimization by gate resizing and critical path identification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chen-Liang Fang, Wen-Ben Jone
1994 B conf
Designing General-Purpose Fault-Tolerant Distributed Systems - A Layered Approach.
ICPADS
Amiya R. Nayak, Wen-Ben Jone, Sunil R. Das
1994 J jnl
Multiple Fault Detection in Parity Checkers.
IEEE Trans. Computers
Wen-Ben Jone, Cheng-Juei Wu
1994 Misc conf
On Probabilistic Testing of Large-Scale Sequential Circuits Using Circuit Decomposition.
VLSI Design
Sunil R. Das, Wen-Ben Jone, Amiya Nayak, Ian Choi
1993 Misc conf
CACOP - A Random Pattern Testability Analyzer.
VLSI Design
Wen-Ben Jone, Sunil R. Das
1993 J jnl
Defect level estimation of circuit testing using sequential statistical analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wen-Ben Jone
1993 J jnl
Multiple fault testing using minimal single fault test set for fanout-free circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wen-Ben Jone, Patrick H. Madden
1993 C conf
On Multiple Fault Detection of Parity Checkers.
ISCAS
Cheng-Juei Wu, Wen-Ben Jone
1993 A conf
Realizing a High Measure of Confidence for Defect Level Analysis of Random Testing.
ITC
Paresh Gondalia, Allan Gutjahr, Wen-Ben Jone
1993 A* conf
Timing Optimization By Gate Resizing And Critical Path Identification.
DAC
Wen-Ben Jone, Chen-Liang Fang
1992 J jnl
On random testing for combinational circuits with a high measure of confidence.
IEEE Trans. Syst. Man Cybern.
Sunil R. Das, Wen-Ben Jone
1991 J jnl
Analysis of Hamming count compaction scheme.
J. Electron. Test.
Wen-Ben Jone, Anita Gleason
1991 A conf
Defect Level Estimation of Random and Pseudorandom Testing.
ITC
Wen-Ben Jone
1991 C conf
Reduced Hamming Count and Its Aliasing Probability.
ICCD
Anita Gleason, Wen-Ben Jone
1990 J jnl
Multiple-output parity bit signature for exhaustive testing.
J. Electron. Test.
Wen-Ben Jone, Sunil R. Das
1990 J jnl
Probabilistic modeling and fault analysis in sequential logic using computer simulation.
IEEE Trans. Syst. Man Cybern.
Sunil R. Das, Wen-Ben Jone, K. L. Wong
1989 A* conf
A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing.
DAC
Wen-Ben Jone, Christos A. Papachristou
1989 A* conf
A Scheme for Overlaying Concurrent Testing of VLSI Circuits.
DAC
Wen-Ben Jone, Christos A. Papachristou, M. Pereira
1989 C conf
Hamming count-a compaction testing technique.
ICCD
Anita Gleason, Wen-Ben Jone