Weizheng Wang

28 papers Journal 25Unranked 3
YearRankTypeTitle / Venue / Authors
2025 J jnl
Low-Power and High-Speed SRAM Cells With Double-Node Upset Self-Recovery for Reliable Applications.
IEEE Trans. Very Large Scale Integr. Syst.
Shuo Cai, Xinjie Liang, Zhu Huang, Weizheng Wang, Fei Yu
2025 J jnl
SSA: An Effective Secure Scan Architecture Based on Hidden, Randomly Inserted Keys and PUF.
IEEE Internet Things J.
Weizheng Wang, Zhizhi Wu, Jinhai Chen, Peng Liu, Shuo Cai, Neal N. Xiong
2024 J jnl
A Low-Overhead and High-Security Scan Design Based on Scan Obfuscation.
IEEE Access
Weizheng Wang, Xingxing Gong, Shuo Cai, Jiamin Liu, Xiangqi Wang
2024 J jnl
A secure scan architecture using dynamic key to thwart scan-based side-channel attacks.
Microelectron. J.
Weizheng Wang, Jinhai Chen, Xianmin Pan
2024 J jnl
DAF: An Effective Design-for-Testability Authorization Framework Based on Obfuscation Mechanisms for Defending Complex Attacks.
IEEE Internet Things J.
Weizheng Wang, Xingxing Gong, Xiangqi Wang, Shuo Cai, Peng Liu, Neal N. Xiong
2023 — conf
A Low-Delay Quadruple-Node-Upset Self-Recoverable Latch Design.
ATS
Shuo Cai, Jiangbiao Ouyang, Yan Wen, Weizheng Wang, Fei Yu
2023 J jnl
A highly reliable and low-power cross-coupled 18T SRAM cell.
Microelectron. J.
Shuo Cai, Yan Wen, Jiangbiao Ouyang, Weizheng Wang, Fei Yu, Bo Li
2023 J jnl
A secure scan architecture using parallel latch-based lock.
Integr.
Weizheng Wang, Jian Liang, Xiangqi Wang, Xianmin Pan, Shuo Cai
2023 J jnl
Four-input-C-element-based multiple-node-upset-self-recoverable latch designs.
Integr.
Shuo Cai, Caicai Xie, Yan Wen, Weizheng Wang, Fei Yu, Lairong Yin
2023 J jnl
Low-power and high-speed SRAM cells for double-node-upset recovery.
Integr.
Shuo Cai, Yan Wen, Caicai Xie, Weizheng Wang, Fei Yu
2022 J jnl
An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation.
J. Electron. Test.
Shuo Cai, Binyong He, Sicheng Wu, Jin Wang, Weizheng Wang, Fei Yu
2022 J jnl
Ensuring Cryptography Chips Security by Preventing Scan-Based Side-Channel Attacks With Improved DFT Architecture.
IEEE Trans. Syst. Man Cybern. Syst.
Weizheng Wang, Xiangqi Wang, Jin Wang, Neal N. Xiong, Shuo Cai, Peng Liu
2021 — conf
A Low-Cost Quadruple-Node-Upset Self-Recoverable Latch Design.
ITC-Asia
Shuo Cai, Caicai Xie, Yan Wen, Weizheng Wang
2021 J jnl
Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory.
IEEE Trans. Emerg. Top. Comput.
Peng Liu, Zhiqiang You, Jigang Wu, Michael Elimu, Weizheng Wang, Shuo Cai, Yinhe Han
2020 J jnl
Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults.
J. Electron. Test.
Shuo Cai, Binyong He, Weizheng Wang, Peng Liu, Fei Yu, Lairong Yin, Bo Li
2019 J jnl
A Secure DFT Architecture Protecting Crypto Chips Against Scan-Based Attacks.
IEEE Access
Weizheng Wang, Jincheng Wang, Wei Wang, Peng Liu, Shuo Cai
2019 J jnl
A word-frequency-preserving steganographic method based on synonym substitution.
Int. J. Comput. Sci. Eng.
Lingyun Xiang, Xiao Yang, Jiahe Zhang, Weizheng Wang
2019 J jnl
Enhancing Sensor Network Security with Improved Internal Hardware Design.
Sensors
Weizheng Wang, Zhuo Deng, Jin Wang
2019 J jnl
Securing Cryptographic Chips against Scan-Based Attacks in Wireless Sensor Network Applications.
Sensors
Weizheng Wang, Zhuo Deng, Jin Wang, Arun Kumar Sangaiah, Shuo Cai, Zafer Al-Makhadmeh, Amr Tolba
2019 J jnl
Single Event Transient Propagation Probabilities Analysis for Nanometer CMOS Circuits.
J. Electron. Test.
Shuo Cai, Weizheng Wang, Fei Yu, Binyong He
2018 — conf
Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory.
ATS
Peng Liu, Jigang Wu, Zhiqiang You, Michael Elimu, Weizheng Wang, Shuo Cai
2017 J jnl
Reliability evaluation of logic circuits based on transient faults propagation metrics.
IEICE Electron. Express
Shuo Cai, Fei Yu, Weizheng Wang, Tieqiao Liu, Peng Liu, Wei Wang
2016 J jnl
A 2.7 GHz Low-Phase-Noise LC-QVCO Using the Gate-Modulated Coupling Technique.
Wirel. Pers. Commun.
Fei Yu, Qiang Tang, Weizheng Wang, Honglin Wu
2015 J jnl
Logic operation-based DFT method and 1R memristive crossbar March-like test algorithm.
IEICE Electron. Express
Peng Liu, Zhiqiang You, Jishun Kuang, Zhipeng Hu, Weizheng Wang
2013 J jnl
Low power logic BIST with high test effectiveness.
IEICE Electron. Express
Weizheng Wang, Peng Liu, Shuo Cai, Lingyun Xiang
2012 J jnl
A scan disabling-based BAST scheme for test cost and test power reduction.
IEICE Electron. Express
Zhiqiang You, Weizheng Wang, Peng Liu, Jishun Kuang, Zheng Qin
2012 J jnl
Switching activity reduction for scan-based BIST using weighted scan input data.
IEICE Electron. Express
Weizheng Wang, Jishun Kuang, Peng Liu, Xin Peng, Zhiqiang You
2011 J jnl
A scan disabling-based BAST scheme for test cost reduction.
IEICE Electron. Express
Zhiqiang You, Weizheng Wang, Zhiping Dou, Peng Liu, Jishun Kuang