Weizhe Hua - RankMe

27 papers A* 12A 1Journal 13Unranked 1

Year	Rank	Type	Title / Venue / Authors
2024	A*	`conf`	Information Flow Control in Machine Learning through Modular Model Architecture. USENIX Security Symposium Trishita Tiwari, Suchin Gururangan, Chuan Guo, Weizhe Hua, Sanjay Kariyappa, Udit Gupta, Wenjie Xiong, Kiwan Maeng, Hsien-Hsin S. Lee, G. Edward Suh
2023	J	`jnl`	Information Flow Control in Machine Learning through Modular Model Architecture. CoRR Trishita Tiwari, Suchin Gururangan, Chuan Guo, Weizhe Hua, Sanjay Kariyappa, Udit Gupta, Wenjie Xiong, Kiwan Maeng, Hsien-Hsin S. Lee, G. Edward Suh
2022	A*	`conf`	GuardNN: secure accelerator architecture for privacy-preserving deep learning. DAC Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh
2022	A*	`conf`	MGX: near-zero overhead memory protection for data-intensive accelerators. ISCA Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh
2022	J	`jnl`	Reverse-Engineering CNN Models Using Side-Channel Attacks. IEEE Des. Test Weizhe Hua, Zhiru Zhang, G. Edward Suh
2022	A*	`conf`	SoftVN: efficient memory protection via software-provided version numbers. ISCA Muhammad Umar, Weizhe Hua, Zhiru Zhang, G. Edward Suh
2022	J	`jnl`	Structured Pruning is All You Need for Pruning CNNs at Initialization. CoRR Yaohui Cai, Weizhe Hua, Hongzheng Chen, G. Edward Suh, Christopher De Sa, Zhiru Zhang
2022	A*	`conf`	Transformer Quality in Linear Time. ICML Weizhe Hua, Zihang Dai, Hanxiao Liu, Quoc V. Le
2022	J	`jnl`	Transformer Quality in Linear Time. CoRR Weizhe Hua, Zihang Dai, Hanxiao Liu, Quoc V. Le
2021	A*	`conf`	BulletTrain: Accelerating Robust Neural Network Training via Boundary Example Mining. NeurIPS Weizhe Hua, Yichi Zhang, Chuan Guo, Zhiru Zhang, G. Edward Suh
2021	J	`jnl`	BulletTrain: Accelerating Robust Neural Network Training via Boundary Example Mining. CoRR Weizhe Hua, Yichi Zhang, Chuan Guo, Zhiru Zhang, G. Edward Suh
2021	J	`jnl`	Sinan: Data Driven Resource Management for Cloud Microservices. CoRR Yanqi Zhang, Weizhe Hua, Zhuangzhuang Zhou, G. Edward Suh, Christina Delimitrou
2021	J	`jnl`	Sinan: Data-Driven, QoS-Aware Cluster Management for Microservices. CoRR Yanqi Zhang, Weizhe Hua, Zhuangzhuang Zhou, G. Edward Suh, Christina Delimitrou
2021	A*	`conf`	Sinan: ML-based and QoS-aware resource management for cloud microservices. ASPLOS Yanqi Zhang, Weizhe Hua, Zhuangzhuang Zhou, G. Edward Suh, Christina Delimitrou
2020	J	`jnl`	Contrastive Weight Regularization for Large Minibatch SGD. CoRR Qiwei Yuan, Weizhe Hua, Yi Zhou, Cunxi Yu
2020	J	`jnl`	GuardNN: Secure DNN Accelerator for Privacy-Preserving Deep Learning. CoRR Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh
2020	J	`jnl`	MgX: Near-Zero Overhead Memory Protection with an Application to Secure DNN Acceleration. CoRR Weizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh
2020	A*	`conf`	Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations. ICLR Yichi Zhang, Ritchie Zhao, Weizhe Hua, Nayun Xu, G. Edward Suh, Zhiru Zhang
2020	J	`jnl`	Precision Gating: Improving Neural Network Efficiency with Dynamic Dual-Precision Activations. CoRR Yichi Zhang, Ritchie Zhao, Weizhe Hua, Nayun Xu, G. Edward Suh, Zhiru Zhang
2019	A*	`conf`	Boosting the Performance of CNN Accelerators with Dynamic Fine-Grained Channel Gating. MICRO Weizhe Hua, Yuan Zhou, Christopher De Sa, Zhiru Zhang, G. Edward Suh
2019	A*	`conf`	Channel Gating Neural Networks. NeurIPS Weizhe Hua, Yuan Zhou, Christopher De Sa, Zhiru Zhang, G. Edward Suh
2018	J	`jnl`	Channel Gating Neural Networks. CoRR Weizhe Hua, Christopher De Sa, Zhiru Zhang, G. Edward Suh
2018	A*	`conf`	Reverse engineering convolutional neural networks through side-channel information leaks. DAC Weizhe Hua, Zhiru Zhang, G. Edward Suh
2017	A*	`conf`	Secure Information Flow Verification with Mutable Dependent Types. DAC Andrew Ferraiuolo, Weizhe Hua, Andrew C. Myers, G. Edward Suh
2016	J	`jnl`	A Low-Power Low-Area Error-Detecting Latch for Resilient Architectures in 28-nm FDSOI. IEEE Trans. Circuits Syst. II Express Briefs Ramy N. Tadros, Weizhe Hua, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel
2016	—	`conf`	Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications. ASYNC Ramy N. Tadros, Weizhe Hua, Matheus Gibiluka, Matheus T. Moreira, Ney Laert Vilar Calazans, Peter A. Beerel
2016	A	`conf`	Low Area, Low Power, Robust, Highly Sensitive Error Detecting Latch for Resilient Architectures. ISLPED Weizhe Hua, Ramy N. Tadros, Peter A. Beerel