Weixin Gai - RankMe

44 papers C 18Journal 9Unranked 17

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	8.4 A 112Gb/S/Wire Single-Ended Simultaneous Bi-Directional Transceiver with Dynamic Equalizer for Die-to-Die Interface in 28nm CMOS. ISSCC Zhiwen Huang, Zhifei Wang, Bingyi Ye, Tianchen Ye, Dunshan Yu, Wei Wang, Weixin Gai
2025	—	`conf`	25.5 A 99.5mW/Port DC-to-40GHz Integrated Channel Analyzer for High-Density Signal Integrity Measurement in 28nm CMOS. ISSCC Guangdong Wu, Yuanliang Li, Bingyi Ye, Fangzhu Li, Xin Liu, Haowei Niu, Ruixu Wang, Dunshan Yu, Weixin Gai
2025	—	`conf`	A 1.11pJ/b 224Gb/s XSR Receiver with Slice-Based CTLE and PI-Based Clock Generator in 12nm CMOS. ISSCC Bingyi Ye, Tianchen Ye, Tianyuan Zhong, Zhiwen Huang, Lei Shen, Boyang Zhang, Dunshan Yu, Yandong He, Weixin Gai
2025	J	`jnl`	A 4×106 Gb/s Mixed-Signal PAM-4 Transceivers for Optical Direct-Detect Applications With Adaptive Linearity Compensation in 28-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Boyang Zhang, Tianchen Ye, Zhifei Wang, Xin Liu, Tianyuan Zhong, Ruixu Wang, Weixin Gai
2025	—	`conf`	A 50Gb/s Burst-Mode NRZ Receiver with 5-Tap FFE, 7-Tap DFE and 15ns Lock Time in 28nm CMOS for Symmetric 50G-PON. ISSCC Boyang Zhang, Tianchen Ye, Shuaizhe Ma, Tianyuan Zhong, Xin Liu, Feiyang Zhang, Bingyi Ye, Dan Li, Weixin Gai
2025	—	`conf`	A 64Gb/s/wire 10.5Tb/s/mm/Layer Single-Ended Simultaneous Bi-Directional Transceiver with Echo and Crosstalk Cancellation for a Die-to-Die Interface in 28nm CMOS. ISSCC Zhifei Wang, Zhiwen Huang, Tianchen Ye, Bingyi Ye, Fangzhu Li, Wei Wang, Dunshan Yu, Weixin Gai
2024	—	`conf`	A 200-Gb/s PAM-4 Transmitter with 1.6-Vppd Output Swing and Clock Skew Correction in 12-nm FinFET. VLSI Technology and Circuits Boyang Zhang, Zhifei Wang, Zeze Feng, Tianchen Ye, Bingyi Ye, Zixu Wang, Weixin Gai
2024	J	`jnl`	A Five-Tap Delay-Line-Based Feed-Forward-Equalizer for 200-Gb/s Wireline Receiver in 28-nm CMOS. IEEE J. Solid State Circuits Bingyi Ye, Guangdong Wu, Weixin Gai, Kai Sheng, Yandong He
2023	—	`conf`	A 0.43pJ/b 200Gb/s 5-Tap Delay-Line-Based Receiver FFE with Low-Frequency Equalization in 28nm CMOS. ISSCC Bingyi Ye, Guangdong Wu, Weixin Gai, Kai Sheng, Yandong He
2023	—	`conf`	A 128Gb/s PAM-4 Transmitter with Programmable-Width Pulse Generator and Pattern-Dependent Pre-Emphasis in 28nm CMOS. ISSCC Kai Sheng, Weixin Gai, Zeze Feng, Haowei Niu, Bingyi Ye, Hang Zhou
2023	J	`jnl`	A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS. IEEE J. Solid State Circuits Bingyi Ye, Kai Sheng, Weixin Gai, Haowei Niu, Boyang Zhang, Yandong He, Song Jia, Congcong Chen, Jiaqi Yu
2023	J	`jnl`	A 4.6-pJ/b 200-Gb/s Analog DP-QPSK Coherent Optical Receiver in 28-nm CMOS. IEEE J. Solid State Circuits Kai Sheng, Haowei Niu, Boyang Zhang, Weixin Gai, Bingyi Ye, Hang Zhou, Congcong Chen
2022	—	`conf`	A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS. ISSCC Bingyi Ye, Kai Sheng, Weixin Gai, Haowei Niu, Boyang Zhang, Yandong He, Song Jia, Congcong Chen, Jiaqi Yu
2022	—	`conf`	A 4.6pJ/b 200Gb/s Analog DP-QPSK Coherent Optical Receiver in 28nm CMOS. ISSCC Kai Sheng, Haowei Niu, Boyang Zhang, Weixin Gai, Bingyi Ye, Hang Zhou, Congcong Chen
2022	C	`conf`	A High-Linearity 14GHz 7b Phase Interpolator for Ultra-High-Speed Wireline Applications. ISCAS Ninghuang Li, Weixin Gai, Bingyi Ye, Haowei Niu, Lei Lu
2022	J	`jnl`	A Residue Amplifier with 85 dB DC Gain and 15 GHz Closed-Loop Bandwidth for 14-Bit 3GSPS Pipeline ADC. Circuits Syst. Signal Process. Cece Huang, Weixin Gai, Yuanfu Zhao, Yafei Ji, Fei Chu, Tieliang Zhang
2022	—	`conf`	An Input Buffer with 85dB SFDR for High-Speed Pipeline ADC. ICTA Cece Huang, Yuanfu Zhao, Yafei Ji, Xin Yang, Tieliang Zhang, Weixin Gai
2021	J	`jnl`	56 Gb/s PAM4 receiver with an overshoot compensation scheme in 28 nm CMOS technology. Microelectron. J. Ai He, Weixin Gai, Bingyi Ye, Boyang Zhang, Kai Sheng, Yuanliang Li
2021	C	`conf`	A 14GHz Cascade Differential-Capacitor-Based DCO with Resistor-Biased Buffer. ISCAS Dong Yanchi, Weixin Gai, Xiao Xiang, Haowei Niu
2021	C	`conf`	A 2-Bit 4-Level 4-Wire 56Gb/s Transceiver in 14nm FinFET. ISCAS Kai Sheng, Linqi Shi, Weixin Gai, Qianting Hua, Peng Lin
2021	C	`conf`	A 25Gb/s 185mW PAM-4 Receiver with 4-Tap Adaptive DFE and Sampling Clock Optimization in 55nm CMOS. ISCAS Liangxiao Tang, Weixin Gai, Chih-Kong Ken Yang, Bingyi Ye, Congcong Chen
2021	—	`conf`	An Adaptive DFE Using Pattern-Dependent Data-Level Reference in 28 nm CMOS Technology. ASICON Ai He, Weixin Gai, Kai Sheng, Ninghuang Li
2021	C	`conf`	Analog Signal Processing Circuits for a 400Gb/s 16QAM Optical Coherent Receiver. ISCAS Boyang Zhang, Weixin Gai, Haowei Niu, Bingyi Ye, Kai Sheng, Tianjian Zuo, Lei Liu
2021	J	`jnl`	Equal-slope baud-rate CDR algorithm with optimized eye opening. Microelectron. J. Xiao Xiang, Weixin Gai, Ai He, Hang Zhou, Dong Yanchi
2019	C	`conf`	An 8-12GHz 0.92° Phase Error Quadrature Clock Generator Based on Two-Stage Poly Phase Filter with Intermediate Point Compensation. ISCAS Xiao Xiang, Weixin Gai, Linqi Shi, Ai He, Kai Sheng
2019	—	`conf`	Design of an Adaptive Loop Gain Controller Based on Auto-correlation Detection Scheme in All-Digital Phase-Locked Loop. ASICON Sheng Zhang, Song Jia, Hanzun Zhang, Rongshan Wei, Weixin Gai
2019	C	`conf`	Double-Comparison Settling Error Correction Scheme for Binary Scaled SAR ADCs. ISCAS Ai He, Weixin Gai, Yufan Feng, Zhongzhu Pu, Xiao Xiang
2018	C	`conf`	A 108fs ISCAS Yinxuan Lyu, Jianhua Feng, Chenfeng Tu, Linqi Shi, Hongfei Ye, Weixin Gai, Dunshan Yu
2018	—	`conf`	A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS. ISSCC Liangxiao Tang, Weixin Gai, Linqi Shi, Xiao Xiang, Kai Sheng, Ai He
2018	C	`conf`	A Sub-ps Integrated-Jitter 10 GHz ADPLL with Fractional Capacitor. ISCAS Linqi Shi, Weixin Gai, Jichao Huang, Liangxiao Tang, Xiao Xiang
2018	C	`conf`	An 8.52-11.34 GHz 0.34° Phase Error Quadrature Clock Generator with Time-Voltage-Time Convertor. ISCAS Linqi Shi, Weixin Gai, Xiaoting Zhi, Liangxiao Tang, Xiao Xiang
2017	C	`conf`	A 40 Gb/s 74.9 mW PAM4 receiver with novel clock and data recovery. ISCAS Liangxiao Tang, Weixin Gai, Linqi Shi, Xiao Xiang
2016	C	`conf`	A 1.27mW 20Gbps 1: 16 DEMUX with a symmetrical-edge-delay sense amplifier. ISCAS Shihao Li, Weixin Gai, Xiao Xiang, Liangxiao Tang, Jichao Huang, Tong Zhao, Xiaoting Zhi
2016	C	`conf`	PAM4 receiver with adaptive threshold voltage and adaptive decision feedback equalizer. ISCAS Liangxiao Tang, Weixin Gai, Linqi Shi
2015	C	`conf`	A 2-tap 40-Gb/s 4-PAM transmitter with level selection based pre-emphasis. ISCAS Yang Wang, Weixin Gai
2015	C	`conf`	A novel 6-Gbps half-rate SST transmitter with impedance calibration and adjustable pre-emphasis. ISCAS Jincai Liu, Weixin Gai, Liangxiao Tang
2013	C	`conf`	A 2.7-GHz digitally-controlled ring oscillator with supply sensitivity of 0.0014%-fDCO/1%-VDD using digital current-regulated tuning. ISCAS Te Han, Weixin Gai
2013	C	`conf`	A novel frequency search algorithm to achieve fast locking without phase tracking in ADPLL. ISCAS Bohan Wu, Weixin Gai, Te Han
2013	C	`conf`	SSC tracking analysis and a deeper-SSC estimator. ISCAS Yaming Zhang, Weixin Gai
2009	J	`jnl`	A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control. IEEE J. Solid State Circuits Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone
2009	—	`conf`	A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control. ISSCC Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone
2007	—	`conf`	A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer. ISSCC Yasuo Hidaka, Weixin Gai, Akira Hattori, Takeshi Horie, Jian Jiang, Kouichi Kanda, Yoichi Koyanagi, Satoshi Matsubara, Hideki Osone
2007	—	`conf`	Design Consideration of 6.25 Gbps Signaling for High-Performance Server. ASP-DAC Jian Hong Jiang, Weixin Gai, Akira Hattori, Yasuo Hidaka, Takeshi Horie, Yoichi Koyanagi, Hideki Osone
2003	J	`jnl`	A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems. J. VLSI Signal Process. Xingjun Wu, Hongyi Chen, Yihe Sun, Weixin Gai