Weiwu Hu

79 papers A* 5A 7B 2C 8Misc 1Journal 33Unranked 23
YearRankTypeTitle / Venue / Authors
2016 J jnl
An introduction to CPU and DSP design in China.
Sci. China Inf. Sci.
Weiwu Hu, Yifu Zhang, Jie Fu
2015 A conf
HERMES: a fast cross-ISA binary translator with post-optimization.
CGO
Xiaochun Zhang, Qi Guo, Yunji Chen, Tianshi Chen, Weiwu Hu
2014 — conf
A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS.
VLSIC
Hao Li, Shuai Chen, Liqiong Yang, Rui Bai, Weiwu Hu, Freeman Y. Zhong, Samuel Palermo, Patrick Yin Chiang
2014 J jnl
An 8-Core MIPS-Compatible Processor in 32/28 nm Bulk CMOS.
IEEE J. Solid State Circuits
Weiwu Hu, Liang Yang, Bao-Xia Fan, Huandong Wang, Yunji Chen
2014 J jnl
Auxiliary stream for optimizing memory access of video decoders.
Sci. China Inf. Sci.
Shaoli Liu, Ling Li, Yunji Chen, Weiwu Hu
2014 J jnl
Pre-Silicon Bug Forecast.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Qi Guo, Tianshi Chen, Yunji Chen, Rui Wang, Huanhuan Chen, Weiwu Hu, Guoliang Chen
2013 — conf
A 1.2 pJ/b 6.4 Gb/s 8+1-lane forwarded-clock receiver with PVT-variation-tolerant all-digital clock and data recovery in 28nm CMOS.
CICC
Shuai Chen, Hao Li, Liqiong Yang, Zongren Yang, Weiwu Hu, Patrick Yin Chiang
2013 J jnl
Deterministic Replay Using Global Clock.
ACM Trans. Archit. Code Optim.
Yunji Chen, Tianshi Chen, Ling Li, Ruiyang Wu, Dao-Fu Liu, Weiwu Hu
2013 — conf
Godson-3B1500: A 32nm 1.35GHz 40W 172.8GFLOPS 8-core processor.
ISSCC
Weiwu Hu, Yifu Zhang, Liang Yang, Bao-Xia Fan, Yunji Chen, Shi-Qiang Zhong, Huandong Wang, Zichu Qi, Pengyu Wang, Xiang Gao, Xu Yang, Bin Xiao, Hongsheng Wang, Zongren Yang, Liqiong Yang, Shuai Chen
2013 J jnl
LDet: Determinizing Asynchronous Transfer for Postsilicon Debugging.
IEEE Trans. Computers
Yunji Chen, Tianshi Chen, Ling Li, Lei Li, Liang Yang, Menghao Su, Weiwu Hu
2013 J jnl
Microarchitectural design space exploration made fast.
Microprocess. Microsystems
Qi Guo, Tianshi Chen, Yunji Chen, Ling Li, Weiwu Hu
2012 J jnl
Linear Time Memory Consistency Verification.
IEEE Trans. Computers
Weiwu Hu, Yunji Chen, Tianshi Chen, Cheng Qian, Lei Li
2012 J jnl
Program Regularization in Memory Consistency Verification.
IEEE Trans. Parallel Distributed Syst.
Yunji Chen, Lei Li, Tianshi Chen, Ling Li, Lei Wang, Xiaoxue Feng, Weiwu Hu
2012 A* conf
Statistical performance comparisons of computers.
HPCA
Tianshi Chen, Yunji Chen, Qi Guo, Olivier Temam, Yue Wu, Weiwu Hu
2011 — conf
Alpha Compression with Variable Data Formats.
Eurographics (Short Papers)
Yifei Jiang, Mindan Gui, Shuai Chen, Weiwu Hu
2011 J jnl
An FFT Performance Model for Optimizing General-Purpose Processor Architecture.
J. Comput. Sci. Technol.
Ling Li, Yunji Chen, Dao-Fu Liu, Cheng Qian, Weiwu Hu
2011 B conf
Brief announcement: program regularization in verifying memory consistency.
SPAA
Lei Li, Tianshi Chen, Yunji Chen, Ling Li, Cheng Qian, Weiwu Hu
2011 J jnl
Design for Testability Features of Godson-3 Multicore Microprocessor.
J. Comput. Sci. Technol.
Zichu Qi, Hui Liu, Xiangku Li, Weiwu Hu
2011 A* conf
Effective and Efficient Microprocessor Design Space Exploration Using Unlabeled Design Configurations.
IJCAI
Qi Guo, Tianshi Chen, Yunji Chen, Zhi-Hua Zhou, Weiwu Hu, Zhiwei Xu
2011 A conf
Empirical design bugs prediction for verification.
DATE
Qi Guo, Tianshi Chen, Haihua Shen, Yunji Chen, Yue Wu, Weiwu Hu
2011 — conf
Godson-3B: A 1GHz 40W 8-core 128GFLOPS processor in 65nm CMOS.
ISSCC
Weiwu Hu, Ru Wang, Yunji Chen, Bao-Xia Fan, Shi-Qiang Zhong, Xiang Gao, Zichu Qi, Xu Yang
2011 J jnl
Physical Implementation of the Eight-Core Godson-3B Microprocessor.
J. Comput. Sci. Technol.
Ru Wang, Bao-Xia Fan, Liang Yang, Yan-Ping Gao, Dong Liu, Bin Xiao, Jiang-Mei Wang, Yifu Zhang, Hong Wang, Weiwu Hu
2011 J jnl
Sinusoidal Clock Sampling for Multigigahertz ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Rui Bai, Jingguang Wang, Lingli Xia, Feng Zhang, Zongren Yang, Weiwu Hu, Patrick Chiang
2011 J jnl
The Godson Processors: Its Research, Development, and Contributions.
J. Comput. Sci. Technol.
Weiwu Hu, Yan-Ping Gao, Tianshi Chen, Jun-Hua Xiao
2010 A conf
A multi-FPGA based platform for emulating a 100m-transistor-scale processor with high-speed peripherals (abstract only).
FPGA
Huandong Wang, Xiang Gao, Yunji Chen, Dan Tang, Weiwu Hu
2010 A* conf
DMA cache: Using on-chip storage to architecturally separate I/O data from CPU data for improving I/O performance.
HPCA
Dan Tang, Yungang Bao, Weiwu Hu, Mingyu Chen
2010 Misc conf
Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power.
VLSI Design
Zichu Qi, Qi Guo, Ge Zhang, Xiangku Li, Weiwu Hu
2010 A* conf
LReplay: a pending period based deterministic replay scheme.
ISCA
Yunji Chen, Weiwu Hu, Tianshi Chen, Ruiyang Wu
2010 — conf
On-the-Fly Reduction of Stimuli for Functional Verification.
Asian Test Symposium
Qi Guo, Tianshi Chen, Haihua Shen, Yunji Chen, Weiwu Hu
2010 — conf
Optimizing power and throughput for m-out-of-n encoded asynchronous circuits.
ISQED
Jun Xu, Ge Zhang, Weiwu Hu
2010 J jnl
System Architecture of Godson-3 Multi-Core Processors.
J. Comput. Sci. Technol.
Xiang Gao, Yunji Chen, Huandong Wang, Dan Tang, Weiwu Hu
2009 — conf
A Scalable Scan Architecture for Godson-3 Multicore Microprocessor.
Asian Test Symposium
Zichu Qi, Hui Liu, Xiangku Li, Da Wang, Yinhe Han, Huawei Li, Weiwu Hu
2009 — conf
A case study of improving at-speed testing coverage of a gigahertz microprocessor.
ICECS
Zichu Qi, Hui Liu, Xiangku Li, Jun Xu, Weiwu Hu
2009 C conf
Efficient binary translation system with low hardware cost.
ICCD
Weiwu Hu, Qi Liu, Jian Wang, Songsong Cai, Menghao Su, Xiaoyu Li
2009 A* conf
Fast complete memory consistency verification.
HPCA
Yunji Chen, Yi Lv, Weiwu Hu, Tianshi Chen, Haihua Shen, Pengyu Wang, Hong Pan
2009 J jnl
Global Clock, Physical Time Order and Pending Period Analysis in Multiprocessor Systems
CoRR
Yunji Chen, Tianshi Chen, Weiwu Hu
2009 J jnl
Godson-3: A Scalable Multicore RISC Processor with x86 Emulation.
IEEE Micro
Weiwu Hu, Jian Wang, Xiang Gao, Yunji Chen, Qi Liu, Guojie Li
2009 C conf
Measuring and Compensating for Process Mismatch-induced, Reference Spurs in Phase-locked Loops using a Sub-sampled DSP.
ISCAS
Zhuo Gao, D. Kesharwani, Patrick Chiang, Weiwu Hu
2008 — conf
A High Speed CMOS Transmitter and Rail-to-Rail Receiver.
DELTA
Feng Zhang, Zongren Yang, Wei Feng, Hao Cui, Lingyi Huang, Weiwu Hu
2008 C conf
A synchronized variable frequency clock scheme in chip multiprocessors.
ISCAS
Qifei Fan, Ge Zhang, Weiwu Hu
2008 A conf
An interconnect-aware power efficient cache coherence protocol for CMPs.
IPDPS
Hongbo Zeng, Jun Wang, Ge Zhang, Weiwu Hu
2008 J jnl
Chip Multithreaded Consistency Model.
J. Comput. Sci. Technol.
Zusong Li, Dandan Huan, Weiwu Hu, Zhimin Tang
2008 C conf
Fetching Primary and Redundant Instructions in Turn for a Fault-Tolerant Embedded Microprocessor.
PRDC
Shijian Zhang, Weiwu Hu
2008 J jnl
Making Effective Decisions in Computer Architects' Real-World: Lessons and Experiences with Godson-2 Processor Designs.
J. Comput. Sci. Technol.
Weiwu Hu, Jian Wang
2008 — conf
Testing content addressable memories using instructions and march-like algorithms.
ICECS
Lin Ma, Yunji Chen, Menghao Su, Zichu Qi, Heng Zhang, Weiwu Hu
2007 J jnl
Accelerating sequential programs on Chip Multiprocessors via Dynamic Prefetching Thread.
Microprocess. Microsystems
Hou Rui, Longbing Zhang, Weiwu Hu
2007 C conf
An Efficient Error Control Scheme for Chip-to-Chip Optical Interconnects.
ISCAS
Jun Wang, Ge Zhang, Weiwu Hu
2007 — conf
CREA: A Checkpoint Based Reliable Micro-architecture for Superscalar Processors.
ATS
Shijian Zhang, Weiwu Hu
2007 — conf
Concerning with On-Chip Network Features to Improve Cache Coherence Protocols for CMPs.
Asia-Pacific Computer Systems Architecture Conference
Hongbo Zeng, Kun Huang, Ming Wu, Weiwu Hu
2007 J jnl
Implementing a 1GHz Four-Issue Out-of-Order Execution Microprocessor in a Standard Cell ASIC Methodology.
J. Comput. Sci. Technol.
Weiwu Hu, Ji-Ye Zhao, Shi-Qiang Zhong, Xu Yang, Elio Guidetti, Chris Wu
2006 — conf
A Hybrid Hardware/Software Generated Prefetching Thread Mechanism on Chip Multiprocessors.
Euro-Par
Hou Rui, Longbing Zhang, Weiwu Hu
2006 J jnl
High Performance General-Purpose Microprocessors: Past and Future.
J. Comput. Sci. Technol.
Weiwu Hu, Rui Hou, Jun-Hua Xiao, Long-Bin Zhang
2006 C conf
Microarchitecture and Performance Analysis of Godson-2 SMT Processor.
ICCD
Zusong Li, Xianchao Xu, Weiwu Hu, Zhimin Tang
2006 J jnl
Parallel Error Detection for Leading Zero Anticipation.
J. Comput. Sci. Technol.
Ge Zhang, Weiwu Hu, Zichu Qi
2006 — conf
Processor Directed Dynamic Page Policy.
Asia-Pacific Computer Systems Architecture Conference
Dandan Huan, Zusong Li, Weiwu Hu, Zhiyong Liu
2005 — conf
A Memory Bandwidth Effective Cache Store Miss Policy.
Asia-Pacific Computer Systems Architecture Conference
Hou Rui, Fuxin Zhang, Weiwu Hu
2005 — conf
A novel design of leading zero anticipation circuit with parallel error detection.
ISCAS (1)
Ge Zhang, Zichu Qi, Weiwu Hu
2005 J jnl
Microarchitecture of the Godson-2 Processor.
J. Comput. Sci. Technol.
Weiwu Hu, Fuxin Zhang, Zusong Li
2004 C conf
A shared virtual memory network with fast remote direct memory access and message passing.
CLUSTER
Gang Shi, Mingchang Hu, Hongda Yin, Weiwu Hu, Zhimin Tang
2001 A conf
A Comparison of Two Strategies of Dynamic Data Prefetching in Software DSM.
IPDPS
Haiming Liu, Weiwu Hu
2001 C conf
Communication with Threads in Software DSM.
CLUSTER
Weiwu Hu, Gang Shi, Fuxin Zhang
2001 J jnl
Dynamic Data Prefetching in Home-Based Software DSMs.
J. Comput. Sci. Technol.
Weiwu Hu, Fuxin Zhang, Haiming Liu
2001 J jnl
Optimizing Home-Based Software DSM Protocols.
Clust. Comput.
Weiwu Hu, Weisong Shi, Zhimin Tang
2000 — conf
A New Home-Based Software DSM Protocol for SMP Clusters.
Euro-Par
Weiwu Hu, Fuxin Zhang, Haiming Liu
1999 A conf
Adaptive Write Detection in Home-based Software DSMs.
HPDC
Weiwu Hu, Weisong Shi, Zhimin Tang
1999 A conf
Dynamic Task Migration in Home-based Software DSM Systems.
HPDC
Weisong Shi, Weiwu Hu, Zhimin Tang, M. Rasit Eskicioglu
1999 — conf
Evaluation of the JIAJIA Software DSM System on High Performance Computer Architectures.
HICSS
M. Rasit Eskicioglu, T. Anthony Marsland, Weiwu Hu, Weisong Shi
1999 — conf
JIAJIA: A Software DSM System Based on a New Cache Coherence Protocol.
HPCN Europe
Weiwu Hu, Weisong Shi, Zhimin Tang
1999 — conf
Reducing System Overheads in Home-based Software DSMs.
IPPS/SPDP
Weiwu Hu, Weisong Shi, Zhimin Tang
1999 J jnl
Where does the time go in software DSMs? - Experiences with JIAJIA.
J. Comput. Sci. Technol.
Weisong Shi, Weiwu Hu, Zhimin Tang
1999 — conf
Write Detection in Home-Based Software DSMs.
Euro-Par
Weiwu Hu, Weisong Shi, Zhimin Tang
1998 J jnl
A framework of memory consistency models.
J. Comput. Sci. Technol.
Weiwu Hu, Weisong Shi, Zhimin Tang
1998 J jnl
A lock-based cache coherence protocol for scope consistency.
J. Comput. Sci. Technol.
Weiwu Hu, Weisong Shi, Zhimin Tang, Ming Li
1998 J jnl
Out-of-order execution in sequentially consistent shared-memory systems: Theory and experiments.
J. Comput. Sci. Technol.
Weiwu Hu, Peisu Xia
1997 J jnl
An Interaction of Coherence Protocols and Memory Consistency Models in DSM Systems.
ACM SIGOPS Oper. Syst. Rev.
Weisong Shi, Weiwu Hu, Zhimin Tang
1997 J jnl
An innovative implementation for directory-based cache coherence in shared memory multiprocessors.
SIGARCH Comput. Archit. News
Weisong Shi, Weiwu Hu, Ming Zhu
1997 J jnl
Out-of-order execution in sequentially consistent shared-memory systems.
SIGARCH Comput. Archit. News
Weiwu Hu, Peisu Xia
1996 — conf
Event Ordering Condition for Correct Executions in Shared-Memory Systems.
ISPAN
Weiwu Hu, Peisu Xia
1994 B conf
A Graph Model for Investigating Memory Consistency.
ICPADS
Weiwu Hu