| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2025 | J | jnl |
IEEE Trans. Instrum. Meas.
|
| 2025 | J | jnl |
Symmetry
|
| 2023 | J | jnl |
RAIRO Oper. Res.
|
| 2021 | J | jnl |
Neurocomputing
|
| 2019 | J | jnl |
Neurocomputing
|
| 2019 | J | jnl |
Int. J. Inf. Comput. Secur.
|
| 2019 | A* | conf |
AAAI
|
| 2018 | J | jnl |
SIAM J. Sci. Comput.
|
| 2018 | A | conf |
CIKM
|
| 2018 | J | jnl |
Inf. Sci.
|
| 2017 | — | conf |
EIDWT
|
| 2017 | — | conf |
BIBM
|
| 2017 | J | jnl |
Comput. Manag. Sci.
|
| 2017 | A* | conf |
AAAI
|
| 2017 | A* | conf |
AAAI
|
| 2017 | J | jnl |
J. Sensors
|
| 2016 | J | jnl |
IEEE Trans. Multim.
|
| 2016 | — | conf |
3PGCIC
|
| 2016 | A* | conf |
IJCAI
|
| 2015 | A* | conf |
IJCAI
|
| 2015 | A* | conf |
AAAI
|
| 2014 | — | conf |
VLSI-DAT
|
| 2014 | A* | conf |
AAAI
|
| 2014 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2013 | J | jnl |
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
|
| 2013 | C | conf |
ISCAS
|
| 2013 | — | conf |
A highly pipelined VLSI architecture for all modes and block sizes intra prediction in HEVC encoder.
ASICON
|
| 2013 | J | jnl |
A pipelined VLSI architecture for Sample Adaptive Offset (SAO) filter and deblocking filter of HEVC.
IEICE Electron. Express
|
| 2012 | J | jnl |
IEICE Trans. Electron.
|
| 2012 | A | conf |
ICME
|
| 2005 | C | conf |
BROADNETS
|