Weiwei Shan

119 papers A* 3A 4C 7Journal 52Unranked 53
YearRankTypeTitle / Venue / Authors
2026 — conf
30.1 A 28nm 127.54TFLOPS/W MXFP6 and 117.42TFLOPS/W MXFP8 Compute-in-Memory Macro with Adaptive-Preserved-Bit-Width and Serial-Dual-Bit-Sliding Schemes.
ISSCC
Xing Wang, Yucheng Du, Tianhui Jiao, Defa Wu, Xi Chen, Miaoyu Tang, Yi Yang, Zhichao Liu, An Guo, Gaoming Fu, Peng Li, Jun Dong, Bo Liu, Xinning Liu, Weiwei Shan, Hao Cai, Guangyu Sun, Lin Tong, Jun Yang, Xin Si
2026 — conf
BALANCE: Bit and Layer-Aware Lightweight ECC Design Method for In-Flash Computing Based LLM Inference Accelerator.
ASP-DAC
Changwei Yan, Lishuo Deng, Mingbo Hao, Cai Li, Weiwei Shan
2026 J jnl
Coupled disaster mechanisms and theoretical framework in multi-hazard scenarios: insights from non-coal mines.
Reliab. Eng. Syst. Saf.
Menglong Wu, Xiaobing Zhang, Weiwei Shan, Yang Liu, Yanfeng Jiang
2025 — conf
14.3 A 28nm 17.83-to-62.84TFLOPS/W Broadcast-Alignment Floating-Point CIM Macro with Non-Two's-Complement MAC for CNNs and Transformers.
ISSCC
Xing Wang, Tianhui Jiao, Yi Yang, Shaochen Li, Dongqi Li, An Guo, Yuhui Shi, Yuchen Tang, Jinwu Chen, Zhican Zhang, Zhichao Liu, Bo Liu, Weiwei Shan, Xin Wang, Hao Cai, Wenwu Zhu, Jun Yang, Xin Si
2025 — conf
14.6 A 28nm 64kb Bit-Rotated Hybrid-CIM Macro with an Embedded Sign-Bit-Processing Array and a Multi-Bit-Fusion Dual-Granularity Cooperative Quantizer.
ISSCC
Xi Chen, Shaochen Li, Zhican Zhang, Wentao Zheng, Xiao Tan, Yuchen Tang, Yuhui Shi, Lizheng Ren, Yibo Mai, Feiran Liu, Jinwu Chen, Zhaoyang Zhang, An Guo, Tianzhu Xiong, Bo Wang, Xinning Liu, Weiwei Shan, Bo Liu, Hao Cai, Jun Yang, Xin Si
2025 — conf
14.7 NeuroPilot: A 28nm, 69.4fJ/node and 0.22ns/node, 32×32 Mimetic-Path-Searching CIM-Macro with Dynamic-Logic Pilot PE and Dual-Direction Searching.
ISSCC
An Guo, Jingmin Zhang, Xingyu Pu, Yi Yang, Defa Wu, Yuchen Tang, Yuhui Shi, Yinghai Gao, Zhichao Liu, Bo Wang, Tianzhu Xiong, Zhaoyang Zhang, Xi Chen, Jinwu Chen, Feiran Liu, Xing Wang, Xinning Liu, Weiwei Shan, Bo Liu, Hao Cai, Xin Si, Jun Yang
2025 C conf
A 250M-2.5GHz Two-Stage Duty-Cycle Corrector with 10%-90% Correction Range and 3-Cycle Correction Latency for Mitigating Aging Effects.
ISCAS
Zhiting Li, Lishuo Deng, Cai Li, Changwei Yan, Zhangrui Qian, Weiwei Shan
2025 J jnl
A 4.69-TOPS/W Training, 2.34-μJ/Image Inference On-Chip Training Accelerator With Inference-Compatible Backpropagation and Design Space Exploration in 28-nm CMOS.
IEEE J. Solid State Circuits
Junyi Qian, Haitao Ge, Yicheng Lu, Weiwei Shan
2025 C conf
A 40nm Early-Warning AVFS Design with Path Activation-Based Monitoring Point Optimization.
ISCAS
Cai Li, Zhuoyuan Li, Kaize Zhou, Lishuo Deng, Junyi Qian, Xiaojie Yin, Kana Meng, Weiwei Shan
2025 J jnl
A Compound Timing Detection of Both Data Transition and Path Activation for Reliable In Situ Error Detection and Correction.
IEEE Trans. Very Large Scale Integr. Syst.
Lishuo Deng, Junyi Qian, Zhengguo Shen, Cai Li, Jingchen Wang, Zhangrui Qian, Ziyu Li, Longning Qi, Weiwei Shan
2025 J jnl
A High-Accuracy and Ultra-Energy-Efficient Cardiac Arrhythmia Classification Processor for Wearable Intelligent ECG Monitoring.
IEEE J. Solid State Circuits
Jiahao Liu, Ziyi Xie, Xiao Liu, Xu Wang, Jianbiao Xiao, Chaozheng Guo, Jiajing Fan, Qingsong Liu, Zhen Zhu, Sixu Li, Zhaomin Zhang, Siqi Yang, Weiwei Shan, Shuisheng Lin, Liang Zhou, Liang Chang, Shanshan Liu, Jun Zhou
2025 J jnl
A Proactive Droop Mitigation Technique Using Dual-Proportional-Derivative Controller Based on Current and Voltage Prediction.
IEEE J. Solid State Circuits
Kaize Zhou, Weiwei Shan, Keran Li, Zhuo Chen, Haitao Ge, Jun Yang
2025 J jnl
A Unified Early-Warning AVFS Design With Path Activation-Aware Monitoring Point Optimization.
IEEE Solid State Circuits Lett.
Cai Li, Kaize Zhou, Junyi Qian, Haochang Zhi, Weiwei Shan
2025 C conf
An All-Digital Voltage Droop Detector Utilizing a Multi-Phase Clock assisted Nyquist Counter.
ISCAS
Zhangrui Qian, Kaize Zhou, Yuxuan Du, Zhiting Li, Weiwei Shan
2025 J jnl
An On-Chip-Training Keyword-Spotting Chip Using Interleaved Pipeline and Computation-in-Memory Cluster in 28-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Junyi Qian, Cai Li, Long Chen, Ruidong Li, Tuo Li, Peng Cao, Xin Si, Weiwei Shan
2025 — conf
Analog Circuit Transfer Method Across Technology Nodes via Transistor Behavior.
ASP-DAC
Haochang Zhi, Jintao Li, Yun Li, Weiwei Shan
2025 — conf
Balancing Objective Optimization and Constraint Satisfaction for Robust Analog Circuit Optimization.
ASP-DAC
Jintao Li, Haochang Zhi, Jiang Xiao, Yanhan Zeng, Weiwei Shan, Yun Li
2025 J jnl
Closed-Loop Pole Analysis via Output Impedance in Miller-Compensated Amplifiers.
IEEE Trans. Circuits Syst. II Express Briefs
Haochang Zhi, Shaojie Xu, Jintao Li, Tong Zhou, Yun Li, Weiwei Shan, Wanyuan Qu
2025 A conf
Efficient Hold Buffer Optimization by Supply Noise-Aware Dynamic Timing Analysis.
DATE
Lishuo Deng, Changwei Yan, Cai Li, Zhuo Chen, Weiwei Shan
2025 J jnl
KVNAND: Efficient On-Device Large Language Model Inference Using DRAM-Free In-Flash Computing.
CoRR
Lishuo Deng, Shaojie Xu, Jinwu Chen, Changwei Yan, Jiajie Wang, Zhe Jiang, Weiwei Shan
2025 A* conf
UVLLM: An Automated Universal RTL Verification Framework using LLMs.
DAC
Yuchen Hu, Junhao Ye, Ke Xu, Jialin Sun, Shiyue Zhang, Xinyao Jiao, Dingrong Pan, Jie Zhou, Ning Wang, Weiwei Shan, Xinwei Fang, Xi Wang, Nan Guan, Zhe Jiang
2025 C conf
Variation-Adaptive Negative Bitline and Skip Bitline Pre-charge Scheme for Low-Power SRAM.
ISCAS
Lishuo Deng, Changwei Yan, Yiran Zhang, Xin Si, Weiwei Shan
2024 — conf
14.2 Proactive Voltage Droop Mitigation Using Dual-Proportional-Derivative Control Based on Current and Voltage Prediction Applied to a Multicore Processor in 28nm CMOS.
ISSCC
Weiwei Shan, Kaize Zhou, Keran Li, Yuxuan Du, Zhuo Chen, Junyi Qian, Haitao Ge, Jun Yang, Xin Si
2024 — conf
34.3 A 22nm 64kb Lightning-Like Hybrid Computing-in-Memory Macro with a Compressed Adder Tree and Analog-Storage Quantizers for Transformer and CNNs.
ISSCC
An Guo, Xi Chen, Fangyuan Dong, Jinwu Chen, Zhihang Yuan, Xing Hu, Yuanpeng Zhang, Jingmin Zhang, Yuchen Tang, Zhican Zhang, Gang Chen, Dawei Yang, Zhaoyang Zhang, Lizheng Ren, Tianzhu Xiong, Bo Wang, Bo Liu, Weiwei Shan, Xinning Liu, Hao Cai, Guangyu Sun, Jun Yang, Xin Si
2024 J jnl
A 0.61-μW Fully Integrated Keyword-Spotting ASIC With Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN.
IEEE J. Solid State Circuits
Cai Li, Haochang Zhi, Kaiyue Yang, Junyi Qian, Zhihao Yan, Lixuan Zhu, Chao Chen, Xi Wang, Weiwei Shan
2024 — conf
A 22nm Variation-Tolerant Clock Duty-Cycle Controller for Mitigating Aging-Induced Clock Duty-Cycle Distortion with Path Replica.
ICTA
Lishuo Deng, Zhiting Li, Changwei Yan, Junyi Qian, Cai Li, Ruidong Li, Tuo Li, Weiwei Shan
2024 — conf
A 28nm 128-kb Exponent- and Mantissa-Computation-InMemory Dual-macro for Floating-point and INT CNNs.
A-SSCC
An Guo, Xueshan Dong, Fangyuan Dong, Dongqi Li, Yiran Zhang, Jingmin Zhang, Yuchen Tang, Yuhui Shi, Xiao Tan, Bo Liu, Weiwei Shan, Hao Cai, Jun Yang, Xin Si
2024 — conf
An Adaptive Wide-Voltage-Range Droop Detection and Protection System Assisted with Timing Error Detection in 28nm CMOS.
CICC
Lishuo Deng, Zhengguo Shen, Zhuo Chen, Cai Li, Junyi Qian, Yuxuan Du, Kaize Zhou, Keran Li, Ruidong Li, Tuo Li, Xiaofeng Zou, Weiwei Shan
2024 — conf
An All-digital, 3.68 mV/LSB Voltage Sensor based Droop Prediction and Fast Mitigation System in 28nm CMOS.
A-SSCC
Yuxuan Du, Kaize Zhou, Zhuo Chen, Lishuo Deng, Tuo Li, Yan Lu, Weiwei Shan
2024 A conf
AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis.
ICCAD
Jintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi, Keren Zhu, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang, Yun Li, Xuan Zeng
2024 J jnl
AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis.
CoRR
Jintao Li, Haochang Zhi, Ruiyu Lyu, Wangzhen Li, Zhaori Bi, Keren Zhu, Yanhan Zeng, Weiwei Shan, Changhao Yan, Fan Yang, Yun Li, Xuan Zeng
2024 J jnl
DSC-TRCP: Dynamically Self-Calibrating Tunable Replica Critical Paths Based Timing Monitoring for Variation Resilient Circuits.
IEEE J. Solid State Circuits
Yuxuan Du, Junyi Qian, Zhengguo Shen, Chengjun Wu, Weiwei Shan, Xi Wang
2024 J jnl
FLC-EDC: A Fast Low-Cost Error Detection and Correction Scheme for AVFS System Based on Flip-Flops Resampling in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Yuqiang Cui, Lishuo Deng, Keran Li, Weiwei Shan
2024 J jnl
Knowledge Transfer Framework for PVT Robustness in Analog Integrated Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jintao Li, Yanhan Zeng, Haochang Zhi, Jingci Yang, Weiwei Shan, Yongfu Li, Yun Li
2024 A conf
MEIC: Re-thinking RTL Debug Automation using LLMs.
ICCAD
Ke Xu, Jialin Sun, Yuchen Hu, Xinwei Fang, Weiwei Shan, Xi Wang, Zhe Jiang
2024 J jnl
MEIC: Re-thinking RTL Debug Automation using LLMs.
CoRR
Ke Xu, Jialin Sun, Yuchen Hu, Xinwei Fang, Weiwei Shan, Xi Wang, Zhe Jiang
2024 — conf
Make Each Iteration Count.
ACM TUR-C
Yuchen Hu, Ke Xu, Jialin Sun, Xinwei Fang, Weiwei Shan, Xi Wang, Zhe Jiang
2024 J jnl
UVLLM: An Automated Universal RTL Verification Framework using LLMs.
CoRR
Yuchen Hu, Junhao Ye, Ke Xu, Jialin Sun, Shiyue Zhang, Xinyao Jiao, Dingrong Pan, Jie Zhou, Ning Wang, Weiwei Shan, Xinwei Fang, Xi Wang, Nan Guan, Zhe Jiang
2024 J jnl
Ultra-low-power one-hot transmission-gate multiplexer (OTG-MUX) scalable into large fan-in circuits in 28 nm CMOS.
Integr.
Yuqiang Cui, Weiwei Shan, Peng Cao
2023 J jnl
A 1.23μJ/Inference, All-Digital Shuffle-Type Group-CNN Accelerator in 28nm CMOS With 85.8% Accuracy on CIFAR-10.
IEEE Trans. Circuits Syst. II Express Briefs
Long Chen, Cai Li, Tao Wang, Junyi Qian, Weiwei Shan
2023 — conf
A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference.
ISSCC
Hao Cai, Zhongjian Bian, Yaoru Hou, Yongliang Zhou, Jia-Le Cui, Yanan Guo, Xiaoyun Tian, Bo Liu, Xin Si, Zhen Wang, Jun Yang, Weiwei Shan
2023 — conf
A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.
ISSCC
An Guo, Xin Si, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li, Yongliang Zhou, Lizheng Ren, Yeyang Xue, Xueshan Dong, Hui Gao, Yiran Zhang, Jingmin Zhang, Yuyao Kong, Tianzhu Xiong, Bo Wang, Hao Cai, Weiwei Shan, Jun Yang
2023 — conf
A 28nm All-Digital, 1.92-7.32mV/LSB, 0.5-2GS/s sample rate, 0-latency Voltage Sensor with Dynamic PVT Calibration for Wide-range Adaptive Voltage Scaling.
CICC
Yuxuan Du, Haitao Ge, Zhuo Chen, Kaize Zhou, Zhengguo Shen, Weiwei Shan
2023 — conf
A 608nW Near-Microphone Keyword-Spotting Chip Using Real-Point Serial FFT-Based MFCC and Temporal Depthwise Separable CNN in 28nm CMOS.
CICC
Cai Li, Haochang Zhi, Long Chen, Kaiyue Yang, Junyi Qian, Zhihao Yan, Lixuan Zhu, Weiwei Shan
2023 — conf
A Compact and Robust 28nm CMOS Temperature Sensor with Machine Learning Assisted Design for DVFS SoC.
ICTA
Yizhi Ding, Haochang Zhi, Jintao Li, Zhuo Chen, Kaiyue Yang, Weiwei Shan
2023 J jnl
AAD-KWS: A Sub-μ W Keyword Spotting Chip With an Acoustic Activity Detector Embedded in MFCC and a Tunable Detection Window in 28-nm CMOS.
IEEE J. Solid State Circuits
Weiwei Shan, Junyi Qian, Lixuan Zhu, Jun Yang, Cheng Huang, Hao Cai
2023 J jnl
An All-Digital, 1.92-7.32 mV/LSB, 0.5-2 GS/s Sample Rate, and 0-Latency Prediction Voltage Sensor With Dynamic PVT Calibration for Droop Detection and AVS System.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuxuan Du, Junyi Qian, Zhuo Chen, Weiwei Shan
2023 J jnl
An efficient path delay variability model for wide-voltage-range digital circuits.
Sci. China Inf. Sci.
Weiwei Shan, Yuqiang Cui, Wentao Dai, Xinning Liu, Jingjing Guo, Peng Cao, Jun Yang
2023 J jnl
Beyond Eliminating Timing Margin: An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator Without Accuracy Loss.
IEEE J. Solid State Circuits
Zhengguo Shen, Weiwei Shan, Yuxuan Du, Ziyu Li, Jun Yang
2023 J jnl
Design and analysis of leading one/zero detector based approximate multipliers.
Microelectron. J.
Yuxuan Du, Zhuo Chen, Boyang Cheng, Weiwei Shan
2023 J jnl
Design of high-efficiency complex multiplier for fault-tolerant computation.
Integr.
Zhuo Chen, Yuxuan Du, Boyang Cheng, Weiwei Shan
2023 C conf
IVATS: A Leakage Reduction Technique Based on Input Vector Analysis and Transistor Stacking in CMOS Circuits.
ISCAS
Lishuo Deng, Keran Li, Weiwei Shan
2023 A conf
Multi-Task Evolutionary to PVT Knowledge Transfer for Analog Integrated Circuit Optimization.
ICCAD
Jintao Li, Haochang Zhi, Weiwei Shan, Yongfu Li, Yanhan Zeng, Yun Li
2023 — conf
TEPD: A Compound Timing Detection of Both Data-Transition and Path-Activation for Reliable In-Situ Timing Error Detection and Correction in 28nm CMOS.
A-SSCC
Zhengguo Shen, Junyi Qian, Keran Li, Ziyu Li, Lishuo Deng, Weiwei Shan
2022 — conf
A 28nm, 4.69TOPS/W Training, 2.34µJ/lmage Inference, on-chip Training Accelerator with Inference-compatible Back Propagation.
ICTA
Haitao Ge, Weiwei Shan, Yicheng Lu, Jun Yang
2022 — conf
A High-Precision PVT-Tolerance Adaptive Clock Circuit Over Wide Frequencies in 28nm CMOS.
APCCAS
Yuqiang Cui, Weiwei Shan
2022 — conf
A Voltage Error Quantizer For Digital Low Dropout Regulators With Fast Transient Response and Low Steady-State Error.
ICTA
Kaize Zhou, Dejian Li, Chongfei Shen, Yuxuan Du, Zhuo Chen, Weiwei Shan
2022 — conf
An Energy-Efficient Cardiac Arrhythmia Classification Processor using Heartbeat Difference based Classification and Event-Driven Neural Network Computation with Adaptive Wake-Up.
CICC
Jiahao Liu, Jianbiao Xiao, Jiajing Fan, Qingsong Liu, Zixuan Zhu, Sixu Li, Zhaomin Zhang, Siqi Yang, Weiwei Shan, Shuisheng Lin, Liang Chang, Liang Zhou, Jun Zhou
2022 J jnl
An Ultra-Energy-Efficient and High Accuracy ECG Classification Processor With SNN Inference Assisted by On-Chip ANN Learning.
IEEE Trans. Biomed. Circuits Syst.
Ruixin Mao, Sixu Li, Zhaomin Zhang, Zihan Xia, Jianbiao Xiao, Zixuan Zhu, Jiahao Liu, Weiwei Shan, Liang Chang, Jun Zhou
2022 A* conf
An energy-efficient seizure detection processor using event-driven multi-stage CNN classification and segmented data processing with adaptive channel selection.
DAC
Jiahao Liu, Zirui Zhong, Yong Zhou, Hui Qiu, Jianbiao Xiao, Jiajing Fan, Zhaomin Zhang, Sixu Li, Yiming Xu, Siqi Yang, Weiwei Shan, Shuisheng Lin, Liang Chang, Jun Zhou
2021 J jnl
A 510-nW Wake-Up Keyword-Spotting Chip Using Serial-FFT-Based MFCC and Binarized Depthwise Separable CNN in 28-nm CMOS.
IEEE J. Solid State Circuits
Weiwei Shan, Minhao Yang, Tao Wang, Yicheng Lu, Hao Cai, Lixuan Zhu, Jiaming Xu, Chengjun Wu, Longxing Shi, Jun Yang
2021 J jnl
A Time-Domain Binary CNN Engine With Error-Detection-Based Resilience in 28nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Zhikuang Cai, Boyang Cheng, Yuxuan Du, Xinchao Shang, Weiwei Shan
2021 — conf
AAD-KWS: a sub-$\mu\mathrm{W}$ keyword spotting chip with a zero-cost, acoustic activity detector from a 170nW MFCC feature extractor in 28nm CMOS.
ESSDERC
Lixuan Zhu, Weiwei Shan, Jiaming Xu, Yicheng Lu
2021 — conf
AAD-KWS: a sub-µW keyword spotting chip with a zero-cost, acoustic activity detector from a 170nW MFCC feature extractor in 28nm CMOS.
ESSCIRC
Lixuan Zhu, Weiwei Shan, Jiaming Xu, Yicheng Lu
2021 — conf
An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator without Accuracy Loss in 28nm CMOS.
A-SSCC
Ziyu Li, Weiwei Shan, Chengjun Wu, Haitao Ge, Jun Yang
2021 — conf
Design of an ultra-low Power MFCC Feature Extraction Circuit with Embedded Speech Activity Detector.
ICTA
Kaiyue Yang, Lixuan Zhu, Weiwei Shan
2021 — conf
Energy-Efficient Design of Large Fan-in Dynamic One-hot Multiplexer in 28nm CMOS Technology.
ICTA
Yuqiang Cui, Chengjun Wu, Ziyu Li, Weiwei Shan
2021 J jnl
Nanowatt Acoustic Inference Sensing Exploiting Nonlinear Analog Feature Extraction.
IEEE J. Solid State Circuits
Minhao Yang, HongJie Liu, Weiwei Shan, Jun Zhang, Ilya Kiselev, Sang Joon Kim, Christian C. Enz, Mingoo Seok
2020 — conf
14.1 A 510nW 0.41V Low-Memory Low-Computation Keyword-Spotting Chip Using Serial FFT-Based MFCC and Binarized Depthwise Separable Convolutional Neural Network in 28nm CMOS.
ISSCC
Weiwei Shan, Minhao Yang, Jiaming Xu, Yicheng Lu, Shuai Zhang, Tao Wang, Jun Yang, Longxing Shi, Mingoo Seok
2020 J jnl
A Bi-Directional, Zero-Latency Adaptive Clocking Circuit in a 28-nm Wide AVFS System.
IEEE J. Solid State Circuits
Weiwei Shan, Wentao Dai, Liang Wan, Minyi Lu, Longxing Shi, Mingoo Seok, Jun Yang
2020 J jnl
A Wide-Voltage-Range Transition-Detector With In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in 28 nm CMOS.
IEEE Trans. Circuits Syst.
Xinchao Shang, Minyi Lu, Chengjun Wu, Yiming Xiang, Jiaming Xu, Weiwei Shan
2020 — conf
An Energy-Efficient Time-Domain Binary Neural Network Accelerator with Error-Detection in 28nm CMOS.
APCCAS
Yuxuan Du, Xinchao Shang, Weiwei Shan
2020 — conf
Design of Approximate Complex Constant Multiplier for Fast Fourier Transform in 28nm CMOS.
ICTA
Lixuan Zhu, Lixing Li, Weiwei Shan
2020 J jnl
Machine Learning Assisted Side-Channel-Attack Countermeasure and Its Application on a 28-nm AES Circuit.
IEEE J. Solid State Circuits
Weiwei Shan, Shuai Zhang, Jiaming Xu, Minyi Lu, Longxing Shi, Jun Yang
2020 J jnl
TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS.
IEEE J. Solid State Circuits
Weiwei Shan, Wentao Dai, Chuan Zhang, Hao Cai, Peiye Liu, Jun Yang, Longxing Shi
2020 — conf
Using Wind Turbines for Providing Defined Levels of Synthetic Inertia in System Split Scenarios.
ISGT-Europe
Martin Shan, Daniel Duckwitz, Weiwei Shan
2019 — conf
A 923 Gbps/W, 113-Cycle, 2-Sbox Energy-efficient AES Accelerator in 28nm CMOS.
VLSI Circuits
Weiwei Shan, Ao Fan, Jiaming Xu, Jun Yang, Mingoo Seok
2019 — conf
A Depthwise Separable Convolution Neural Network for Small-footprint Keyword Spotting Using Approximate MAC Unit and Streaming Convolution Reuse.
APCCAS
Yicheng Lu, Weiwei Shan, Jiaming Xu
2019 J jnl
A Wide-Voltage-Range Half-Path Timing Error-Detection System With a 9-Transistor Transition-Detector in 40-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Weiwei Shan, Xinchao Shang, Xing Wan, Hao Cai, Chuan Zhang, Jun Yang
2019 J jnl
Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hao Cai, You Wang, Lirida Alves de Barros Naviner, Xinning Liu, Weiwei Shan, Jun Yang, Weisheng Zhao
2019 — conf
An Energy-Efficient In-Memory BNN Architecture With Time-Domain Analog and Digital Mixed-Signal Processing.
NANOARCH
Tao Wang, Weiwei Shan
2019 — conf
Successive Stripe Artifact Removal Based on Robust PCA for Millimeter Wave Automotive Radar Image.
APSIPA
Weiwei Shan, Shogo Muramatsu, Akira Oshima, Hiroyoshi Yamada
2019 — conf
Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI.
ACM Great Lakes Symposium on VLSI
Hao Cai, Menglin Han, Weiwei Shan, Jun Yang, You Wang, Wang Kang, Weisheng Zhao
2019 — conf
ynamic Adaptation of Approximate Bit-width for CNNs based on Quantitative Error Resilience.
NANOARCH
Chengjun Wu, Weiwei Shan, Jiaming Xu
2018 — conf
A 0.46V-1.1V Transition-Detector with In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in AES Accelerator.
A-SSCC
Xinchao Shang, Weiwei Shan, Jiaming Xu, Minyi Lu, Yiming Xiang, Longxing Shi, Jun Yang
2018 — conf
A Compact, Lightweight and Low-Cost 8-Bit Datapath AES Circuit for IoT Applications in 28nm CMOS.
TrustCom/BigDataSE
Minyi Lu, Ao Fan, Jiaming Xu, Weiwei Shan
2018 J jnl
A Low Overhead, Within-a-Cycle Adaptive Clock Stretching Circuit With Wide Operating Range in 40-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Weiwei Shan, Liang Wan, Xinning Liu, Xinchao Shang, Wentao Dai, Shuai Shao, Jun Yang, Longxing Shi
2018 J jnl
A Low-Overhead Timing Monitoring Technique for Variation-Tolerant Near-Threshold Digital Integrated Circuits.
IEEE Access
Weiwei Shan, Xinning Liu, Minyi Lu, Liang Wan, Jun Yang
2018 — conf
Correlation-Based Electromagnetic Analysis Attack Using Haar Wavelet Reconstruction with Low-Pass Filtering on an FPGA Implementaion of AES.
TrustCom/BigDataSE
Aiguo Bu, Wentao Dai, Minyi Lu, Hao Cai, Weiwei Shan
2018 J jnl
Design and Implementation of a Reconfigurable Cryptographic Coprocessor with Multiple Side-Channel Attacks Countermeasures.
J. Circuits Syst. Comput.
Xinchao Shang, Weiwei Shan, Xinning Liu
2018 — conf
Differential Power Analysis of 8-Bit Datapath AES for IoT Applications.
TrustCom/BigDataSE
Jiaming Xu, Ao Fan, Minyi Lu, Weiwei Shan
2018 C conf
Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques.
ISCAS
Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner, Weiwei Shan, Jun Yang, Weisheng Zhao
2018 J jnl
HTD: A Light-Weight Holosymmetrical Transition Detector for Wide-Voltage-Range Variation Resilient ICs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wentao Dai, Weiwei Shan, Xinchao Shang, Xinning Liu, Hao Cai, Jun Yang
2018 — conf
Short-path Padding Method for Timing Error Resilient Circuits based on Transmission Gates Insertion.
ACM Great Lakes Symposium on VLSI
Wentao Dai, Peiye Liu, Weiwei Shan
2018 J jnl
Timing Error Prediction AVFS With Detection Window Tuning for Wide-Operating-Range ICs.
IEEE Trans. Circuits Syst. II Express Briefs
Weiwei Shan, Xinchao Shang, Longxing Shi, Wentao Dai, Jun Yang
2017 — conf
A 0.44V-1.1V 9-transistor transition-detector and half-path error detection technique for low power applications.
A-SSCC
Xinchao Shang, Weiwei Shan, Longxing Shi, Xing Wan, Jun Yang
2017 J jnl
An improved timing error prediction monitor for wide adaptive frequency scaling.
IEICE Electron. Express
Weiwei Shan, Xinning Liu, Minyi Lu, Shuai Shao, Zhikuang Cai, Jun Yang
2017 — conf
HTD: A light-weight holosymmetrical transition detector based in-situ timing monitoring technique for wide-voltage-range in 40nm CMOS.
A-SSCC
Wentao Dai, Weiwei Shan, Xinning Liu, Jun Yang
2017 J jnl
In-Situ Timing Monitor-Based Adaptive Voltage Scaling System for Wide-Voltage-Range Applications.
IEEE Access
Weiwei Shan, Longxing Shi, Jun Yang
2016 J jnl
Timing monitoring paths selection for wide voltage IC.
IEICE Electron. Express
Weiwei Shan, Wentao Dai, Youhua Shi, Peng Cao, Xiaoyan Xiang
2015 J jnl
A Secure Reconfigurable Crypto IC With Countermeasures Against SPA, DPA, and EMA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Weiwei Shan, Xingyuan Fu, Zhipeng Xu
2014 A* conf
A Side-channel Analysis Resistant Reconfigurable Cryptographic Coprocessor Supporting Multiple Block Cipher Algorithms.
DAC
Weiwei Shan, Longxing Shi, Xingyuan Fu, Xiao Zhang, Chaoxuan Tian, Zhipeng Xu, Jun Yang, Jie Li
2014 — conf
Timing error prediction based adaptive voltage scaling for dynamic variation tolerance.
APCCAS
Weiwei Shan, Zhipeng Xu
2014 J jnl
VLSI design of a reconfigurable S-box based on memory sharing method.
IEICE Electron. Express
Weiwei Shan, Xiao Zhang, Xingyuan Fu, Peng Cao
2013 J jnl
An improved timing monitor for deep dynamic voltage scaling system.
IEICE Electron. Express
Weiwei Shan, Haolin Gu, Bo Li, Xiaoqing Wu, Haikun Jin, Yintao Guo, Peng Cao
2013 J jnl
BIST design of power switch.
IEICE Electron. Express
Xin Chen, Ning Wu, Wei Hu, Weiwei Shan
2013 J jnl
Evaluation of Correlation Power Analysis Resistance and Its Application on Asymmetric Mask Protected Data Encryption Standard Hardware.
IEEE Trans. Instrum. Meas.
Weiwei Shan, Xin Chen, Bo Li, Peng Cao, Jie Li, Gugang Gao, Longxing Shi
2013 J jnl
Implementation of correlation power analysis attack on an FPGA DES design.
Int. J. Inf. Commun. Technol.
Jun Yang, Weiwei Shan, Junyin Liu, Huafang Sun
2013 J jnl
On-chip long-term jitter measurement for PLL based on undersampling technique.
IEICE Electron. Express
Zhikuang Cai, Haobo Xu, Shixuan Que, Weiwei Shan, Jun Yang
2012 — conf
A New Approach to Implement Discrete Wavelet Transform on Coarse-Grained Reconfigurable Architecture.
CyberC
Jie Li, Xinxiang Ke, Peng Cao, Weiwei Shan
2012 — conf
A Power Analysis Resistant DES Cryptographic Algorithm and Its Hardware Design.
ICDMA
Jie Li, Yuxiang Lv, Huafang Sun, Weiwei Shan
2012 — conf
Configuration Cache Management for Coarse-Grained Reconfigurable Architecture with Multi-Array.
CyberC
Peng Cao, Yong Cai, Bo Liu, Weiwei Shan
2012 — conf
Memory Bandwidth Optimization Strategy of Coarse-Grained Reconfigurable Architecture.
CyberC
Peng Cao, Huiyan Jiang, Bo Liu, Weiwei Shan
2012 — conf
Uniform SystemC Co-Simulation Methodology for System-on-Chip Designs.
CyberC
Xuexiang Wang, Weiwei Shan, Hao Liu
2011 J jnl
A Novel Combined Proportional-Derivative Control for Electrostatic MEMS Mirror Actuation.
IEICE Trans. Electron.
Weiwei Shan, Xin Chen
2009 C conf
Adaptive Fuzzy Logic Controller and Its Application in MEMS Mirror Actuation Feedback Control.
IDEAL
Weiwei Shan, Xiqun Zhu, Yuan Ma
2009 J jnl
Cmos Circuit Design of a Takagi-Sugeno Fuzzy Logic Controller.
J. Circuits Syst. Comput.
Weiwei Shan, Yan Liang, Dongming Jin
2008 J jnl
Analog Circuit Implementation of a Variable Universe Adaptive Fuzzy Logic Controller.
IEEE Trans. Circuits Syst. II Express Briefs
Weiwei Shan, Yuan Ma, Robert W. Newcomb, Dongming Jin
2005 — conf
VLSI Implementation of a Self-tuning Fuzzy Controller Based on Variable Universe of Discourse.
FSKD (1)
Weiwei Shan, Dongming Jin, Weiwei Jin, Zhihao Xu