Weitao Pan

45 papers A* 1C 1Journal 28Unranked 15
YearRankTypeTitle / Venue / Authors
2026 J jnl
A Grouped Sorting Queue Supporting Dynamic Updates for Timer Management in High-Speed Network Interface Cards.
CoRR
Zekun Wang, Binghao Yue, Weitao Pan, Jianyi Shi, Yue Hao
2026 J jnl
CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-Based CIM Architectures.
IEEE Trans. Computers
Yingjie Qi, Jianlei Yang, Rubing Yang, Cenlin Duan, Xiaolin He, Ziyan He, Weitao Pan, Weisheng Zhao
2026 J jnl
Enhancing deterministic transmission in Time-Sensitive Networking: A Joint Guard Band Compression and Non-Disruptive Frame Preemption model.
J. Syst. Archit.
Ling Zheng, Jingzhuo Liu, Keyao Zhang, Qianxi Men, Li Zhen, Weitao Pan
2025 J jnl
CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-based CIM Architectures.
CoRR
Yingjie Qi, Jianlei Yang, Rubing Yang, Cenlin Duan, Xiaolin He, Ziyan He, Weitao Pan, Weisheng Zhao
2025 J jnl
Corrections to "GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features".
IEEE Trans. Very Large Scale Integr. Syst.
Peijun Ma, Ge Shang, Hongjin Liu, Jiangyi Shi, Weitao Pan, Yan Zhang, Yue Hao
2025 — conf
Deadline Guaranteed Scheduling Based on Time-Ordered Queues for Time-Sensitive Low-Earth-Orbit Satellite Networks.
VTC2025-Fall
Ling Zheng, Guodong Wei, Qianxi Men, Yingge Feng, Weitao Pan
2025 J jnl
Design of a Timer Queue Supporting Dynamic Update Operations.
CoRR
Zekun Wang, Binghao Yue, Weitao Pan, Jiangyi Shi, Yue Hao
2025 J jnl
GNN-Based Hardware Trojan Detection at Register Transfer Level Leveraging Multiple-Category Features.
IEEE Trans. Very Large Scale Integr. Syst.
Peijun Ma, Ge Shang, Hongjin Liu, Jiangyi Shi, Weitao Pan, Yan Zhang, Yue Hao
2025 J jnl
Group-based windows scheduling method for non-deterministic periodic flows in time-sensitive networks.
Comput. Networks
Zhe Zhao, Yongjun Li, Xiang Wang, Qin Tian, Ke Wang, Kai Zhang, Weitao Pan
2025 J jnl
Hardware Trojan Detection Methods for Gate-Level Netlists Based on Graph Neural Networks.
IEEE Trans. Computers
Peijun Ma, Jie Li, Hongjin Liu, Jiangyi Shi, Shaolin Zhang, Weitao Pan, Yue Hao
2025 — conf
Queuing Model with Setup and Multi-Vacations for Mixed-Critical Services in Time-Sensitive SAGIN.
VTC2025-Fall
Ling Zheng, Yingge Feng, Weiqiang Wang, Weitao Pan
2025 J jnl
RELIC-GNN: Efficient State Registers Identification with Graph Neural Network for Reverse Engineering.
CoRR
Weitao Pan, Meng Dong, Zhiliang Qiu, Jianlei Yang, Zhixiong Di, Yiming Gao
2024 J jnl
An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method.
IEEE Trans. Neural Networks Learn. Syst.
Xiaotao Jia, Huiyi Gu, Yuhao Liu, Jianlei Yang, Xueyan Wang, Weitao Pan, Youguang Zhang, Sorin Cotofana, Weisheng Zhao
2024 J jnl
DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao
2024 J jnl
Design and implementation of a frame preemption model without guard bands for time-sensitive networking.
Comput. Networks
Zhe Zhao, Zhiliang Qiu, Weitao Pan, Hui Li, Ling Zheng, Ya Gao
2023 C conf
A Machine Learning Based Approach to Detect Machine Learning Design Patterns.
APSEC
Weitao Pan, Hironori Washizaki, Nobukazu Yoshioka, Yoshiaki Fukazawa, Foutse Khomh, Yann-Gaël Guéhéneuc
2023 J jnl
A unioned graph neural network based hardware Trojan node detection.
IEICE Electron. Express
Weitao Pan, Meng Dong, Cong Wen, Hongjin Liu, Shaolin Zhang, Bo Shi, Zhixiong Di, Zhiliang Qiu, Yiming Gao, Ling Zheng
2023 J jnl
Access mechanism for period flows of non-deterministic end systems for time-sensitive networks.
Comput. Networks
Zhe Zhao, Lu Gao, Weitao Pan, Zhiliang Qiu, Xu Guo, Ya Gao, Ling Zheng
2023 J jnl
DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-based Processing-In-Memory.
CoRR
Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao
2022 J jnl
A Universal, Low-Delay, SEC-DEC-TAEC Code for State Register Protection.
IEEE Access
Meng Dong, Weitao Pan, Zhiliang Qiu, Xiaoxin Qi, Ling Zheng, Huan Liu
2022 J jnl
Evaluation Method for Feature Selection in Proton Exchange Membrane Fuel Cell Fault Diagnosis.
IEEE Trans. Ind. Electron.
Lei Mao, Zhongyong Liu, Derek Low, Weitao Pan, Qingbo He, Lisa M. Jackson, Qiang Wu
2022 J jnl
Eventor: An Efficient Event-Based Monocular Multi-View Stereo Accelerator on FPGA Platform.
CoRR
Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao
2022 A* conf
Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform.
DAC
Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao
2021 J jnl
Architecture design and performance analysis of a novel memory system for high-bandwidth onboard switching fabric.
Comput. Networks
Ling Zheng, Weitao Pan, Ya Gao, Huan Liu, Jing Jiang
2021 — conf
Combined Shared-Memory and Buffered-Crossbar Architecture for High-Bandwidth Onboard Switching Fabric.
APNet
Ling Zheng, Chen Yi, Weitao Pan, Huan Liu
2021 — conf
Design and Implementation of AS6802 Clock Synchronization System in TTE thernet.
ICCCS
Jinlong Dong, Zhiliang Qiu, Weitao Pan, Min Wu, Jialiang Cao
2021 — conf
Design of HIMAC Coprocessor for HINOC3.0.
ICCCS
Jinjian Huang, Zhiliang Qiu, Weitao Pan, Jun Li, Zhikai Gao, Bing Han, Zihao Xiong, Meng Dong
2021 — conf
GGTS: FPGA-Based General Ground Test System for Space-Borne Equipment.
ICCCS
Jialu Mang, Zhiliang Qiu, Weitao Pan, Meng Dong, Min Wu
2021 J jnl
Hardware Trojan Designs Based on High-Low Probability and Partitioned Combinational Logic With a Malicious Reset Signal.
IEEE Trans. Circuits Syst. II Express Briefs
Jiangyi Shi, Xinyuan Zhang, Peijun Ma, Weitao Pan, Pengfei Li, Zhengguang Tang
2021 — conf
HyperParser: A High-Performance Parser Architecture for Next Generation Programmable Switch and SmartNIC.
APNet
Huan Liu, Zhiliang Qiu, Weitao Pan, Jiajun Li, Jinjian Huang
2021 J jnl
Low-Cost and Programmable CRC Implementation Based on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs
Huan Liu, Zhiliang Qiu, Weitao Pan, Jun Li, Ling Zheng, Ya Gao
2020 — conf
Dual-Plane Switch Architecture for Time-Triggered Ethernet.
ACM Great Lakes Symposium on VLSI
Meng Dong, Zhiliang Qiu, Weitao Pan, Hongbin Zhang, Chenglei Kong, Hui Jin, Jianlei Yang
2020 — conf
High-Performance and Range-Supported Packet Classification Algorithm for Network Security Systems in SDN.
ICC Workshops
Ling Zheng, Jing Jiang, Weitao Pan, Huan Liu
2020 J jnl
Performance analysis and hardware implementation of a nearly optimal buffer management scheme for high-performance shared-memory switches.
Int. J. Commun. Syst.
Ling Zheng, Weitao Pan, Yinghua Li, Ya Gao
2019 J jnl
AFBV: A High-Performance Network Flow Classification Method for Multi-Dimensional Fields and FPGA Implementation.
J. Circuits Syst. Comput.
Ling Zheng, Zhiliang Qiu, Weina Wang, Weitao Pan, Shiyong Sun, Ya Gao
2018 — conf
A High-Speed Large-Capacity Packet Buffer Scheme for High-Bandwidth Switches and Routers.
ChinaCom
Ling Zheng, Zhiliang Qiu, Weitao Pan, Ya Gao
2018 J jnl
Analysis and Implementation of a QoS Optimization Method for Access Networks.
IEICE Trans. Commun.
Ling Zheng, Zhiliang Qiu, Weitao Pan, Yibo Mei, Shiyong Sun, Zhiyi Zhang
2018 — conf
Analysis of a Shared-Private Buffer Management Scheme for Shared Memory Switches.
CITS
Ling Zheng, Zhiliang Qiu, Weitao Pan, Ya Gao, Junxiang Zhang, Dong Zhang
2018 J jnl
Design and analysis of a parallel hybrid memory architecture for per-flow buffering in high-speed switches and routers.
J. Commun. Networks
Ling Zheng, Zhiliang Qiu, Shiyong Sun, Weitao Pan, Ya Gao, Zhiyi Zhang
2018 — conf
Research on Model of Five-level Scheduling Based on SDN.
CITS
Weitao Pan, Lili Gao, Ling Zheng, Zhiliang Qiu, Junxiang Zhang, Dong Zhang, Ya Gao
2018 — conf
The Design and Implementation of IEEE 1588v2 Clock Synchronization System by Generating Hardware Timestamps in MAC Layer.
CITS
Meng Dong, Zhiliang Qiu, Weitao Pan, Can Chen, Junxiang Zhang, Dong Zhang
2018 — conf
The High Speed Packet Classification Supporting Multi - Field for Flow Tables in OpenFlow.
CITS
Zhiliang Qiu, Weina Wang, Shiyong Sun, Weitao Pan, Ling Zheng, Ya Gao, Zhiyi Zhang
2017 — conf
Analyzing the Impact of Redundant Paths on Multistage Switch Performance.
ChinaCom (1)
Ya Gao, Weitao Pan, Ling Zheng
2017 J jnl
Improved analytical model for performance evaluation of crosspoint-queued switch under uniform traffic.
IET Networks
Ya Gao, Weitao Pan, Ling Zheng
2016 J jnl
Dual priority congestion aware shared-resource Network-on-Chip architecture.
IEICE Electron. Express
Hao Shu, Jiangyi Shi, Peijun Ma, Huaxi Gu, Weitao Pan, Lin-An Yang