Weisheng Zhao

315 papers A* 20A 18B 2C 32Misc 1Journal 150Unranked 89
YearRankTypeTitle / Venue / Authors
2026 J jnl
ACE-GNN: Adaptive GNN Co-Inference With System-Aware Scheduling in Dynamic Edge Environments.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Xinming Wei, Cenlin Duan, Weisheng Zhao, Chunming Hu
2026 J jnl
An FD-SOI-Based Compact In-Pixel Computing Architecture Enabling Real-Time Feature Extraction.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yijiao Wang, Jiayao Wu, Yaqi Wang, Zhongzhen Tong, Xinrui Duan, Yiming Shi, Wen Shi, Weisheng Zhao
2026 J jnl
CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-Based CIM Architectures.
IEEE Trans. Computers
Yingjie Qi, Jianlei Yang, Rubing Yang, Cenlin Duan, Xiaolin He, Ziyan He, Weitao Pan, Weisheng Zhao
2026 J jnl
Efficient SRAM-PIM Co-Design by Joint Exploration of Value-Level and Bit-Level Sparsity.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Cenlin Duan, Jianlei Yang, Yikun Wang, Yiou Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2026 J jnl
GCoDE: Efficient Device-Edge Co-Inference for GNNs via Architecture-Mapping Co-Search.
IEEE Trans. Computers
Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Zhi Yang, Weisheng Zhao, Chunming Hu
2026 J jnl
High-performance true random number generator based on SOT-MTJ spin relaxation.
Sci. China Inf. Sci.
Jialiang Yin, Xiuye Zhang, Boyan Zhang, Bolin Zhang, Wenlong Cai, Ao Du, Binchao Tang, Haowei Zhang, Shijian Bao, Chunyi Li, Daoqian Zhu, Kewen Shi, Hongxi Liu, Lang Zeng, He Zhang, Kaihua Cao, Weisheng Zhao
2026 J jnl
NFGen: Normalizing Flow-Based Joint Generative Model for Variability-Aware Design Technology Co-Optimization.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tao Zou, Zhenxing Dou, Zhiwei Chen, Yijiao Wang, Wen Shi, Zhiyu Wang, Peng Wang, Runsheng Wang, Weisheng Zhao, Asen Asenov
2026 J jnl
ReNN-RV: Run-Time PE Reconfiguration for DNN Inference Acceleration With Custom RISC-V ISA.
IEEE Trans. Computers
Yueting Li, Terry Tao Ye, Ngai Wong, Zhenhua Zhu, Yongfu Li, Weisheng Zhao
2025 J jnl
A 0.88 e‾
IEEE Trans. Circuits Syst. I Regul. Pap.
Jianxin Wu, Wenjie Li, Wang Kang, Jing Kou, Liang Zhang, Liangchen Li, He Zhang, Weisheng Zhao
2025 J jnl
A 32 kb 55 nm Radiation-Hardened SRAM Chip With SEU ≤1.1 E-11 Upsets/Bit-Day, SEL >107.1 MeV ⋅ cm²/mg, and TID >100 Krad(Si) for Space Applications.
IEEE Trans. Circuits Syst. I Regul. Pap.
Deming Zhang, Jiaxin Yang, Dingyi Luo, Jianpeng Zhang, Lang Zeng, Bi Wang, Yue Zhang, Weisheng Zhao
2025 — conf
A Custom RISC-V ISA with Scalable Processing Units for Efficient Neural Network Inference.
CF
Yueting Li, Wanshuang Lin, Wendong Xu, Ngai Wong, Weisheng Zhao
2025 J jnl
A Heterogeneous System With Computing in Memory Processing Elements to Accelerate CNN Inference.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jinkai Wang, Youxiang Chen, Zekun Wang, Zhengkun Gu, Bojun Zhang, Haiming Qiu, Kun Zhang, Weisheng Zhao, Yue Zhang
2025 J jnl
A High-Speed, Low-Power, High-Reliability and Fully Single Event Double Node Upset Tolerant Design for Magnetic Random Access Memory.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jiaxin Yang, Ziyang Guo, Shixuan Wang, Jilong Liu, Yue Zhang, Weisheng Zhao, Lang Zeng, Deming Zhang
2025 J jnl
A Self-Decryption Pass Transistor Logic-Based In-MRAM Computing Macro Using Hybrid VGSOT-MTJ/GAA-CNTFET.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhongzhen Tong, Sifan Sun, Kaili Zhang, Chenghang Li, Jiye Yao, Yulong Qiu, Chao Wang, Zhaohao Wang, Ke Zhang, Amara Amara, Xiaoyang Lin, Weisheng Zhao
2025 J jnl
A Time and Energy-Efficient Asynchronous Hybrid-Searching Auto Frequency Calibration for a 3.2 GHz Phase-Locked Loop.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zijie Wang, Fanxun Cai, Lianbo Wu, Hui Zhang, Weisheng Zhao
2025 J jnl
ACE-GNN: Adaptive GNN Co-Inference with System-Aware Scheduling in Dynamic Edge Environments.
CoRR
Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Xinming Wei, Cenlin Duan, Weisheng Zhao, Chunming Hu
2025 J jnl
AM-CIM: Approximate Memory Based Near Sensor Compute-in-Memory Architecture for Keyword Spotting.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuhao Liu, Xiaotao Jia, Guangcai Yuan, Jianyi Yu, Cong Shi, Qi Wei, Youguang Zhang, Weisheng Zhao, Fei Qiao
2025 A conf
An Adaptive Sparse Matrix Compression CIM Accelerator based on 256Kb SOT-MRAM for Downlink Massive MIMO Communications.
ICCAD
Liangchen Li, Jianxin Wu, Changyu Li, Liang Zhang, Anyang Yu, Junda Zhao, Zhaohao Wang, Chengyuan Sun, Kaihua Cao, Hongxi Liu, Wang Kang, He Zhang, Weisheng Zhao
2025 A* conf
CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures.
DAC
Yingjie Qi, Jianlei Yang, Yiou Wang, Yikun Wang, Dayu Wang, Ling Tang, Cenlin Duan, Xiaolin He, Weisheng Zhao
2025 J jnl
CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures.
CoRR
Yingjie Qi, Jianlei Yang, Yiou Wang, Yikun Wang, Dayu Wang, Ling Tang, Cenlin Duan, Xiaolin He, Weisheng Zhao
2025 J jnl
CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-based CIM Architectures.
CoRR
Yingjie Qi, Jianlei Yang, Rubing Yang, Cenlin Duan, Xiaolin He, Ziyan He, Weitao Pan, Weisheng Zhao
2025 J jnl
Efficient SRAM-PIM Co-design by Joint Exploration of Value-Level and Bit-Level Sparsity.
CoRR
Cenlin Duan, Jianlei Yang, Yikun Wang, Yiou Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2025 A* conf
Finesse: An Agile Design Framework for Pairing-based Cryptography via Software/Hardware Co-Design.
ISCA
Tianwei Pan, Tianao Dai, Jianlei Yang, Hongbin Jing, Yang Su, Zeyu Hao, Xiaotao Jia, Chunming Hu, Weisheng Zhao
2025 J jnl
Finesse: An Agile Design Framework for Pairing-based Cryptography via Software/Hardware Co-Design.
CoRR
Tianwei Pan, Tianao Dai, Jianlei Yang, Hongbin Jing, Yang Su, Zeyu Hao, Xiaotao Jia, Chunming Hu, Weisheng Zhao
2025 J jnl
GCoDE: Efficient Device-Edge Co-Inference for GNNs via Architecture-Mapping Co-Search.
CoRR
Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Zhi Yang, Weisheng Zhao, Chunming Hu
2025 J jnl
HPIM: Heterogeneous Processing-In-Memory-based Accelerator for Large Language Models Inference.
CoRR
Cenlin Duan, Jianlei Yang, Rubing Yang, Yikun Wang, Yiou Wang, Lingkun Long, Yingjie Qi, Xiaolin He, Ao Zhou, Xueyan Wang, Weisheng Zhao
2025 A conf
HRAMTran: A Hybrid-RAM Transformer Accelerator With Dynamic Sparsity Floating-Point CIM and Written-Back Transpose Array.
ICCAD
Bojun Zhang, Jinkai Wang, Xianan Zhu, Ziyuan Guo, Zhengkun Gu, Kaili Zhang, Zhizhong Zhang, Kun Zhang, Weisheng Zhao, Yue Zhang
2025 J jnl
HiT-CIM: A High-Throughput Compute-in-Memory SRAM Architecture With Simultaneous Weight Loading/Computing and Balance Capabilities.
IEEE Trans. Emerg. Top. Comput.
Junzhan Liu, Sifan Sun, Liang Zhang, Lichuan Luo, Liang Ran, He Zhang, Wang Kang, Weisheng Zhao
2025 J jnl
In-MRAM Computing Based on Complementary-Sensing Time-Based Readout Circuit Using Hybrid VGSOT-MTJ/GAA-CNTFET.
IEEE Trans. Circuits Syst. II Express Briefs
Zhongzhen Tong, Sifan Sun, Kaili Zhang, Chenghang Li, Daming Zhou, Zhaohao Wang, Xiaoyang Lin, Weisheng Zhao
2025 A* conf
MIRACLE: Multimodal Information Retrieval via a Combined In-Memory Processing and Content Addressable Memory Approach.
DAC
Xuehui Liu, Xueyan Wang, Tianyang Yu, Chen Cheng, Shuo Ran, Bi Wu, Xiaotao Jia, Weiqiang Liu, Gang Qu, Weisheng Zhao
2025 J jnl
MS-SCIM: A Mixed-Signal Stochastic Computing-in-Memory Paradigm for Information Security.
IEEE Trans. Circuits Syst. I Regul. Pap.
Pengxu Wang, Yijiao Wang, Jialiang Yin, Jiayao Wu, Xinrui Duan, Yaqi Wang, Zhaohao Wang, Weisheng Zhao
2025 J jnl
Model quantization for computing-in-memory: a survey.
Sci. China Inf. Sci.
Sifan Sun, Jinyu Bai, Hanting Chen, Kaiwen Deng, Zhiwei Xie, Jingjing Li, Bin Cao, He Zhang, Wang Kang, Weisheng Zhao
2025 J jnl
Orbitronics for energy-efficient magnetization switching.
Sci. China Inf. Sci.
Yuxuan Yao, Daoqian Zhu, Qingtao Xia, Jianing Liang, Yuhao Jiang, Zhiyang Peng, Jiaxu Li, Chen Xiao, Renyou Xu, Wenwen Wang, Xiantao Shang, Shiyang Lu, Dapeng Zhu, Hongxi Liu, Kaihua Cao, Weisheng Zhao
2025 J jnl
Technically Feasible Robust Complementary SOT-MRAM Design for Improving the Area and Energy Efficiency.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chao Wang, Zhongkui Zhang, Xiaoyang Xu, Xianzeng Guo, Qihang Gao, Zhaohao Wang, Weisheng Zhao
2025 J jnl
Temperature-Resilient Reconfigurable PUF with Dual-Pulse Modulation based on SOT-MRAM Chip.
CoRR
Min Wang, Chuanpeng Jiang, Zhaohao Wang, Zhengyi Hou, Zhongkui Zhang, Yuanfu Zhao, Hongxi Liu, Weisheng Zhao
2025 — conf
Thermal-Compensated MRAM Sensing: Dynamic TMR Stabilization Across Wide Temperature Range.
MOCAST
Tuo Zhang, Xinpeng Jiang, Chao Wang, Bi Wang, Hongxi Liu, Kaihua Cao, Xuan Li, Hui Jin, Geifei Wang, Zhaohao Wang, He Zhang, Weisheng Zhao
2025 A conf
Ultra Energy-Efficient Butterfly Counting in Bipartite Networks via Algorithm-Architecture Co-Optimization.
ICCAD
Haiyang Liu, Xueyan Wang, Jianlei Yang, Xiaotao Jia, Gang Qu, Weisheng Zhao
2024 J jnl
A Charge-Domain Compute-In-Memory Macro With Cell-Embedded DA Conversion and Two-Stage AD Conversion for Bit-Scalable MAC Operation.
IEEE Trans. Circuits Syst. II Express Briefs
Kaili Zhang, Zhongzhen Tong, XinXin Liang, Chengzhi Wang, You Wang, Yue Zhang, Weisheng Zhao, Lang Zeng, Deming Zhang
2024 A* conf
A Combined Content Addressable Memory and In-Memory Processing Approach for k-Clique Counting Acceleration.
DAC
Xidi Ma, Weichen Zhang, Xueyan Wang, Tianyang Yu, Bi Wu, Gang Qu, Weisheng Zhao
2024 — conf
A Novel Radiation-Hardened Non-volatile Magnetic Latch Circuit.
NVMTS
Jiaxin Yang, Jilong Liu, Lang Zeng, Yue Zhang, Weisheng Zhao, Deming Zhang
2024 J jnl
APIM: An Antiferromagnetic MRAM-Based Processing-In-Memory System for Efficient Bit-Level Operations of Quantized Convolutional Neural Networks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yueting Li, Jinkai Wang, Daoqian Zhu, Jinhao Li, Ao Du, Xueyan Wang, Yue Zhang, Weisheng Zhao
2024 J jnl
An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method.
IEEE Trans. Neural Networks Learn. Syst.
Xiaotao Jia, Huiyi Gu, Yuhao Liu, Jianlei Yang, Xueyan Wang, Weitao Pan, Youguang Zhang, Sorin Cotofana, Weisheng Zhao
2024 J jnl
Area and Energy Efficient Short-Circuit-Logic-Based STT-MRAM Crossbar Array for Binary Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs
Chao Wang, Zhaohao Wang, Zhongkui Zhang, Youguang Zhang, Weisheng Zhao
2024 J jnl
BSTCIM: A Balanced Symmetry Ternary Fully Digital In-MRAM Computing Macro for Energy Efficiency Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhongzhen Tong, Chenghang Li, Chao Wang, Suteng Zhao, Qianyong Peng, Zhenyu Yan, Siqi Zhang, Daming Zhou, Zhaohao Wang, Xiaoyang Lin, Weisheng Zhao
2024 J jnl
CIMQ: A Hardware-Efficient Quantization Framework for Computing-In-Memory-Based Neural Network Accelerators.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jinyu Bai, Sifan Sun, Weisheng Zhao, Wang Kang
2024 J jnl
CIM²PQ: An Arraywise and Hardware-Friendly Mixed Precision Quantization Method for Analog Computing-In-Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sifan Sun, Jinyu Bai, Zhaoyu Shi, Weisheng Zhao, Wang Kang
2024 — conf
CRISP: Triangle Counting Acceleration via Content Addressable Memory-Integrated 3D-Stacked Memory.
ITC-Asia
Shangtong Zhang, Xueyan Wang, Weisheng Zhao, Yier Jin
2024 J jnl
CiM-BNN:Computing-in-MRAM Architecture for Stochastic Computing Based Bayesian Neural Network.
IEEE Trans. Emerg. Top. Comput.
Huiyi Gu, Xiaotao Jia, Yuhao Liu, Jianlei Yang, Xueyan Wang, Youguang Zhang, Sorin Dan Cotofana, Weisheng Zhao
2024 J jnl
DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao
2024 A* conf
FRM-CIM: Full-Digital Recursive MAC Computing in Memory System Based on MRAM for Neural Network Applications.
DAC
Jinkai Wang, Zekun Wang, Bojun Zhang, Zhengkun Gu, Youxiang Chen, Weisheng Zhao, Yue Zhang
2024 A* conf
GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration.
DAC
Tong Qiao, Jianlei Yang, Yingjie Qi, Ao Zhou, Chen Bai, Bei Yu, Weisheng Zhao, Chunming Hu
2024 J jnl
GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration.
CoRR
Tong Qiao, Jianlei Yang, Yingjie Qi, Ao Zhou, Chen Bai, Bei Yu, Weisheng Zhao, Chunming Hu
2024 A* conf
Graph Neural Networks Automated Design and Deployment on Device-Edge Co-Inference Systems.
DAC
Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Zhi Yang, Weisheng Zhao, Chunming Hu
2024 J jnl
Graph Neural Networks Automated Design and Deployment on Device-Edge Co-Inference Systems.
CoRR
Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Zhi Yang, Weisheng Zhao, Chunming Hu
2024 J jnl
HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices.
CoRR
Ao Zhou, Jianlei Yang, Yingjie Qi, Tong Qiao, Yumeng Shi, Cenlin Duan, Weisheng Zhao, Chunming Hu
2024 J jnl
HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices.
IEEE Trans. Computers
Ao Zhou, Jianlei Yang, Yingjie Qi, Tong Qiao, Yumeng Shi, Cenlin Duan, Weisheng Zhao, Chunming Hu
2024 — conf
LLP-ECCA: A Low-Latency and Programmable Framework for Elliptic Curve Cryptography Accelerators.
ITC-Asia
Yicheng Huang, Xueyan Wang, Tianao Dai, Jianlei Yang, Zhaojun Lu, Xiaotao Jia, Gang Qu, Weisheng Zhao
2024 J jnl
Multicorner Timing Analysis Acceleration for Iterative Physical Design of ICs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Wei W. Xing, Longze Wang, Zhelong Wang, Zhaoyu Shi, Ning Xu, Yuanqing Cheng, Weisheng Zhao
2024 A* conf
PPGNN: Fast and Accurate Privacy-Preserving Graph Neural Network Inference via Parallel and Pipelined Arithmetic-and-Logic FHE Accelerator.
DAC
Yuntao Wei, Xueyan Wang, Song Bian, Yicheng Huang, Weisheng Zhao, Yier Jin
2024 A* conf
Series-Parallel Hybrid SOT-MRAM Computing-in-Memory Macro with Multi-Method Modulation for High Area and Energy Efficiency.
DAC
Weiliang Huang, Jinyu Bai, Wang Kang, Zhaohao Wang, Kaihua Cao, Hongxi Liu, He Zhang, Weisheng Zhao
2024 J jnl
Spin-orbit torque efficiency enhancement to tungsten-based SOT-MTJs by interface modification with an ultrathin MgO.
Sci. China Inf. Sci.
Shiyang Lu, Xiaobai Ning, Hongchao Zhang, Sixi Zhen, Xiaofei Fan, Danrong Xiong, Dapeng Zhu, Gefei Wang, Hongxi Liu, Kaihua Cao, Weisheng Zhao
2024 J jnl
Toward Energy-efficient STT-MRAM-based Near Memory Computing Architecture for Embedded Systems.
ACM Trans. Embed. Comput. Syst.
Yueting Li, Xueyan Wang, He Zhang, Biao Pan, Keni Qiu, Wang Kang, Jun Wang, Weisheng Zhao
2024 A* conf
Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity.
DAC
Cenlin Duan, Jianlei Yang, Yiou Wang, Yikun Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2024 J jnl
Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity.
CoRR
Cenlin Duan, Jianlei Yang, Yiou Wang, Yikun Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao
2023 J jnl
A Survey of MRAM-Centric Computing: From Near Memory to In Memory.
IEEE Trans. Emerg. Top. Comput.
Yueting Li, Tianshuo Bai, Xinyi Xu, Yundong Zhang, Bi Wu, Hao Cai, Biao Pan, Weisheng Zhao
2023 J jnl
BoA-PTA: A Bayesian Optimization Accelerated PTA Solver for SPICE Simulation.
ACM Trans. Design Autom. Electr. Syst.
Wei W. Xing, Xiang Jin, Tian Feng, Dan Niu, Weisheng Zhao, Zhou Jin
2023 J jnl
DDC-PIM: Efficient Algorithm/Architecture Co-design for Doubling Data Capacity of SRAM-based Processing-In-Memory.
CoRR
Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao
2023 J jnl
Experimental Demonstration of STT-MRAM-based Nonvolatile Instantly On/Off System for IoT Applications: Case Studies.
ACM Trans. Embed. Comput. Syst.
Yueting Li, Wang Kang, Kunyu Zhou, Keni Qiu, Weisheng Zhao
2023 — conf
Full reliability characterization of three-terminal SOT-MTJ devices and corresponding arrays.
IRPS
Xinyi Xu, Hongchao Zhang, Chuanpeng Jiang, Jinhao Li, Shiyang Lu, Yunpeng Li, Honglei Du, Xueying Zhang, Zhaohao Wang, Kaihua Cao, Weisheng Zhao, Shuqin Lyu, Hao Xu, Bonian Jiang, Le Wang, Bowen Man, Cong Zhang, Dandan Li, Shuhui Li, Xiaofei Fan, Gefei Wang, Hongxi Liu
2023 A* conf
Hardware-Aware Graph Neural Network Automated Design for Edge Computing Platforms.
DAC
Ao Zhou, Jianlei Yang, Yingjie Qi, Yumeng Shi, Tong Qiao, Weisheng Zhao, Chunming Hu
2023 J jnl
Hardware-Aware Graph Neural Network Automated Design for Edge Computing Platforms.
CoRR
Ao Zhou, Jianlei Yang, Yingjie Qi, Yumeng Shi, Tong Qiao, Weisheng Zhao, Chunming Hu
2023 J jnl
IMGA: Efficient In-Memory Graph Convolution Network Aggregation With Data Flow Optimizations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yuntao Wei, Xueyan Wang, Shangtong Zhang, Jianlei Yang, Xiaotao Jia, Zhaohao Wang, Gang Qu, Weisheng Zhao
2023 J jnl
Implementation of 16 Boolean logic operations based on one basic cell of spin-transfer-torque magnetic random access memory.
Sci. China Inf. Sci.
Yan Huang, Kaihua Cao, Kun Zhang, Jinkai Wang, Kewen Shi, Zuolei Hao, Wenlong Cai, Ao Du, Jialiang Yin, Qing Yang, Junfeng Li, Jianfeng Gao, Chao Zhao, Weisheng Zhao
2023 J jnl
Layout Aware Optimization Methodology for SOT-MRAM Based on Technically Feasible Top-Pinned Magnetic Tunnel Junction Process.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chao Wang, Zhaohao Wang, Zhongkui Zhang, Jiagao Feng, Youguang Zhang, Weisheng Zhao
2023 J jnl
NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration.
Sci. China Inf. Sci.
Yinglin Zhao, Jianlei Yang, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao
2023 J jnl
Outgoing Editorial.
IEEE Trans. Circuits Syst. I Regul. Pap.
Weisheng Zhao, Hai Helen Li, Domenico Zito
2023 A conf
TAM: A Computing in Memory based on Tandem Array within STT-MRAM for Energy-Efficient Analog MAC Operation.
DATE
Jinkai Wang, Zhengkun Gu, Hongyu Wang, Zuolei Hao, Bojun Zhang, Weisheng Zhao, Yue Zhang
2023 A conf
THE-V: Verifiable Privacy-Preserving Neural Network via Trusted Homomorphic Execution.
ICCAD
Yuntao Wei, Xueyan Wang, Song Bian, Weisheng Zhao, Yier Jin
2023 A* conf
TOTAL: Multi-Corners Timing Optimization Based on Transfer and Active Learning.
DAC
Wei W. Xing, Zheng Xing, Rongqi Lu, Zhelong Wang, Ning Xu, Yuanqing Cheng, Weisheng Zhao
2023 J jnl
TinyFormer: Efficient Transformer Design and Deployment on Tiny Devices.
CoRR
Jianlei Yang, Jiacheng Liao, Fanding Lei, Meichen Liu, Junyi Chen, Lingkun Long, Han Wan, Bei Yu, Weisheng Zhao
2023 — conf
Toward Energy-Efficient Sparse Matrix-Vector Multiplication with near STT-MRAM Computing Architecture.
ASP-DAC
Yueting Li, He Zhang, Xueyan Wang, Hao Cai, Yundong Zhang, Shuqin Lv, Renguang Liu, Weisheng Zhao
2022 J jnl
A Machine Learning Attack-Resilient Strong PUF Leveraging the Process Variation of MRAM.
IEEE Trans. Circuits Syst. II Express Briefs
Rashid Ali, Deming Zhang, Hao Cai, Weisheng Zhao, You Wang
2022 J jnl
A Mini Tutorial of Processing in Memory: From Principles, Devices to Prototypes.
IEEE Trans. Circuits Syst. II Express Briefs
Biao Pan, Guangyao Wang, He Zhang, Wang Kang, Weisheng Zhao
2022 J jnl
A Spintronic In-Memory Computing Network for Efficient Hamming Codec Implementation.
IEEE Trans. Circuits Syst. II Express Briefs
Linjun Jiang, Erya Deng, He Zhang, Zhaohao Wang, Wang Kang, Weisheng Zhao
2022 J jnl
Accelerating Graph-Connected Component Computation With Emerging Processing-In-Memory Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xuhang Chen, Xueyan Wang, Xiaotao Jia, Jianlei Yang, Gang Qu, Weisheng Zhao
2022 — conf
An In-memory Booth Multiplier Based on Non-volatile Memory for Neural Network Applications.
NANOARCH
Jiayao Wu, Yijiao Wang, Zhi Yang, Kuiqing He, Pengxu Wang, Weisheng Zhao
2022 A* conf
CP-SRAM: charge-pulsation SRAM marco for ultra-high energy-efficiency computing-in-memory.
DAC
He Zhang, Linjun Jiang, Jianxin Wu, Tingran Chen, Junzhan Liu, Wang Kang, Weisheng Zhao
2022 J jnl
Eventor: An Efficient Event-Based Monocular Multi-View Stereo Accelerator on FPGA Platform.
CoRR
Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao
2022 A* conf
Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platform.
DAC
Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao
2022 J jnl
Femtosecond laser-assisted switching in perpendicular magnetic tunnel junctions with double-interface free layer.
Sci. China Inf. Sci.
Luding Wang, Wenlong Cai, Kaihua Cao, Kewen Shi, Bert Koopmans, Weisheng Zhao
2022 J jnl
NAND-SPIN-Based Processing-in-MRAM Architecture for Convolutional Neural Network Acceleration.
CoRR
Yinglin Zhao, Jianlei Yang, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao
2022 J jnl
S
IEEE Trans. Computers
Jianlei Yang, Wenzhi Fu, Xingzhou Cheng, Xucheng Ye, Pengcheng Dai, Weisheng Zhao
2022 — ch.
Spintronic Solutions for Approximate Computing.
Approximate Computing
You Wang, Hao Cai, Kaili Zhang, Bo Wu, Bo Liu, Deming Zhang, Weisheng Zhao
2022 J jnl
Stateful implication logic based on perpendicular magnetic tunnel junctions.
Sci. China Inf. Sci.
Wenlong Cai, Mengxing Wang, Kaihua Cao, Huaiwen Yang, Shouzhong Peng, Huisong Li, Weisheng Zhao
2022 J jnl
Towards Systems Education for Artificial Intelligence: A Course Practice in Intelligent Computing Architectures.
CoRR
Jianlei Yang, Xiaopeng Gao, Weisheng Zhao
2022 J jnl
Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture.
IEEE Trans. Computers
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Rong Yin, Xuhang Chen, Gang Qu, Weisheng Zhao
2022 Misc conf
Work-in-Progress: Toward Energy-efficient Near STT-MRAM Processing Architecture for Neural Networks.
CODES+ISSS
Yueting Li, Bingluo Zhao, Xinyi Xu, Yundong Zhang, Jun Wang, Weisheng Zhao
2021 — conf
A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output.
ICTA
He Zhang, Junzhan Liu, Wang Kang, Yunqian Fan, Shufeng Fu, Jinyu Bai, Biao Pan, Yongpan Liu, Weisheng Zhao
2021 — conf
A Computing-in-memory Scheme with Series Bit-cell in STT-MRAM for Efficient Multi-bit Analog Multiplication.
NANOARCH
Zuolei Hao, Yue Zhang, Jinkai Wang, Hongyu Wang, Yining Bai, Guanda Wang, Weisheng Zhao
2021 J jnl
A NAND-SPIN-Based Magnetic ADC.
IEEE Trans. Circuits Syst. II Express Briefs
Bi Wu, Zhaohao Wang, Yuxuan Li, Ying Wang, Dijun Liu, Weisheng Zhao, Xiaobo Sharon Hu
2021 — conf
A Novel Multi-Context Non-Volatile Content-Addressable Memory Cell and Multi-Level Architecture for High Reliability and Density.
NVMSA
Xian Wang, Deming Zhang, Kaili Zhang, Erya Deng, You Wang, Weisheng Zhao
2021 C conf
A Reconfigurable Arbiter PUF Based on STT-MRAM.
ISCAS
Rashid Ali, You Wang, Haoyuan Ma, Zhengyi Hou, Deming Zhang, Erya Deng, Weisheng Zhao
2021 A conf
Brief Industry Paper: optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms.
RTAS
Ao Zhou, Jianlei Yang, Yeqi Gao, Tong Qiao, Yingjie Qi, Xiaoyi Wang, Yunli Chen, Pengcheng Dai, Weisheng Zhao, Chunming Hu
2021 C conf
Computing-in-Memory Paradigm Based on STT-MRAM with Synergetic Read/Write-Like Modes.
ISCAS
Chao Wang, Zhaohao Wang, Youguang Zhang, Weisheng Zhao
2021 J jnl
Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization.
IEEE Trans. Neural Networks Learn. Syst.
Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao
2021 A conf
FedSkel: Efficient Federated Learning on Heterogeneous Systems with Skeleton Gradients Update.
CIKM
Junyu Luo, Jianlei Yang, Xucheng Ye, Xin Guo, Weisheng Zhao
2021 J jnl
FedSkel: Efficient Federated Learning on Heterogeneous Systems with Skeleton Gradients Update.
CoRR
Junyu Luo, Jianlei Yang, Xucheng Ye, Xin Guo, Weisheng Zhao
2021 J jnl
Forecasting the outcome of spintronic experiments with Neural Ordinary Differential Equations.
CoRR
Xing Chen, Flavio Abreu Araujo, Mathieu Riou, Jacob Torrejon, Dafine Ravelosona, Wang Kang, Weisheng Zhao, Julie Grollier, Damien Querlioz
2021 C conf
Fully Single Event Double Node Upset Tolerant Design for Magnetic Random Access Memory.
ISCAS
Deming Zhang, Xian Wang, Kaili Zhang, Lang Zeng, You Wang, Bi Wang, Erya Deng, Chuanjie Wang, Peng Wu, Youguang Zhang, Weisheng Zhao
2021 J jnl
Optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms.
CoRR
Ao Zhou, Jianlei Yang, Yeqi Gao, Tong Qiao, Yingjie Qi, Xiaoyi Wang, Yunli Chen, Pengcheng Dai, Weisheng Zhao, Chunming Hu
2021 J jnl
Proposal of High Density Two-Bits-Cell Based NAND-Like Magnetic Random Access Memory.
IEEE Trans. Circuits Syst. II Express Briefs
Zhitai Yu, Yijiao Wang, Zeqing Zhang, Kuiqing He, Lang Zeng, Zhaohao Wang, Weisheng Zhao
2021 J jnl
S2Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks.
CoRR
Jianlei Yang, Wenzhi Fu, Xingzhou Cheng, Xucheng Ye, Pengcheng Dai, Weisheng Zhao
2021 — conf
Soft Error Sensitivity of Magnetic Random Access Memory and Its Radiation Hardening Design.
ISOCC
Bi Wang, Zhaohao Wang, Min Wang, Weisheng Zhao, Liang Wang, Yuanfu Zhao
2021 C conf
Spin-Orbit Torque Nonvolatile Flip-Flop Designs.
ISCAS
Erya Deng, Wang Kang, Weisheng Zhao, Shaoqian Wei, You Wang, Deming Zhang
2021 A conf
SpinLiM: Spin Orbit Torque Memory for Ternary Neural Networks Based on the Logic-in-Memory Architecture.
DATE
Lichuan Luo, He Zhang, Jinyu Bai, Youguang Zhang, Wang Kang, Weisheng Zhao
2021 C conf
SpinSim: A Computer Architecture-Level Variation Aware STT-MRAM Performance Evaluation Framework.
ISCAS
Haoyuan Ma, You Wang, Rashid Ali, Zhengyi Hou, Deming Zhang, Erya Deng, Gefei Wang, Weisheng Zhao
2021 J jnl
Spintronics for Energy- Efficient Computing: An Overview and Outlook.
Proc. IEEE
Zongxia Guo, Jialiang Yin, Yue Bai, Daoqian Zhu, Kewen Shi, Gefei Wang, Kaihua Cao, Weisheng Zhao
2021 — conf
Tiny neural network search and implementation for embedded FPGA: a software-hardware co-design approach.
A-SSCC
Jinyu Bai, Yunqian Fan, Sifan Sun, Wang Kang, Weisheng Zhao
2021 J jnl
Toward Energy-Efficient STT-MRAM Design With Multi-Modes Reconfiguration.
IEEE Trans. Circuits Syst. II Express Briefs
Hao Cai, Juntong Chen, Yongliang Zhou, Weisheng Zhao
2021 J jnl
Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture.
CoRR
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Rong Yin, Xuhang Chen, Gang Qu, Weisheng Zhao
2020 J jnl
A Comparative Cross-layer Study on Racetrack Memories: Domain Wall vs Skyrmion.
ACM J. Emerg. Technol. Comput. Syst.
Wang Kang, Bi Wu, Xing Chen, Daoqian Zhu, Zhaohao Wang, Xichao Zhang, Yan Zhou, Youguang Zhang, Weisheng Zhao
2020 J jnl
A Diode-Enhanced Scheme for Giant Magnetoresistance Amplification and Reconfigurable Logic.
IEEE Access
Jiang Nan, Kun Zhang, Yue Zhang, Shaohua Yan, Zhizhong Zhang, Zhenyi Zheng, Guanda Wang, Qunwen Leng, Youguang Zhang, Weisheng Zhao
2020 J jnl
A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bi Wu, Pengcheng Dai, Yuanqing Cheng, Ying Wang, Jianlei Yang, Zhaohao Wang, Dijun Liu, Weisheng Zhao
2020 — conf
A Novel In-memory Computing Scheme Based on Toggle Spin Torque MRAM.
ACM Great Lakes Symposium on VLSI
Yining Bai, Yue Zhang, Jinkai Wang, Guanda Wang, Zhizhong Zhang, Zhenyi Zheng, Kun Zhang, Weisheng Zhao
2020 J jnl
A Self-Timed Voltage-Mode Sensing Scheme With Successive Sensing and Checking for STT-MRAM.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl.
Yongliang Zhou, Hao Cai, Lei Xie, Menglin Han, Mingyue Liu, Shi Xu, Bo Liu, Weisheng Zhao, Jun Yang
2020 — conf
An In-memory Highly Reconfigurable Logic Circuit Based on Diode-assisted Enhanced Magnetoresistance Device.
ACM Great Lakes Symposium on VLSI
Zhe Huang, Yue Zhang, Kun Zhang, Zhizhong Zhang, Jinkai Wang, Youguang Zhang, Weisheng Zhao
2020 J jnl
An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing.
CCF Trans. High Perform. Comput.
Yu Pan, Xiaotao Jia, Zhen Cheng, Peng Ouyang, Xueyan Wang, Jianlei Yang, Weisheng Zhao
2020 J jnl
Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bi Wu, Weisheng Zhao, Xiaobo Sharon Hu, Pengcheng Dai, Zhaohao Wang, Chao Wang, Ying Wang, Jianlei Yang, Yuanqing Cheng, Dijun Liu, Youguang Zhang
2020 J jnl
Compact Modeling and Analysis of Voltage-Gated Spin-Orbit Torque Magnetic Tunnel Junction.
IEEE Access
Kaili Zhang, Deming Zhang, Chengzhi Wang, Lang Zeng, You Wang, Weisheng Zhao
2020 C conf
Computing-in-Memory Architecture Based on Field-Free SOT-MRAM with Self-Reference Method.
ISCAS
Chao Wang, Zhaohao Wang, Yansong Xu, Jianlei Yang, Youguang Zhang, Weisheng Zhao
2020 — conf
Deep Neural Network accelerator with Spintronic Memory.
ACM Great Lakes Symposium on VLSI
He Zhang, Wang Kang, Youguang Zhang, Weisheng Zhao
2020 J jnl
Design of Magnetic Non-Volatile TCAM With Priority-Decision in Memory Technology for High Speed, Low Power, and High Reliability.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chengzhi Wang, Deming Zhang, Lang Zeng, Weisheng Zhao
2020 J jnl
Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization.
CoRR
Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao
2020 C conf
Efficient Time-Domain In-Memory Computing Based on TST-MRAM.
ISCAS
Jinkai Wang, Yue Zhang, Chenyu Lian, Yining Bai, Zhe Huang, Guanda Wang, Kun Zhang, Youguang Zhang, Weisheng Zhao
2020 — ed.
GLSVLSI '20: Great Lakes Symposium on VLSI 2020, Virtual Event, China, September 7-9, 2020
ACM Great Lakes Symposium on VLSI
Tinoosh Mohsenin, Weisheng Zhao, Yiran Chen, Onur Mutlu
2020 J jnl
Hardware Security in Spin-Based Computing-In-Memory: Analysis, Exploits, and Mitigation Techniques.
CoRR
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Gang Qu, Weisheng Zhao
2020 J jnl
Hardware Security in Spin-based Computing-in-memory: Analysis, Exploits, and Mitigation Techniques.
ACM J. Emerg. Technol. Comput. Syst.
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Gang Qu, Weisheng Zhao
2020 A conf
High-Density, Low-Power Voltage-Control Spin Orbit Torque Memory with Synchronous Two-Step Write and Symmetric Read Techniques.
DATE
Haotian Wang, Wang Kang, Liuyang Zhang, He Zhang, Brajesh Kumar Kaushik, Weisheng Zhao
2020 J jnl
MTJ-LRB: Proposal of MTJ-Based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing.
IEEE Trans. Circuits Syst.
Yongliang Zhou, Hao Cai, Bo Liu, Weisheng Zhao, Jun Yang
2020 J jnl
Movable-Type Transfer and Stacking of van der Waals Heterostructures for Spintronics.
IEEE Access
Yuan Cao, Xinhe Wang, Xiaoyang Lin, Wei Yang, Chen Lv, Yuan Lu, Youguang Zhang, Weisheng Zhao
2020 C conf
PRISM: Energy-Efficient Polymorphic Operation Based on Spin-Orbit Torque Memory for Reconfigurable Computing.
ISCAS
Liang Chang, Zhaohao Wang, Yang Zhao, Youguang Zhang, Weisheng Zhao, Jun Zhou
2020 J jnl
Prototyping federated learning on edge computing systems.
Frontiers Comput. Sci.
Jianlei Yang, Yixiao Duan, Tong Qiao, Huanyu Zhou, Jingyuan Wang, Weisheng Zhao
2020 J jnl
SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Xiaotao Jia, Jianlei Yang, Pengcheng Dai, Runze Liu, Yiran Chen, Weisheng Zhao
2020 A* conf
SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training.
DAC
Pengcheng Dai, Jianlei Yang, Xucheng Ye, Xingzhou Cheng, Junyu Luo, Linghao Song, Yiran Chen, Weisheng Zhao
2020 J jnl
SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training.
CoRR
Pengcheng Dai, Jianlei Yang, Xucheng Ye, Xingzhou Cheng, Junyu Luo, Linghao Song, Yiran Chen, Weisheng Zhao
2020 A* conf
TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture.
DAC
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao
2020 J jnl
TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture.
CoRR
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao
2020 — conf
Towards Systems Education for Artificial Intelligence: A Course Practice in Intelligent Computing Architectures.
ACM Great Lakes Symposium on VLSI
Jianlei Yang, Xiaopeng Gao, Weisheng Zhao
2020 C conf
Voltage-Gated Spin-Hall Effect Based Magnetic Non-Volatile Flip-Flop for High Speed, Low Power and Compact Cell Area.
ISCAS
Kaili Zhang, Deming Zhang, Chengzhi Wang, Lang Zeng, Weisheng Zhao
2020 J jnl
Write Back Energy Optimization for STT-MRAM-based Last-level Cache with Data Pattern Characterization.
ACM J. Emerg. Technol. Comput. Syst.
Jiacheng Ni, Keren Liu, Bi Wu, Weisheng Zhao, Yuanqing Cheng, Xiaolong Zhang, Ying Wang
2019 J jnl
A Novel MTJ-Based Non-Volatile Ternary Content-Addressable Memory for High-Speed, Low-Power, and High-Reliable Search Operation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chengzhi Wang, Deming Zhang, Lang Zeng, Erya Deng, Jie Chen, Weisheng Zhao
2019 — conf
A Skyrmion Racetrack Memory based Computing In-memory Architecture for Binary Neural Convolutional Network.
ACM Great Lakes Symposium on VLSI
Yu Pan, Peng Ouyang, Yinglin Zhao, Shouyi Yin, Youguang Zhang, Shaojun Wei, Weisheng Zhao
2019 J jnl
Accelerating CNN Training by Sparsifying Activation Gradients.
CoRR
Xucheng Ye, Jianlei Yang, Pengcheng Dai, Yiran Chen, Weisheng Zhao
2019 J jnl
Addressing Failure and Aging Degradation in MRAM/MeRAM-on-FDSOI Integration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hao Cai, You Wang, Lirida Alves de Barros Naviner, Xinning Liu, Weiwei Shan, Jun Yang, Weisheng Zhao
2019 J jnl
An Adaptive Thermal-Aware ECC Scheme for Reliable STT-MRAM LLC Design.
IEEE Trans. Very Large Scale Integr. Syst.
Bi Wu, Beibei Zhang, Yuanqing Cheng, Ying Wang, Dijun Liu, Weisheng Zhao
2019 J jnl
An STT-MRAM Based in Memory Architecture for Low Power Integral Computing.
IEEE Trans. Computers
Yinglin Zhao, Peng Ouyang, Wang Kang, Shouyi Yin, Youguang Zhang, Shaojun Wei, Weisheng Zhao
2019 A conf
CORN: In-Buffer Computing for Binary Neural Network.
DATE
Liang Chang, Xin Ma, Zhaohao Wang, Youguang Zhang, Weisheng Zhao, Yuan Xie
2019 J jnl
DASM: Data-Streaming-Based Computing in Nonvolatile Memory Architecture for Embedded System.
IEEE Trans. Very Large Scale Integr. Syst.
Liang Chang, Xin Ma, Zhaohao Wang, Youguang Zhang, Yufei Ding, Weisheng Zhao, Yuan Xie
2019 J jnl
Erase-hidden and Drivability-improved Magnetic Non-Volatile Flip-Flops with NAND-SPIN Devices.
CoRR
Ziyi Wang, Zhaohao Wang, Yansong Xu, Bi Wu, Weisheng Zhao
2019 — conf
Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration.
ISVLSI
Yinglin Zhao, Jianlei Yang, Xiaotao Jia, Xueyan Wang, Zhaohao Wang, Wang Kang, Youguang Zhang, Weisheng Zhao
2019 J jnl
Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jianlei Yang, Xueyan Wang, Qiang Zhou, Zhaohao Wang, Hai Li, Yiran Chen, Weisheng Zhao
2019 — conf
High speed and reliable Sensing Scheme with Three Voltages for STT-MRAM.
NANOARCH
Jinkai Wang, Yue Zhang, Chenyu Lian, Guanda Wang, Kun Zhang, Xiulong Wu, Youguang Zhang, Weisheng Zhao
2019 J jnl
Low-Power (1T1N) Skyrmionic Synapses for Spiking Neuromorphic Systems.
IEEE Access
Tinish Bhattacharya, Sai Li, Yangqi Huang, Wang Kang, Weisheng Zhao, Manan Suri
2019 — conf
Low-Power, High-Speed and High-Density Magnetic Non-Volatile SRAM Design with Voltage-Gated Spin-Orbit Torque.
NANOARCH
Chengzhi Wang, Deming Zhang, Lang Zeng, Kaili Zhang, Youguang Zhang, Weisheng Zhao
2019 C conf
Magnetic Skyrmion-Based Neural Recording System Design for Brain Machine Interface.
ISCAS
Biao Pan, Kang Wang, Xing Chen, Jinyu Bai, Jianlei Yang, Sai Li, Youguang Zhang, Weisheng Zhao
2019 C conf
Modulation and Demodulation of Digital Frequency Shift Keying System Based on Spin Torque Nano Oscillator with Voltage Controlled Magnetic Anisotropy Effect.
ISCAS
Lang Zeng, Zuodong Zhang, Haoxuan Chen, Tianqi Gao, Deming Zhang, Mingzhi Long, Youguang Zhang, Weisheng Zhao
2019 J jnl
Multi-Port 1R1W Transpose Magnetic Random Access Memory by Hierarchical Bit-Line Switching.
IEEE Access
Liang Chang, Zhaohao Wang, Youguang Zhang, Weisheng Zhao
2019 J jnl
Novel Radiation Hardening Read/Write Circuits Using Feedback Connections for Spin-Orbit Torque Magnetic Random Access Memory.
IEEE Trans. Circuits Syst. I Regul. Pap.
Bi Wang, Zhaohao Wang, Bi Wu, Yumeng Bai, Kaihua Cao, Yuanfu Zhao, Youguang Zhang, Weisheng Zhao
2019 J jnl
PXNOR-BNN: In/With Spin-Orbit Torque MRAM Preset-XNOR Operation-Based Binary Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Liang Chang, Xin Ma, Zhaohao Wang, Youguang Zhang, Yuan Xie, Weisheng Zhao
2019 — conf
Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel Junction.
ISVLSI
Hao Cai, Honglan Jiang, Menglin Han, Zhaohao Wang, You Wang, Jun Yang, Jie Han, Leibo Liu, Weisheng Zhao
2019 — ed.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, GLSVLSI 2019, Tysons Corner, VA, USA, May 9-11, 2019
ACM Great Lakes Symposium on VLSI
Houman Homayoun, Baris Taskin, Tinoosh Mohsenin, Weisheng Zhao
2019 — conf
Process Variation-Resilient STT-MTJ based TRNG using Linear Correcting Codes.
NANOARCH
Rashid Ali, You Wang, Zhengyi Hou, Haoyuan Ma, Youguang Zhang, Weisheng Zhao
2019 J jnl
SPINBIS: Spintronics based Bayesian Inference System with Stochastic Computing.
CoRR
Xiaotao Jia, Jianlei Yang, Pengcheng Dai, Runze Liu, Yiran Chen, Weisheng Zhao
2019 C conf
SR-WTA: Skyrmion Racing Winner-Takes-All Module for Spiking Neural Computing.
ISCAS
Biao Pan, Kang Wang, Xing Chen, Jinyu Bai, Jianlei Yang, Youguang Zhang, Weisheng Zhao
2019 — conf
Shaped Content Addressable Memory Based On Spin Orbit Torque Driven Chiral Domain Wall Motions.
NANOARCH
Yue Zhang, Jiang Nan, Guanda Wang, Xueying Zhang, Youguang Zhang, Weisheng Zhao
2019 — conf
Spintronic Memories: From Memory to Computing-in-Memory.
NANOARCH
Wang Kang, He Zhang, Weisheng Zhao
2019 — conf
Thermal Stable and Fast Perpendicular Shape Anisotropy Magnetic Tunnel Junction.
NANOARCH
Guanda Wang, Yue Zhang, Zhe Huang, Jinkai Wang, Kun Zhang, Zhizhong Zhang, Youguang Zhang, Weisheng Zhao
2019 J jnl
Ultra-Dense Ring-Shaped Racetrack Memory Cache Design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Guanda Wang, Yue Zhang, Beibei Zhang, Bi Wu, Jiang Nan, Xueying Zhang, Zhizhong Zhang, Jacques-Olivier Klein, Dafine Ravelosona, Zhaohao Wang, Youguang Zhang, Weisheng Zhao
2019 — conf
Ultra-fast and Energy-efficient Write-Computing Operation for Neuromorphic Computing.
ISOCC
Liang Chang, Zhaohao Wang, Youguang Zhang, Weisheng Zhao
2019 — conf
Ultra-low power consumption Spintronics Devices.
ASICON
Zongxia Guo, Kaihua Cao, Kewen Shi, Weisheng Zhao
2019 — conf
Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI.
ACM Great Lakes Symposium on VLSI
Hao Cai, Menglin Han, Weiwei Shan, Jun Yang, You Wang, Wang Kang, Weisheng Zhao
2019 A* conf
ZUMA: Enabling Direct Insertion/Deletion Operations with Emerging Skyrmion Racetrack Memory.
DAC
Zheng Liang, Guangyu Sun, Wang Kang, Xing Chen, Weisheng Zhao
2019 A* conf
eSLAM: An Energy-Efficient Accelerator for Real-Time ORB-SLAM on FPGA Platform.
DAC
Runze Liu, Jianlei Yang, Yiran Chen, Weisheng Zhao
2019 J jnl
eSLAM: An Energy-Efficient Accelerator for Real-Time ORB-SLAM on FPGA Platform.
CoRR
Runze Liu, Jianlei Yang, Yiran Chen, Weisheng Zhao
2018 — conf
A Comparative Study on Racetrack Memories: Domain Wall vs. Skyrmion.
NVMSA
Wang Kang, Xing Chen, Daoqian Zhu, Xichao Zhang, Yan Zhou, Keni Qiu, Youguang Zhang, Weisheng Zhao
2018 J jnl
A Fast and Power-Efficient Hardware Architecture for Visual Feature Detection in Affine-SIFT.
IEEE Trans. Circuits Syst. I Regul. Pap.
Peng Ouyang, Shouyi Yin, Leibo Liu, Youguang Zhang, Weisheng Zhao, Shaojun Wei
2018 J jnl
A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM.
IEEE Access
He Zhang, Wang Kang, Youguang Zhang, Meng-Fan Chang, Weisheng Zhao
2018 — conf
A Novel 15T-4MTJ based Non-volatile Ternary Content-Addressable Memory Cell for High-Speed, Low-Power and High-Reliable Search Operation.
APCCAS
Chengzhi Wang, Deming Zhang, Lang Zeng, Jie Chen, Weisheng Zhao
2018 — conf
A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation.
NANOARCH
Chaoxin Ding, Wang Kang, He Zhang, Youguang Zhang, Weisheng Zhao
2018 — conf
A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM.
ISVLSI
Liuyang Zhang, Wang Kang, Hao Cai, Peng Ouyang, Lionel Torres, Youguang Zhang, Aida Todri-Sanial, Weisheng Zhao
2018 — conf
A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform.
FPT
Wenzhi Fu, Jianlei Yang, Pengcheng Dai, Yiran Chen, Weisheng Zhao
2018 J jnl
A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform.
CoRR
Wenzhi Fu, Jianlei Yang, Pengcheng Dai, Yiran Chen, Weisheng Zhao
2018 — conf
Design Space Exploration of Magnetic Tunnel Junction based Stochastic Computing in Deep Learning.
ACM Great Lakes Symposium on VLSI
You Wang, Yue Zhang, Youguang Zhang, Weisheng Zhao, Hao Cai, Lirida A. B. Naviner
2018 C conf
Design and Data Management for Magnetic Racetrack Memory.
ISCAS
Bing Li, Fan Chen, Wang Kang, Weisheng Zhao, Yiran Chen, Hai Li
2018 — conf
Emerging Neuromorphic Computing Paradigms Exploring Magnetic Skyrmions.
ISVLSI
Sai Li, Wang Kang, Xing Chen, Jinyu Bai, Biao Pan, Youguang Zhang, Weisheng Zhao
2018 C conf
Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques.
ISCAS
Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner, Weiwei Shan, Jun Yang, Weisheng Zhao
2018 J jnl
Exploiting Spin-Orbit Torque Devices as Reconfigurable Logic for Circuit Obfuscation.
CoRR
Jianlei Yang, Xueyan Wang, Qiang Zhou, Zhaohao Wang, Hai Li, Yiran Chen, Weisheng Zhao
2018 — conf
Hardware Acceleration Implementation of Sparse Coding Algorithm with Spintronic Devices.
NANOARCH
Deming Zhang, Yanchun Hou, Chengzhi Wang, Jie Chen, Lang Zeng, Weisheng Zhao
2018 — conf
High-Density and Fast-Configuration Non-Volatile Look-Up Table Based on NAND-Like Spintronic Memory.
APCCAS
He Zhang, Wang Kang, Zhaohao Wang, Erya Deng, Youguang Zhang, Weisheng Zhao
2018 — conf
MRAM-on-FDSOI Integration: A Bit-Cell Perspective.
ISVLSI
Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner, Xinning Liu, Jun Yang, Weisheng Zhao
2018 A conf
Magnetic skyrmions for future potential memory and logic applications: Alternative information carriers.
DATE
Wang Kang, Xing Chen, Daoqian Zhu, Sai Li, Yangqi Huang, Youguang Zhang, Weisheng Zhao
2018 C conf
Multi-bit nonvolatile flip-flop based on NAND-like spin transfer torque MRAM.
VLSI-SoC
Erya Deng, Zhaohao Wang, Wang Kang, Shaoqian Wei, Weisheng Zhao
2018 C conf
NEAR: A Novel Energy Aware Replacement Policy for STT-MRAM LLCs.
ISCAS
Chen Liu, Yuanqing Cheng, Ying Wang, Youguang Zhang, Weisheng Zhao
2018 J jnl
Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint.
J. Comput. Sci. Technol.
Yinglin Zhao, Jianlei Yang, Weisheng Zhao, Aida Todri-Sanial, Yuanqing Cheng
2018 — conf
Process variation aware data management for magnetic skyrmions racetrack memory.
ASP-DAC
Fan Chen, Zheng Li, Wang Kang, Weisheng Zhao, Hai Li, Yiran Chen
2018 C conf
Progresses and challenges of spin orbit torque driven magnetization switching and application (Invited).
ISCAS
Zhaohao Wang, Zuwei Li, Yang Liu, Simin Li, Liang Chang, Wang Kang, Youguang Zhang, Weisheng Zhao
2018 C conf
Radiation hardening design for spin-orbit torque magnetic random access memory.
ISCAS
Bi Wang, Zhaohao Wang, Kaihua Cao, Youguang Zhang, Yuanfu Zhao, Weisheng Zhao
2018 — conf
Reliability Emphasized MTJ/CMOS Hybrid Circuit Towards Ultra-Low Power.
DCIS
Hao Cai, Menglin Han, You Wang, Lirida A. B. Naviner, Xinning Liu, Jun Yang, Weisheng Zhao
2018 — conf
Spintronics based stochastic computing for efficient Bayesian inference system.
ASP-DAC
Xiaotao Jia, Jianlei Yang, Zhaohao Wang, Yiran Chen, Hai Helen Li, Weisheng Zhao
2018 — conf
Stability and Variability Emphasized STT-MRAM Sensing Circuit With Performance Enhancement.
APCCAS
Menglin Han, Hao Cai, Jun Yang, Lirida A. B. Naviner, You Wang, Weisheng Zhao
2018 — conf
Write Energy Optimization for STT-MRAM Cache with Data Pattern Characterization.
ISVLSI
Bi Wu, Xiaolong Zhang, Yuanqing Cheng, Zhaohao Wang, Dijun Liu, Youguang Zhang, Weisheng Zhao
2017 A conf
A true random number generator based on parallel STT-MTJs.
DATE
Yuanzhuo Qu, Jie Han, Bruce F. Cockburn, Witold Pedrycz, Yue Zhang, Weisheng Zhao
2017 — conf
Advanced Low Power Spintronic Memories beyond STT-MRAM.
ACM Great Lakes Symposium on VLSI
Wang Kang, Zhaohao Wang, He Zhang, Sai Li, Youguang Zhang, Weisheng Zhao
2017 — conf
Arithmetic Logic Unit based on all-spin logic devices.
NEWCAS
Qi An, Sébastien Le Beux, Ian O'Connor, Jacques-Olivier Klein, Weisheng Zhao
2017 — conf
Compact modeling of high spin transfer torque efficiency double-barrier magnetic tunnel junction.
NANOARCH
Guanda Wang, Yue Zhang, Zhizhong Zhang, Jiang Nan, Zhenyi Zheng, Yu Wang, Lang Zeng, Youguang Zhang, Weisheng Zhao
2017 J jnl
Dynamic Dual-Reference Sensing Scheme for Deep Submicrometer STT-MRAM.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wang Kang, Tingting Pang, Weifeng Lv, Weisheng Zhao
2017 — conf
Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device.
ACM Great Lakes Symposium on VLSI
Hao Cai, You Wang, Lirida A. B. Naviner, Wang Kang, Weisheng Zhao
2017 — conf
Frequency modulation of spin torque nano oscillator with voltage controlled magnetic anisotropy effect.
NANOARCH
Zuodong Zhang, Lang Zeng, Tianqi Gao, Deming Zhang, Xiaowan Qin, Mingzhi Long, Youguang Zhang, Haiming Yu, Weisheng Zhao
2017 — conf
Interfacial property tuning of heavy metal/CoFeB for large density STT-MRAM.
NVMTS
Wenlong Cai, Kaihua Cao, Mengxing Wang, Shouzhong Peng, Jiaqi Zhou, Anni Cao, Boyu Zhang, Lezhi Wang, Yu Zhang, Jiaqi Wei, Xiaobin He, Hushan Cui, Chao Zhao, Weisheng Zhao
2017 — conf
Novel Pulsed-Latch Replacement in Non-Volatile Flip-Flop Core.
ISVLSI
Hao Cai, You Wang, Lirida A. B. Naviner, Weisheng Zhao
2017 A conf
PRESCOTT: Preset-based cross-point architecture for spin-orbit-torque magnetic random access memory.
ICCAD
Liang Chang, Zhaohao Wang, Alvin Oliver Glova, Jishen Zhao, Youguang Zhang, Yuan Xie, Weisheng Zhao
2017 C conf
Programmable Stateful In-Memory Computing Paradigm via a Single Resistive Device.
ICCD
Wang Kang, He Zhang, Peng Ouyang, Youguang Zhang, Weisheng Zhao
2017 — conf
Proposal for novel magnetic memory device with spin momentum locking materials.
NANOARCH
Xiaowan Qin, Lang Zeng, Tianqi Gao, Deming Zhang, Mingzhi Long, Youguang Zhang, Weisheng Zhao
2017 J jnl
Pseudo-Differential Sensing Framework for STT-MRAM: A Cross-Layer Perspective.
IEEE Trans. Computers
Wang Kang, Liang Chang, Zhaohao Wang, Weifeng Lv, Guangyu Sun, Weisheng Zhao
2017 — conf
Reconfigurable processing in memory architecture based on spin orbit torque.
NANOARCH
Liang Chang, Zhaohao Wang, Youguang Zhang, Weisheng Zhao
2017 J jnl
Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hao Cai, You Wang, Lirida Alves de Barros Naviner, Weisheng Zhao
2017 J jnl
Spintronics based Stochastic Computing for Efficient Bayesian Inference System.
CoRR
Xiaotao Jia, Jianlei Yang, Zhaohao Wang, Yiran Chen, Hai Li, Weisheng Zhao
2017 A conf
Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs.
ICCAD
Bi Wu, Yuanqing Cheng, Pengcheng Dai, Jianlei Yang, Youguang Zhang, Dijun Liu, Ying Wang, Weisheng Zhao
2017 — conf
Ultrafast spintronic integrated circuits.
ASICON
Jiaqi Wei, Liang Chang, Zhaohao Wang, Xiaoyang Lin, Kaihua Cao, Hushan Cui, Wang Kang, Haoxuan Chen, Lang Zeng, Youguang Zhang, Chao Zhao, Weisheng Zhao
2017 A conf
Voltage-controlled MRAM for working memory: Perspectives and challenges.
DATE
Wang Kang, Liang Chang, Youguang Zhang, Weisheng Zhao
2016 — conf
A novel circuit design of true random number generator using magnetic tunnel junction.
NANOARCH
You Wang, Hao Cai, Lirida A. B. Naviner, Jacques-Olivier Klein, Jianlei Yang, Weisheng Zhao
2016 J jnl
A process-variation-resilient methodology of circuit design by using asymmetrical forward body bias in 28 nm FDSOI.
Microelectron. Reliab.
You Wang, Hao Cai, Lirida A. B. Naviner, Xiaoxuan Zhao, Yue Zhang, Mariem Slimani, Jacques-Olivier Klein, Weisheng Zhao
2016 — conf
A spin Hall effect-based multi-level cell for MRAM.
NANOARCH
Qian Shi, Zhaohao Wang, Yuqian Gao, Liang Chang, Wang Kang, Youguang Zhang, Weisheng Zhao
2016 J jnl
All Spin Artificial Neural Networks Based on Compound Spintronic Synapse and Neuron.
IEEE Trans. Biomed. Circuits Syst.
Deming Zhang, Lang Zeng, Kaihua Cao, Mengxing Wang, Shouzhong Peng, Yue Zhang, Youguang Zhang, Jacques-Olivier Klein, Yu Wang, Weisheng Zhao
2016 J jnl
Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect.
IEEE Trans. Very Large Scale Integr. Syst.
Yuanqing Cheng, Aida Todri-Sanial, Jianlei Yang, Weisheng Zhao
2016 — conf
Approximate computing in MOS/spintronic non-volatile full-adder.
NANOARCH
Hao Cai, You Wang, Lirida A. B. Naviner, Zhaohao Wang, Weisheng Zhao
2016 J jnl
Complementary Skyrmion Racetrack Memory with Voltage Manipulation.
CoRR
Wang Kang, Chentian Zheng, Yangqi Huang, Xichao Zhang, Yan Zhou, Weifeng Lv, Weisheng Zhao
2016 — conf
Dual reference sensing scheme with triple steady states for deeply scaled STT-MRAM.
NANOARCH
He Zhang, Wang Kang, Tingting Pang, Weifeng Lv, Youguang Zhang, Weisheng Zhao
2016 — conf
Evaluation of spin-Hall-assisted STT-MRAM for cache replacement.
NANOARCH
Liang Chang, Zhaohao Wang, Yuqian Gao, Wang Kang, Youguang Zhang, Weisheng Zhao
2016 J jnl
Magnetic skyrmion-based synaptic devices.
CoRR
Yangqi Huang, Wang Kang, Xichao Zhang, Yan Zhou, Weisheng Zhao
2016 A* conf
PDS: pseudo-differential sensing scheme for STT-MRAM.
DAC
Wang Kang, Tingting Pang, Bi Wu, Weifeng Lv, Youguang Zhang, Guangyu Sun, Weisheng Zhao
2016 J jnl
Perspectives of Racetrack Memory for Large-Capacity On-Chip Memory: From Device to System.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yue Zhang, Chao Zhang, Jiang Nan, Zhizhong Zhang, Xueying Zhang, Jacques-Olivier Klein, Dafine Ravelosona, Guangyu Sun, Weisheng Zhao
2016 C conf
Quantitative evaluation of reliability and performance for STT-MRAM.
ISCAS
Liuyang Zhang, Aida Todri-Sanial, Wang Kang, Youguang Zhang, Lionel Torres, Yuanqing Cheng, Weisheng Zhao
2016 J jnl
Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jianlei Yang, Peiyuan Wang, Yaojun Zhang, Yuanqing Cheng, Weisheng Zhao, Yiran Chen, Hai (Helen) Li
2016 J jnl
Read disturbance issue and design techniques for nanoscale STT-MRAM.
J. Syst. Archit.
Yi Ran, Wang Kang, Youguang Zhang, Jacques-Olivier Klein, Weisheng Zhao
2016 J jnl
Skyrmion-Electronics: An Overview and Outlook.
Proc. IEEE
Wang Kang, Yangqi Huang, Xichao Zhang, Yan Zhou, Weisheng Zhao
2016 J jnl
Skyrmions as Compact, Robust and Energy-Efficient Interconnects for Domain Wall (DW)-based Systems.
CoRR
Wang Kang, Yangqi Huang, Xichao Zhang, Yan Zhou, Weifeng Lv, Weisheng Zhao
2016 C conf
Spin wave based synapse and neuron for ultra low power neuromorphic computation system.
ISCAS
Lang Zeng, Deming Zhang, Youguang Zhang, Fanghui Gong, Tianqi Gao, Sa Tu, Haiming Yu, Weisheng Zhao
2016 — conf
Stochastic spintronic device based synapses and spiking neurons for neuromorphic computation.
NANOARCH
Deming Zhang, Lang Zeng, Youguang Zhang, Weisheng Zhao, Jacques-Olivier Klein
2016 J jnl
Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM.
IEEE Trans. Reliab.
Bi Wu, Yuanqing Cheng, Jianlei Yang, Aida Todri-Sanial, Weisheng Zhao
2016 — conf
Ultra-low power all spin logic device acceleration based on voltage controlled magnetic anisotropy.
NANOARCH
Zhizhong Zhang, Yue Zhang, Lei Yue, Li Su, Yichuan Shi, Youguang Zhang, Weisheng Zhao
2015 — conf
A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback.
ACM Great Lakes Symposium on VLSI
Bonan Yan, Zheng Li, Yaojun Zhang, Jianlei Yang, Hai Li, Weisheng Zhao, Pierre Chor-Fung Chia
2015 C conf
A body-biasing of readout circuit for STT-RAM with improved thermal reliability.
ISCAS
Lun Yang, Yuanqing Cheng, Yuhao Wang, Hao Yu, Weisheng Zhao, Aida Todri-Sanial
2015 C conf
A new self-reference sensing scheme for TLC MRAM.
ISCAS
Zheng Li, Bonan Yan, Lun Yang, Weisheng Zhao, Yiran Chen, Hai Li
2015 — conf
An architecture-level cache simulation framework supporting advanced PMA STT-MRAM.
NANOARCH
Bi Wu, Yuanqing Cheng, Ying Wang, Aida Todri-Sanial, Guangyu Sun, Lionel Torres, Weisheng Zhao
2015 — conf
Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM.
ISVLSI
Liuyang Zhang, Wang Kang, Youguang Zhang, Yuanqing Cheng, Lang Zeng, Jacques-Olivier Klein, Weisheng Zhao
2015 J jnl
Compact thermal modeling of spin transfer torque magnetic tunnel junction.
Microelectron. Reliab.
You Wang, Hao Cai, Lirida A. B. Naviner, Yue Zhang, Jacques-Olivier Klein, Weisheng Zhao
2015 C conf
Energy-efficient neuromorphic computation based on compound spin synapse with stochastic learning.
ISCAS
Deming Zhang, Lang Zeng, Yuanzhuo Qu, Youguang Zhang, Mengxing Wang, Weisheng Zhao, Tianqi Tang, Yu Wang
2015 A conf
From device to system: cross-layer design exploration of racetrack memory.
DATE
Guangyu Sun, Chao Zhang, Hehe Li, Yue Zhang, Weiqi Zhang, Yizi Gu, Yinan Sun, Jacques-Olivier Klein, Dafine Ravelosona, Yongpan Liu, Weisheng Zhao, Huazhong Yang
2015 — conf
Full-adder circuit design based on all-spin logic device.
NANOARCH
Qi An, Li Su, Jacques-Olivier Klein, Sébastien Le Beux, Ian O'Connor, Weisheng Zhao
2015 J jnl
Guest Editorial for Special Issue on Emerging Memory Technologies - Modeling, Design, and Applications for Multi-Scale Computing.
IEEE Trans. Multi Scale Comput. Syst.
Yiran Chen, Kiyoung Choi, Weisheng Zhao
2015 A* conf
Hi-fi playback: tolerating position errors in shift operations of racetrack memory.
ISCA
Chao Zhang, Guangyu Sun, Xian Zhang, Weiqi Zhang, Weisheng Zhao, Tao Wang, Yun Liang, Yongpan Liu, Yu Wang, Jiwu Shu
2015 — conf
Nonvolatile radiation hardened DICE latch.
NVMTS
Tingting Pang, Wang Kang, Yi Ran, Youguang Zhang, Weifeng Lv, Weisheng Zhao
2015 J jnl
On-Chip Universal Supervised Learning Methods for Neuro-Inspired Block of Memristive Nanodevices.
ACM J. Emerg. Technol. Comput. Syst.
Djaafar Chabi, Weisheng Zhao, Damien Querlioz, Jacques-Olivier Klein
2015 C conf
Perspectives of racetrack memory based on current-induced domain wall motion: From device to system.
ISCAS
Yue Zhang, Chao Zhang, Jacques-Olivier Klein, Dafine Ravelosona, Guangyu Sun, Weisheng Zhao
2015 — conf
Quantitative modeling of racetrack memory, a tradeoff among area, performance, and power.
ASP-DAC
Chao Zhang, Guangyu Sun, Weiqi Zhang, Fan Mi, Hai Li, Weisheng Zhao
2015 — conf
Read disturbance issue for nanoscale STT-MRAM.
NVMSA
Yi Ran, Wang Kang, Youguang Zhang, Jacques-Olivier Klein, Weisheng Zhao
2015 — conf
Realization of neural coding by stochastic switching of magnetic tunnel junction.
NVMTS
Deming Zhang, Lang Zeng, Fanghui Gong, Tianqi Gao, Shaolong Gao, Youguang Zhang, Weisheng Zhao
2015 — conf
Recent progresses of STT memory design and applications.
ASICON
Bonan Yan, Yaojun Zhang, Enes Eken, Wujie Wen, Weisheng Zhao, Yiran Chen
2015 — conf
Robust magnetic full-adder with voltage sensing 2T/2MTJ cell.
NANOARCH
Erya Deng, You Wang, Zhaohao Wang, Jacques-Olivier Klein, Bernard Dieny, Guillaume Prenat, Weisheng Zhao
2015 — conf
Spin orbit torques for ultra-low power computing.
ASICON
Kaihua Cao, Heng Zhao, Mengxing Wang, Weisheng Zhao
2015 J jnl
Spin-Transfer Torque Magnetic Memory as a Stochastic Memristive Synapse for Neuromorphic Systems.
IEEE Trans. Biomed. Circuits Syst.
Adrien F. Vincent, Jerome Larroque, Nicolas Locatelli, Nesrine Ben Romdhane, Olivier Bichler, Christian Gamrat, Weisheng Zhao, Jacques-Olivier Klein, Sylvie Galdin-Retailleau, Damien Querlioz
2015 A conf
Spintronic devices as key elements for energy-efficient neuroinspired architectures.
DATE
Nicolas Locatelli, Adrien F. Vincent, Alice Mizrahi, Joseph S. Friedman, Damir Vodenicarevic, Joo-Von Kim, Jacques-Olivier Klein, Weisheng Zhao, Julie Grollier, Damien Querlioz
2015 J jnl
Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology.
ACM J. Emerg. Technol. Comput. Syst.
Wang Kang, Yue Zhang, Zhaohao Wang, Jacques-Olivier Klein, Claude Chappert, Dafine Ravelosona, Gefei Wang, Youguang Zhang, Weisheng Zhao
2015 — conf
Stochastic computation with Spin Torque Transfer Magnetic Tunnel Junction.
NEWCAS
Lirida Alves de Barros Naviner, Hao Cai, You Wang, Weisheng Zhao, Arwa Ben Dhia
2015 J jnl
Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction.
IEEE Trans. Circuits Syst. I Regul. Pap.
Erya Deng, Yue Zhang, Wang Kang, Bernard Dieny, Jacques-Olivier Klein, Guillaume Prenat, Weisheng Zhao
2015 J jnl
Tunnel Junction with Perpendicular Magnetic Anisotropy: Status and Challenges.
Micromachines
Mengxing Wang, Yue Zhang, Xiaoxuan Zhao, Weisheng Zhao
2015 C conf
Vortex-based spin transfer oscillator compact model for IC design.
ISCAS
Nicolas Locatelli, Damir Vodenicarevic, Weisheng Zhao, Jacques-Olivier Klein, Julie Grollier, Damien Querlioz
2015 J jnl
Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Wang Kang, Liuyang Zhang, Weisheng Zhao, Jacques-Olivier Klein, Youguang Zhang, Dafine Ravelosona, Claude Chappert
2014 — conf
An overview of spin-based integrated circuits.
ASP-DAC
Wang Kang, Weisheng Zhao, Zhaohao Wang, Jacques-Olivier Klein, Yue Zhang, Djaafar Chabi, Youguang Zhang, Dafine Ravelosona, Claude Chappert
2014 J jnl
Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses.
Microelectron. Reliab.
You Wang, Yue Zhang, Erya Deng, Jacques-Olivier Klein, Lirida A. B. Naviner, Weisheng Zhao
2014 — conf
Design and analysis of Racetrack memory based on magnetic domain wall motion in nanowires.
NANOARCH
Nesrine Ben Romdhane, Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Z. R. Wang, Dafine Ravelosona
2014 J jnl
Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells.
J. Parallel Distributed Comput.
Weisheng Zhao, Jean-Michel Portal, Wang Kang, Mathieu Moreau, Yue Zhang, Hassen Aziza, Jacques-Olivier Klein, Zhaohao Wang, Damien Querlioz, Damien Deleruyelle, Marc Bocquet, Dafine Ravelosona, Christophe Muller, Claude Chappert
2014 B conf
Ferroelectric tunnel memristor-based neuromorphic network with 1T1R crossbar architecture.
IJCNN
Zhaohao Wang, Weisheng Zhao, Wang Kang, Youguang Zhang, Jacques-Olivier Klein, Claude Chappert
2014 — conf
On-chip supervised learning rule for ultra high density neural crossbar using memristor for synapse and neuron.
NANOARCH
Djaafar Chabi, Zhaohao Wang, Weisheng Zhao, Jacques-Olivier Klein
2014 — conf
One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories.
NVMSA
Wang Kang, Weisheng Zhao, Lun Yang, Jacques-Olivier Klein, Youguang Zhang, Dafine Ravelosona
2014 J jnl
Robust learning approach for neuro-inspired nanoscale crossbar architecture.
ACM J. Emerg. Technol. Comput. Syst.
Djaafar Chabi, Damien Querlioz, Weisheng Zhao, Jacques-Olivier Klein
2014 C conf
Spin-transfer torque magnetic memory as a stochastic memristive synapse.
ISCAS
Adrien F. Vincent, Jerome Larroque, Weisheng Zhao, Nesrine Ben Romdhane, Olivier Bichler, Christian Gamrat, Jacques-Olivier Klein, Sylvie Galdin-Retailleau, Damien Querlioz
2014 A conf
Spintronics for low-power computing.
DATE
Yue Zhang, Weisheng Zhao, Jacques-Olivier Klein, Wang Kang, Damien Querlioz, Youguang Zhang, Dafine Ravelosona, Claude Chappert
2014 J jnl
Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories.
IEEE Trans. Circuits Syst. I Regul. Pap.
Weisheng Zhao, Mathieu Moreau, Erya Deng, Yue Zhang, Jean-Michel Portal, Jacques-Olivier Klein, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Damien Querlioz, Nesrine Ben Romdhane, Dafine Ravelosona, Claude Chappert
2014 J jnl
Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms.
IEEE Trans. Circuits Syst. I Regul. Pap.
Djaafar Chabi, Weisheng Zhao, Erya Deng, Yue Zhang, Nesrine Ben Romdhane, Jacques-Olivier Klein, Claude Chappert
2013 J jnl
A low-cost built-in error correction circuit design for STT-MRAM reliability improvement.
Microelectron. Reliab.
Wang Kang, Weisheng Zhao, Zhaohao Wang, Yue Zhang, Jacques-Olivier Klein, Youguang Zhang, Claude Chappert, Dafine Ravelosona
2013 — conf
Analytical study of complementary memristive synchronous logic gates.
NANOARCH
Jean-Michel Portal, Mathieu Moreau, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller, Yue Zhang, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao
2013 — conf
Emerging hybrid logic circuits based on non-volatile magnetic memories.
NEWCAS
Weisheng Zhao, Guillaume Prenat, Jacques-Olivier Klein, Bernard Dieny, Claude Chappert, Dafine Ravelosona
2013 — conf
Low power magnetic flip-flop based on checkpointing and self-enable mechanism.
NEWCAS
Djaafar Chabi, Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Claude Chappert
2013 J jnl
Magnetic Adder Based on Racetrack Memory.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hong-Phuc Trinh, Weisheng Zhao, Jacques-Olivier Klein, Yue Zhang, Dafine Ravelosona, Claude Chappert
2013 C conf
Spin-electronics based logic fabrics.
VLSI-SoC
Weisheng Zhao, Jacques-Olivier Klein, Zhaohao Wang, Yue Zhang, Nesrine Ben Romdhane, Damien Querlioz, Dafine Ravelosona, Claude Chappert
2013 — conf
Synchronous full-adder based on complementary resistive switching memory cells.
NEWCAS
Yue Zhang, Erya Deng, Jacques-Olivier Klein, Damien Querlioz, Dafine Ravelosona, Claude Chappert, Weisheng Zhao, Mathieu Moreau, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller
2012 — conf
Bioinspired networks with nanoscale memristive devices that combine the unsupervised and supervised learning approaches.
NANOARCH
Damien Querlioz, Weisheng Zhao, Philippe Dollfus, Jacques-Olivier Klein, Olivier Bichler, Christian Gamrat
2012 J jnl
Cross-point architecture for spin transfer torque magnetic random access memory
CoRR
Weisheng Zhao, Sumanta Chaudhuri, Celso Accoto, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer
2012 — conf
Crossbar architecture based on 2R complementary resistive switching memory cell.
NANOARCH
Weisheng Zhao, Yue Zhang, Jacques-Olivier Klein, Damien Querlioz, Djaafar Chabi, Dafine Ravelosona, Claude Chappert, Jean-Michel Portal, Marc Bocquet, Hassen Aziza, Damien Deleruyelle, Christophe Muller
2012 J jnl
Failure and reliability analysis of STT-MRAM.
Microelectron. Reliab.
Weisheng Zhao, Yue Zhang, Thibaut Devolder, Jacques-Olivier Klein, Dafine Ravelosona, Claude Chappert, Pascale Mazoyer
2012 C conf
MRAM crossbar based configurable logic block.
ISCAS
Yahya Lakys, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert
2012 C conf
Nanodevice-based novel computing paradigms and the neuromorphic approach.
ISCAS
Weisheng Zhao, Damien Querlioz, Jacques-Olivier Klein, Djaafar Chabi, Claude Chappert
2011 J jnl
Design and Modeling of a Neuro-Inspired Learning Circuit Using Nanotube-Based Memory Devices.
IEEE Trans. Circuits Syst. I Regul. Pap.
Si-Yu Liao, Jean-Marie Retrouvey, Guillaume Agnus, Weisheng Zhao, Cristell Maneux, Sébastien Fregonese, Thomas Zimmer, Djaafar Chabi, Arianna Filoramo, Vincent Derycke, Christian Gamrat, Jacques-Olivier Klein
2011 J jnl
Design considerations and strategies for high-reliable STT-MRAM.
Microelectron. Reliab.
Weisheng Zhao, Thibaut Devolder, Yahya Lakys, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer
2011 — conf
Design of MRAM based logic circuits and its applications.
ACM Great Lakes Symposium on VLSI
Weisheng Zhao, Lionel Torres, Yoann Guillemenet, Luis Vitorio Cargnini, Yahya Lakys, Jacques-Olivier Klein, Dafine Ravelosona, Gilles Sassatelli, Claude Chappert
2011 C conf
Embedded MRAM for high-speed computing.
VLSI-SoC
Weisheng Zhao, Yue Zhang, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, D. Revelosona, Claude Chappert, Lionel Torres, Luis Vitorio Cargnini, Raphael Martins Brum, Yoann Guillemenet, Gilles Sassatelli
2011 — conf
High Performance SoC Design Using Magnetic Logic and Memory.
VLSI-SoC (Selected Papers)
Weisheng Zhao, Lionel Torres, Luis Vitorio Cargnini, Raphael Martins Brum, Yue Zhang, Yoann Guillemenet, Gilles Sassatelli, Yahya Lakys, Jacques-Olivier Klein, Daniel Etiemble, Dafine Ravelosona, Claude Chappert
2011 — conf
Magnetic Look-Up Table (MLUT) Featuring Radiation Hardness, High Performance and Low Power.
ARC
Yahya Lakys, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert
2011 — conf
Robust neural logic block (NLB) based on memristor crossbar array.
NANOARCH
Djaafar Chabi, Weisheng Zhao, Damien Querlioz, Jacques-Olivier Klein
2010 C conf
Carbon nanotube-based programmable devices for adaptive architectures.
ISCAS
Guillaume Agnus, Arianna Filoramo, Jean-Philippe Bourgoin, Vincent Derycke, Weisheng Zhao
2010 — conf
Design of embedded MRAM macros for memory-in-logic applications.
ACM Great Lakes Symposium on VLSI
Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer
2010 B conf
High Density Asynchronous LUT Based on Non-volatile MRAM Technology.
FPL
Sumanta Chaudhuri, Weisheng Zhao, Jacques-Olivier Klein, Claude Chappert, Pascale Mazoyer
2009 — conf
Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano/CMOS Circuit Design.
NanoNet
Weisheng Zhao, Guillaume Agnus, Vincent Derycke, Arianna Filoramo, Christian Gamrat, Jean-Philippe Bourgoin