Weiguang Sheng

45 papers A* 2A 6B 1C 4Journal 14Unranked 18

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	TPDA-DRAM: A Variation-Aware DRAM Improving System Performance via In-Situ Timing Margin Detection and Adaptive Mitigation. IEEE Trans. Computers Yuxuan Qin, Chuxiong Lin, Guoming Rao, Ling Yang, Weiguang Sheng, Weifeng He
2026	—	`conf`	Viper: An ILP-Based Vectorization Framework for Fully Homomorphic Encryption. ASP-DAC Weidong Yang, Xinmo Li, Xiangmin Guo, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng
2025	J	`jnl`	A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip. IEEE Trans. Very Large Scale Integr. Syst. Zizheng Dong, Shuaipeng Li, Weijia Zhu, Ang Li, Qin Wang, Naifeng Jing, Weiguang Sheng, Jianfei Jiang, Zhigang Mao
2025	A	`conf`	HEILP: An ILP-Based Scale Management Method for Homomorphic Encryption Compiler. DATE Weidong Yang, Shuya Ji, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng
2025	J	`jnl`	IPDR: An Inter-Chiplet Priority-Driven Deadlock Resolution for 2-D/2.5-D Multichiplet Systems. IEEE Trans. Very Large Scale Integr. Syst. Jinming Zhang, Zhihong Chen, Yaoyao Ye, Hao Chen, Xiao Han, Jianfei Jiang, Weiguang Sheng, Ningyi Xu, Yong Lian, Guanghui He
2025	A*	`conf`	Principle-based Dataflow Optimization for Communication Lower Bound in Operator-Fused Tensor Accelerator. DAC Lei Xu, Chen Yin, Zelong Yuan, Weiguang Sheng, Jianfei Jiang, Qin Wang, Naifeng Jing
2024	C	`conf`	A Flexible and High-Precision Activation Function Unit Based on Equi-Error Partitioning Algorithm. ISCAS Zelong Yuan, Siwei Yuan, Pengyu Liu, Chen Yin, Lei Xu, Weiguang Sheng, Naifeng Jing
2024	J	`jnl`	RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Weidong Yang, Yuqing Yang, Shuya Ji, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao, Weiguang Sheng
2024	—	`conf`	VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet Networks. ACM Great Lakes Symposium on VLSI Duo Yu, Ang Li, Naifeng Jing, Jianfei Jiang, Weiguang Sheng, Qin Wang
2023	C	`conf`	ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors. ICCD Shuya Ji, Weidong Yang, Jianfei Jiang, Naifeng Jing, Weiguang Sheng, Ang Li, Qin Wang
2023	—	`conf`	An Efficient near-Bank Processing Architecture for Personalized Recommendation System. ASP-DAC Yuqing Yang, Weidong Yang, Qin Wang, Naifeng Jing, Jianfei Jiang, Zhigang Mao, Weiguang Sheng
2023	—	`conf`	RTMDet-R2: An Improved Real-Time Rotated Object Detector. PRCV (12) Haifeng Xiang, Naifeng Jing, Jianfei Jiang, Hongbo Guo, Weiguang Sheng, Zhigang Mao, Qin Wang
2023	—	`conf`	ReMap: Reorder Mapping for Multi-level Uneven Distribution on Sparse ReRAM Accelerator. ASICON Zhuo Chen, Zihan Zhang, Jianfei Jiang, Weiguang Sheng, Qin Wang, Naifeng Jing
2022	J	`jnl`	A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images. IEEE Geosci. Remote. Sens. Lett. Guochao Deng, Qin Wang, Jianfei Jiang, Qirun Hong, Naifeng Jing, Weiguang Sheng, Zhigang Mao
2022	J	`jnl`	An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Shengzhao Li, Qin Wang, Jianfei Jiang, Weiguang Sheng, Naifeng Jing, Zhigang Mao
2021	J	`jnl`	A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing. IEEE Trans. Very Large Scale Integr. Syst. Zhuojun Liang, Dongxu Lv, Chao Cui, Hai-Bao Chen, Weifeng He, Weiguang Sheng, Naifeng Jing, Zhigang Mao, Guanghui He
2021	—	`conf`	A Mapping Method for Reconfigurable Array based on Decoupled DataFlow. BigDataSecurity Zihan Zhang, Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao, Naifeng Jing
2021	A	`conf`	Reducing Memory Access Conflicts with Loop Transformation and Data Reuse on Coarse-grained Reconfigurable Architecture. DATE Yuge Chen, Zhongyuan Zhao, Jianfei Jiang, Guanghui He, Zhigang Mao, Weiguang Sheng
2021	A	`conf`	Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture. DATE Chen Yin, Qin Wang, Jianfei Jiang, Weiguang Sheng, Guanghui He, Zhigang Mao, Naifeng Jing
2020	—	`conf`	Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration. ACM Great Lakes Symposium on VLSI Zihan Zhang, Taozhong Li, Ning Guan, Qin Wang, Guanghui He, Weiguang Sheng, Zhigang Mao, Naifeng Jing
2020	J	`jnl`	Priority Branches for Ship Detection in Optical Remote Sensing Images. Remote. Sens. Yijia Zhang, Weiguang Sheng, Jianfei Jiang, Naifeng Jing, Qin Wang, Zhigang Mao
2020	J	`jnl`	Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling. IEEE Trans. Parallel Distributed Syst. Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Wenzhi Yin, Pengfei Ye, Jinchao Li, Zhigang Mao
2019	J	`jnl`	A New Cellular-Based Redundant TSV Structure for Clustered Faults. IEEE Trans. Very Large Scale Integr. Syst. Qin Wang, Zechen Liu, Jianfei Jiang, Naifeng Jing, Weiguang Sheng
2019	J	`jnl`	Lung Nodule Detection in CT Images Using a Raw Patch-Based Convolutional Neural Network. J. Digit. Imaging Qin Wang, Fengyi Shen, Linyao Shen, Jia Huang, Weiguang Sheng
2019	B	`conf`	mRNA: Enabling Efficient Mapping Space Exploration for a Reconfiguration Neural Accelerator. ISPASS Zhongyuan Zhao, Hyoukjun Kwon, Sachit Kuhar, Weiguang Sheng, Zhigang Mao, Tushar Krishna
2018	A	`conf`	Fail-Slow at Scale: Evidence of Hardware Performance Faults in Large Production Systems. FAST Haryadi S. Gunawi, Riza O. Suminto, Russell Sears, Casey Golliher, Swaminathan Sundararaman, Xing Lin, Tim Emami, Weiguang Sheng, Nematollah Bidokhti, Caitie McCaffrey, Gary Grider, Parks M. Fields, Kevin Harms, Robert B. Ross, Andree Jacobson, Robert Ricci, Kirk Webb, Peter Alvaro, H. Birali Runesha, Mingzhe Hao, Huaicheng Li
2018	J	`jnl`	Fail-Slow at Scale: Evidence of Hardware Performance Faults in Large Production Systems. ACM Trans. Storage Haryadi S. Gunawi, Riza O. Suminto, Russell Sears, Casey Golliher, Swaminathan Sundararaman, Xing Lin, Tim Emami, Weiguang Sheng, Nematollah Bidokhti, Caitie McCaffrey, Deepthi Srinivasan, Biswaranjan Panda, Andrew Baptist, Gary Grider, Parks M. Fields, Kevin Harms, Robert B. Ross, Andree Jacobson, Robert Ricci, Kirk Webb, Peter Alvaro, H. Birali Runesha, Mingzhe Hao, Huaicheng Li
2018	—	`conf`	MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs. ReConFig Shuai Xie, Zhongyuan Zhao, Weiguang Sheng, Qin Wang, Zhigang Mao
2018	A	`conf`	Optimizing the data placement and transformation for multi-bank CGRA computing system. DATE Zhongyuan Zhao, Yantao Liu, Weiguang Sheng, Tushar Krishna, Qin Wang, Zhigang Mao
2017	A	`conf`	A static-placement, dynamic-issue framework for CGRA loop accelerator. DATE Zhongyuan Zhao, Weiguang Sheng, Weifeng He, Zhigang Mao, Zhaoshi Li
2016	J	`jnl`	Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects. J. Circuits Syst. Comput. Jianfei Jiang, Zhigang Mao, Weiguang Sheng, Qin Wang, Weifeng He
2016	J	`jnl`	Parallel SER analysis for combinational and sequential standard cell circuits. Microelectron. J. Weiguang Sheng, Jianfei Jiang, Zhigang Mao
2015	—	`conf`	A contactless testing methodology for pre-bond interposer. MWSCAS Jianfei Jiang, Weiguang Sheng, Qin Wang, Zhigang Mao
2015	—	`conf`	An automatic translation and parallelization system for general purpose reconfigurable processor. ASICON Fengshuo Tian, Weiguang Sheng, Weifeng He
2015	—	`conf`	Designing ARINC653 Partition Constrained Scheduling for Secure Real Time Embedded Avionics. CSCloud Xiang Tao, Yongxin Zhu, Yishu Mao, Han Song, Mengyun Liu, Xinyi Liu, Weiguang Sheng, Weiwei Shi
2015	C	`conf`	Parasitic Parameters Impacts Investigation on Soft Error Rate by a Circuit Level Framework. PRDC Weiguang Sheng, Zhongyuan Zhao, Zhigang Mao
2015	—	`conf`	Resource-saving compile flow for coarse-grained reconfigurable architectures. ReConFig Zhongyuan Zhao, Weiguang Sheng, Naifeng Jing, Weifeng He, Zhigang Mao
2013	—	`conf`	Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor. ASICON Haopeng Liu, Weiguang Sheng, Weifeng He, Zhigang Mao
2012	—	`conf`	Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm. IPDPS Workshops Weiguang Sheng, Weifeng He, Jianfei Jiang, Zhigang Mao
2011	—	`conf`	Automatic compilation flow for a coarse-grained reconfigurable processor. ASICON Hao Wang, Weiguang Sheng, Weifeng He
2011	—	`conf`	Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm. ASICON Yifan Zhou, Weiguang Sheng, Xie Liu, Weifeng He, Zhigang Mao
2009	A*	`conf`	Soft error optimization of standard cell circuits based on gate sizing and multi-objective genetic algorithm. DAC Weiguang Sheng, Liyi Xiao, Zhigang Mao
2008	—	`conf`	A novel soft error sensitivity characterization technique based on simulated fault injection and constrained association analysis. ICECS Weiguang Sheng, Liyi Xiao, Zhigang Mao
2008	—	`conf`	An Automated Fault Injection Technique Based on VHDL Syntax Analysis and Stratified Sampling. DELTA Weiguang Sheng, Liyi Xiao, Zhigang Mao
2008	C	`conf`	Versatile and Efficient Techniques for Speeding-Up Circuit Level Simulated Fault-Injection Campaigns. PRDC Weiguang Sheng, Liyi Xiao, Zhigang Mao