Weifeng He - RankMe

111 papers A* 4A 5B 1C 16Journal 52Unranked 33

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Heterogeneous CIM Architecture With Splittable Nonvolatile Computing-in-SRAM Cell Pairs Enabling Efficient On-Chip Neural Network Inference. IEEE Trans. Very Large Scale Integr. Syst. Dengfeng Wang, Liukai Xu, Yiming Chen, Weifeng He, Guanghui He, Xueqing Li, Yanan Sun
2026	J	`jnl`	DBP-CIM: Energy-Efficient 8T SRAM-Based Diagonal-Block Parallel Computing-in-Memory With Compact Data Layout for Arithmetic Operations. IEEE Trans. Very Large Scale Integr. Syst. Dengfeng Wang, Chengjun Chang, Weifeng He, Guanghui He, Yanan Sun
2026	J	`jnl`	Harmonia: Algorithm-Hardware Co-Design for Memory- and Compute-Efficient BFP-based LLM Inference. CoRR Xinyu Wang, Jieyu Li, Yanan Sun, Weifeng He
2026	J	`jnl`	TPDA-DRAM: A Variation-Aware DRAM Improving System Performance via In-Situ Timing Margin Detection and Adaptive Mitigation. IEEE Trans. Computers Yuxuan Qin, Chuxiong Lin, Guoming Rao, Ling Yang, Weiguang Sheng, Weifeng He
2026	J	`jnl`	Towards disordered pick-and-place of aero-engine blades: A vision-guided method based on stable diffusion model and oriented object detection. Eng. Appl. Artif. Intell. Yizhen Yin, Yu Cai, Xiaolong Wei, Weifeng He, Yuanhan Hou, Caizhi Li, Zhigao Wang, Qichun Hu, Senlin Zhu
2025	J	`jnl`	A 12-nm High-Density Energy-Efficient 1-Mb 2R2W Scratchpad With Local Blocks for Neural Network Applications. IEEE J. Solid State Circuits Hao Zhang, Weifeng He, Wim Dehaene
2025	J	`jnl`	A 394-TOPS/W Matched Filter With Charge-Domain Computing for GPS Signal Acquisition. IEEE J. Solid State Circuits Jieyu Li, Weifeng He, Bo Zhang, Chuxiong Lin, Liang Qi, Dingxuan Liu, Mingoo Seok
2025	—	`conf`	ASF-CRB: an Energy-Efficient Activity-Balanced Charge-Recycling Bus Architecture Based on Alternate Signal Flipping. ACM Great Lakes Symposium on VLSI Xiangyu Ran, Chuxiong Lin, Jieyu Li, Weifeng He
2025	J	`jnl`	An Efficient Multi-View Cross-Attention Accelerator for Vision-Centric 3D Perception in Autonomous Driving. IEEE Trans. Circuits Syst. I Regul. Pap. Dongxu Lyu, Zhenyu Li, Yansong Xu, Gang Wang, Wenjie Li, Yuzhou Chen, Liyan Chen, Weifeng He, Guanghui He
2025	J	`jnl`	An Ultraspeed Middle Voltage and Timing Analyzer With Near-SPICE Accuracy for Charge-Recycling Buses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiangyu Ran, Chuxiong Lin, Yuxuan Qin, Jieyu Li, Ling Yang, Weifeng He
2025	J	`jnl`	CRFF: A Static Contention-Free 23T Flip-Flop With Three Clock Load Transistors for Ultra-Low-Power Applications. IEEE J. Solid State Circuits Kun Su, Mingche Lai, Jieyu Li, Jingkun Duan, Shi Xu, Zhang Luo, Weifeng He
2025	J	`jnl`	Damage location and area measurement of aviation functional surface via neural radiance field and improved Yolov8 network. Artif. Intell. Rev. Qichun Hu, Haojun Xu, Xiaolong Wei, Yu Cai, Yizhen Yin, Junliang Chen, Weifeng He
2025	A*	`conf`	EPIC: Error PredIction and Correction for Power-Efficient Voltage Underscaling Multiply-Accumulate Unit. DAC Tongjing Wu, Xiaolu Hu, Tong Li, Siting Liu, Hui Wang, Weifeng He, Zhigang Mao, Honglan Jiang
2025	J	`jnl`	Explainable deep learning framework for residual stress monitoring in laser shock peening via acoustic emission. J. Ind. Inf. Integr. Rui Qin, Zhifen Zhang, James M. Griffin, Jie Wang, Guangrui Wen, Weifeng He, Xuefeng Chen, Jing Huang
2025	J	`jnl`	HyCTor: A Hybrid CNN-Transformer Network Accelerator With Flexible Weight/Output Stationary Dataflow and Multicore Extension. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shuai Yuan, Weifeng He, Zhenhua Zhu, Fangxin Liu, Zhuoran Song, Guohao Dai, Guanghui He, Yanan Sun
2025	J	`jnl`	Incorporating machine learning in shot peening and laser peening: A review and beyond. Adv. Eng. Informatics Rui Qin, Zhifen Zhang, James M. Griffin, Jing Huang, Guangrui Wen, Weifeng He, Xuefeng Chen
2025	J	`jnl`	Robust Monolithic 3D Carbon-Based Computing-in-SRAM With Variation-Aware Bit-Wise Data-Mapping for High-Performance and Integration Density. IEEE Trans. Circuits Syst. I Regul. Pap. Dengfeng Wang, Weifeng He, Qin Wang, Hailong Jiao, Yanan Sun
2025	—	`conf`	SparseTrim: A Neural Network Accelerator Featuring On-Chip Decompression of Fine-Grained Sparse Model with 10.1TOPS/W System Energy Efficiency. CICC Jieyu Li, Weifeng He, Boran Jiang, Xinyu Wang, Guanghui He, Dingxuan Liu, Mingoo Seok
2024	J	`jnl`	A Metastability Risk Prediction and Mitigation Technique for Clock-Domain Crossing With Single-Stage Synchronizer in Near-Threshold-Voltage Multivoltage/ Frequency-Domain Network-on-Chip. IEEE J. Solid State Circuits Chuxiong Lin, Weifeng He, Yanan Sun, Lin Shao, Bo Zhang, Jun Yang, Mingoo Seok
2024	J	`jnl`	A novel physically interpretable end-to-end network for stress monitoring in laser shock peening. Comput. Ind. Rui Qin, Zhifen Zhang, Jing Huang, Zhengyao Du, Xianwen Xiang, Jie Wang, Guangrui Wen, Weifeng He
2024	J	`jnl`	Aeroengine Blades Damage Detection and Measurement Based on Multimodality Fusion Learning. IEEE Trans. Instrum. Meas. Xin Wu, Xiaolong Wei, Haojun Xu, Yuanhan Hou, Caizhi Li, Yizhen Yin, Weifeng He, Liucheng Zhou
2024	J	`jnl`	Deciphering laser shock peening quality monitoring: Wavelet-driven network with interpretability. Adv. Eng. Informatics Rui Qin, Zhifen Zhang, Jing Huang, Zhengyao Du, Xizhang Chen, Yu Su, Guangrui Wen, Weifeng He, Xuefeng Chen
2024	J	`jnl`	Point cloud enhancement optimization and high-fidelity texture reconstruction methods for air material via fusion of 3D scanning and neural rendering. Expert Syst. Appl. Qichun Hu, Xiaolong Wei, Xin Zhou, Yizhen Yin, Haojun Xu, Weifeng He, Senlin Zhu
2024	A*	`conf`	Reducing DRAM Latency via In-situ Temperature- and Process-Variation-Aware Timing Detection and Adaption. DAC Yuxuan Qin, Chuxiong Lin, Mingche Lai, Zhang Luo, Shi Xu, Weifeng He
2024	J	`jnl`	Research on the Performance State Assessment of Aero-Engine Compressor Driven by Realistic Digital Aero-Engine Structure Model. IEEE Trans. Instrum. Meas. Xin Wu, Xiaolong Wei, Haojun Xu, Weifeng He, Liucheng Zhou, Yuanhan Hou, Yixuan Wang
2024	J	`jnl`	TICA: Timing Slack Inference and Clock Frequency Adaption Technique for a Deeply Pipelined Near-Threshold-Voltage Bitcoin Mining Core. IEEE J. Solid State Circuits Jieyu Li, Weifeng He, Bo Zhang, Guanghui He, Jing Jin, Jun Yang, Mingoo Seok
2023	J	`jnl`	A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hao Zhang, Weifeng He, Yanan Sun, Mingoo Seok
2023	C	`conf`	A Metastability Inference and Avoidance Technique for Near-Threshold-Voltage Network-on-Chip. ISCAS Lin Shao, Mingche Lai, Shi Xu, Chuxiong Lin, Weifeng He
2023	J	`jnl`	A Novel Approach for Surface Integrity Monitoring in High-Energy Nanosecond-Pulse Laser Shock Peening: Acoustic Emission and Hybrid-Attention CNN. IEEE Trans. Ind. Informatics Zhifen Zhang, Rui Qin, Geng Li, Zhengyao Du, Guangrui Wen, Weifeng He
2023	J	`jnl`	A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router. IEEE Trans. Circuits Syst. II Express Briefs Bingxi Pei, Shi Xu, Zhang Luo, Qin Wang, Mingche Lai, Weifeng He
2023	C	`conf`	An Area-Efficient Single-Phase-Clocked and Contention-Free Flip-Flop for Ultra-Low-Voltage Operations. ISCAS Xue Yuan, Kun Su, Jingyi He, Shi Xu, Jieyu Li, Weifeng He
2023	J	`jnl`	BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars. IEEE Trans. Circuits Syst. I Regul. Pap. Yanan Sun, Zhi Li, Weiyi Liu, Weifeng He, Qin Wang, Zhigang Mao
2023	—	`conf`	CCSA: A 394TOPS/W Mixed-Signal GPS Accelerator with Charge-Based Correlation Computing for Signal Acquisition. ISSCC Jieyu Li, Weifeng He, Bo Zhang, Liang Qi, Guanghui He, Mingoo Seok
2023	J	`jnl`	CDAR-DRAM: Enabling Runtime DRAM Performance and Energy Optimization via In-Situ Charge Detection and Adaptive Data Restoration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuxuan Qin, Chuxiong Lin, Weifeng He, Yanan Sun, Zhigang Mao, Mingoo Seok
2023	J	`jnl`	CREAM: Computing in ReRAM-Assisted Energy- and Area-Efficient SRAM for Reliable Neural Network Acceleration. IEEE Trans. Circuits Syst. I Regul. Pap. Yanan Sun, Dengfeng Wang, Liukai Xu, Yiming Chen, Zhi Li, Songyuan Liu, Weifeng He, Yongpan Liu, Huazhong Yang, Xueqing Li
2023	J	`jnl`	PointCNT: A One-Stage Point Cloud Registration Approach Based on Complex Network Theory. Remote. Sens. Xin Wu, Xiaolong Wei, Haojun Xu, Caizhi Li, Yuanhan Hou, Yizhen Yin, Weifeng He
2023	J	`jnl`	Surface stress monitoring of laser shock peening using AE time-scale texture image and multi-scale blueprint separable convolutional networks with attention mechanism. Expert Syst. Appl. Rui Qin, Zhifen Zhang, Jing Huang, Jie Wang, Zhengyao Du, Guangrui Wen, Weifeng He
2023	A	`conf`	TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC Operations. ICCAD Dengfeng Wang, Liukai Xu, Songyuan Liu, Zhi Li, Yiming Chen, Weifeng He, Xueqing Li, Yanan Sun
2023	J	`jnl`	TL-nvSRAM-CIM: Ultra-High-Density Three-Level ReRAM-Assisted Computing-in-nvSRAM with DC-Power Free Restore and Ternary MAC Operations. CoRR Dengfeng Wang, Liukai Xu, Songyuan Liu, Zhi Li, Yiming Chen, Weifeng He, Xueqing Li, Yanan Sun
2022	—	`conf`	All-Digital Full-Precision In-SRAM Computing with Reduction Tree for Energy-Efficient MAC Operations. ICTA Dengfeng Wanq, Zhi Li, Chengjun Chang, Weifeng He, Yanan Sun
2022	A*	`conf`	CREAM: computing in ReRAM-assisted energy and area-efficient SRAM for neural network acceleration. DAC Liukai Xu, Songyuan Liu, Zhi Li, Dengfeng Wang, Yiming Chen, Yanan Sun, Xueqing Li, Weifeng He, Shi Xu
2022	—	`conf`	MPAM: Reliable, Low-Latency, Near-Threshold-Voltage Multi-Voltage/Frequency-Domain Network-on-Chip with Metastability Risk Prediction and Mitigation. CICC Chuxiong Lin, Weifeng He, Yannan Sun, Lin Shao, Bo Zhang, Jun Yang, Mingoo Seok
2022	J	`jnl`	MSLM-RF: A Spatial Feature Enhanced Random Forest for On-Board Hyperspectral Image Classification. IEEE Trans. Geosci. Remote. Sens. Shuai Yuan, Yanan Sun, Weifeng He, Qianrong Gu, Shi Xu, Zhigang Mao, Shikui Tu
2022	J	`jnl`	Online Evaluation of Surface Hardness for Aluminum Alloy in LSP Using Modal Acoustic Emission. IEEE Trans. Instrum. Meas. Zhifen Zhang, Rui Qin, Geng Li, Zimin Liu, Guangrui Wen, Weifeng He
2022	—	`conf`	TICA: A 0.3V, Variation-Resilient 64-Stage Deeply-Pipelined Bitcoin Mining Core with Timing Slack Inference and Clock Frequency Adaption. CICC Jieyu Li, Weifeng He, Bo Zhang, Guanghui He, Jun Yang, Mingoo Seok
2021	J	`jnl`	A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing. IEEE Trans. Very Large Scale Integr. Syst. Zhuojun Liang, Dongxu Lv, Chao Cui, Hai-Bao Chen, Weifeng He, Weiguang Sheng, Naifeng Jing, Zhigang Mao, Guanghui He
2021	—	`conf`	A Dual-rail Based Dynamic Voltage and Frequency Scaling for Wide-Voltage-Range Processor. ASICON Yongjie Lu, Weifeng He
2021	—	`conf`	A Ternary Memristive Logic-in-Memory Design for Fast Data Scan. ICTA Tianhong Shen, Yanan Sun, Weifeng He, Zhi Li, Weiyi Liu, Zhezhi He, Li Jiang
2021	A	`conf`	An Area-Efficient Scannable In Situ Timing Error Detection Technique Featuring Low Test Overhead for Resilient Circuits. ICCAD Hao Zhang, Weifeng He, Yanan Sun, Mingoo Seok
2021	C	`conf`	An Energy-Efficient Logic Cell Library Design Methodology with Fine Granularity of Driving Strength for Near- and Sub-Threshold Digital Circuits. ISCAS Hao Zhang, Weifeng He, Yanan Sun, Mingoo Seok
2021	C	`conf`	An Ultra-Low Leakage Bitcell Structure with the Feedforward Self-Suppression Scheme for Near-Threshold SRAM. ISCAS Hao Zhang, Jieyu Li, Weifeng He, Yanan Sun, Mingoo Seok
2021	A*	`conf`	CDAR-DRAM: An In-situ Charge Detection and Adaptive Data Restoration DRAM Architecture for Performance and Energy Efficiency Improvement. DAC Chuxiong Lin, Weifeng He, Yanan Sun, Zhigang Mao, Mingoo Seok
2021	C	`conf`	Design of Ternary Logic-in-Memory Based on Memristive Dual-Crossbars. ISCAS Weiyi Liu, Yanan Sun, Weifeng He, Qin Wang
2021	—	`conf`	Hierarchical Resource Allocation for RAN slicing in Power Wireless Private Network. ICSPCC Weijun Zheng, Weiping Shao, Weifeng He, Jian Zhang, Bin Hou, Yong Zhang
2021	C	`conf`	High Energy-Efficient LDPC Decoder with AVFS System for NAND Flash Memory. ISCAS Chao Zhang, Jingtong Mo, Zihan Lian, Weifeng He
2021	C	`conf`	Investigation of Dynamic Leakage-Suppression Logic Techniques Crossing Different Technology Nodes from 180 nm Bulk CMOS to 7 nm FinFET Plus Process. ISCAS Jieyu Li, Zihan Lian, Hao Zhang, Weifeng He, Yanan Sun, Mingoo Seok
2021	J	`jnl`	MEDAC: A Metastability Condition Detection and Correction Technique for a Near-Threshold-Voltage Multi-Voltage-/Frequency-Domain Network-on-Chip. IEEE J. Solid State Circuits Chuxiong Lin, Weifeng He, Yanan Sun, Bingxi Pei, Pavan Kumar Chundi, Zhigang Mao, Mingoo Seok
2020	—	`conf`	25.8 A Near- Threshold-Voltage Network-on-Chip with a Metastability Error Detection and Correction Technique for Supporting a Quad-Voltage/Frequency-Domain Ultra-Low-Power System-on-a-Chip. ISSCC Chuxiong Lin, Weifeng He, Yanan Sun, Bingxi Pei, Zhigang Mao, Mingoo Seok
2020	J	`jnl`	Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density. IEEE Trans. Circuits Syst. I Regul. Pap. Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
2020	J	`jnl`	Multi-Label Classification of Fundus Images With EfficientNet. IEEE Access Jing Wang, Liu Yang, Zhanqiang Huo, Weifeng He, Junwei Luo
2019	—	`conf`	A Femto/Pico-Watt Feedforward Leakage Self-Suppression Logic Family in 180 nm to 28 nm Technologies. MWSCAS Joao Pedro Cerqueira, Jieyu Li, Jiangyi Li, Weifeng He, Mingoo Seok
2019	—	`conf`	A New Approximate Multiplier Design for Digital Signal Processing. ASICON Yue Zhao, Tong Li, Feng Dong, Qin Wang, Weifeng He, Jianfei Jiang
2019	—	`conf`	A Novel Memristor-Reusable Mapping Methodology of In-memory Logic Implementation for High Area-Efficiency. NANOARCH Yongjie Lu, Yanan Sun, Weifeng He, Zhigang Mao
2019	—	`conf`	Carbon-Based Three-Dimensional SRAM Cell with Minimum Inter-Layer Area Skew Considering Process imperfections. ASICON Jiachen Jiang, Yanan Sun, Weifeng He, Zhigang Mao, Volkan Kursun
2019	J	`jnl`	Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells. IEEE Trans. Circuits Syst. II Express Briefs Yanan Sun, Jiawei Gu, Weifeng He, Qin Wang, Naifeng Jing, Zhigang Mao, Weikang Qian, Li Jiang
2019	—	`conf`	Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes. ICEIC Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
2018	C	`conf`	Electronic-Photonic Integrated Circuit Design and Crosstalk Modeling for a High Density Multi-Lane MZM Array. ISCAS Pengfei Ji, Jing Gao, Wenyi Xu, Yanan Sun, Weifeng He, Hui Wu
2017	C	`conf`	A 0.2V 2.3pJ/Cycle 28dB output SNR hybrid Markov random field probabilistic-based circuit for noise immunity and energy efficiency. ISCAS Xuwei Jin, Wei Jin, Hao Zhang, Jianfei Jiang, Weifeng He
2017	J	`jnl`	A 0.33 V 2.5 μW cross-point data-aware write structure, read-half-select disturb-free sub-threshold SRAM in 130 nm CMOS. Integr. Wei Jin, Weifeng He, Jianfei Jiang, Haichao Huang, Xuejun Zhao, Yanan Sun, Xin Chen, Naifeng Jing
2017	J	`jnl`	A 12-bit 4928 × 3264 pixel CMOS image signal processor for digital still cameras. Integr. Wei Jin, Guanghui He, Weifeng He, Zhigang Mao
2017	C	`conf`	A hardware-friendly hierarchical HEVC motion estimation algorithm for UHD applications. ISCAS Li Hu, Jiawei Gu, Guanghui He, Weifeng He
2017	A	`conf`	A static-placement, dynamic-issue framework for CGRA loop accelerator. DATE Zhongyuan Zhao, Weiguang Sheng, Weifeng He, Zhigang Mao, Zhaoshi Li
2017	J	`jnl`	In Situ Error Detection Techniques in Ultralow Voltage Pipelines: Analysis and Optimizations. IEEE Trans. Very Large Scale Integr. Syst. Wei Jin, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok
2017	—	`conf`	Low-power single-phase clocked redundant-transition-free flip-flop design with conditional charging scheme. ASICON Ling Chen, Yanan Sun, Weifeng He
2017	—	`conf`	Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors. ASICON Yanan Sun, Weifeng He, Zhigang Mao, Hailong Jiao, Volkan Kursun
2017	J	`jnl`	Near- and Sub-V IEEE J. Solid State Circuits Wei Jin, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok
2017	—	`conf`	Short path padding with multiple-Vt cells for wide-pulsed-latch based circuits at ultra-low voltage. ASICON Yongming Ding, Wei Jin, Guanghui He, Weifeng He
2017	J	`jnl`	Variable strength keeper for high-speed and low-leakage carbon nanotube domino logic. Microelectron. J. Yanan Sun, Weifeng He, Zhigang Mao, Volkan Kursun
2016	—	`conf`	A 0.35V 1.3pJ/cycle 20MHz 8-bit 8-tap FIR core based on wide-pulsed-latch pipelines. A-SSCC Wei Jin, Seongjong Kim, Weifeng He, Zhigang Mao, Mingoo Seok
2016	J	`jnl`	Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects. J. Circuits Syst. Comput. Jianfei Jiang, Zhigang Mao, Weiguang Sheng, Qin Wang, Weifeng He
2016	—	`conf`	Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory. FPT Naifeng Jing, Taozhong Li, Zhongyuan Zhao, Wei Jin, Yanan Sun, Weifeng He, Zhigang Mao
2016	J	`jnl`	High performance parallel turbo decoder with configurable interleaving network for LTE application. Integr. Zhiting Yan, Guanghui He, Weifeng He, Shuaijie Wang, Zhigang Mao
2015	—	`conf`	An automatic translation and parallelization system for general purpose reconfigurable processor. ASICON Fengshuo Tian, Weiguang Sheng, Weifeng He
2015	J	`jnl`	Design and Implementation of Flexible Dual-Mode Soft-Output MIMO Detector With Channel Preprocessing. IEEE Trans. Circuits Syst. I Regul. Pap. Zhiting Yan, Guanghui He, Yifan Ren, Weifeng He, Jianfei Jiang, Zhigang Mao
2015	J	`jnl`	Design optimization for capacitive-resistively driven on-chip global interconnect. IEICE Electron. Express Jianfei Jiang, Weifeng He, Jizeng Wei, Qin Wang, Zhigang Mao
2015	J	`jnl`	Improved Iterative Receiver for Co-channel Interference Suppression in MIMO-OFDM Systems. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Zhiting Yan, Guanghui He, Weifeng He, Zhigang Mao
2015	—	`conf`	Improved pipeline data flow for DySER-based platform. ISQED Zijian Hou, Xin Chen, Weifeng He
2015	A	`conf`	Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAs. ICCAD Naifeng Jing, Jiacheng Zhou, Jianfei Jiang, Xin Chen, Weifeng He, Zhigang Mao
2015	—	`conf`	Resource-saving compile flow for coarse-grained reconfigurable architectures. ReConFig Zhongyuan Zhao, Weiguang Sheng, Naifeng Jing, Weifeng He, Zhigang Mao
2014	C	`conf`	Area and throughput efficient IDCT/IDST architecture for HEVC standard. ISCAS Ziyou Yao, Weifeng He, Liang Hong, Guanghui He, Zhigang Mao
2014	J	`jnl`	Improved Max-Log-MAP BICM-IDD receiver for MIMO systems. IEICE Electron. Express Zhiting Yan, Guanghui He, Xi Chen, Weifeng He, Zhigang Mao
2013	—	`conf`	A cost effective 2-D adaptive block size IDCT architecture for HEVC standard. MWSCAS Liang Hong, Weifeng He, Hui Zhu, Zhigang Mao
2013	J	`jnl`	A full-pipelined 2-D IDCT/IDST VLSI architecture with adaptive block-size for HEVC standard. IEICE Electron. Express Liang Hong, Weifeng He, Hui Zhu, Zhigang Mao
2013	—	`conf`	Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor. ASICON Haopeng Liu, Weiguang Sheng, Weifeng He, Zhigang Mao
2012	—	`conf`	Contention and energy aware mapping for real-time applications on Network-on-Chip. ISOCC Bingjing Ge, Naifeng Jing, Weifeng He, Zhigang Mao
2012	—	`conf`	Group-Based Fast Mode Decision Algorithm for Intra Prediction in HEVC. SITIS Shunqing Yan, Liang Hong, Weifeng He, Qin Wang
2012	—	`conf`	Pareto Optimal Temporal Partition Methodology for Reconfigurable Architectures Based on Multi-objective Genetic Algorithm. IPDPS Workshops Weiguang Sheng, Weifeng He, Jianfei Jiang, Zhigang Mao
2012	J	`jnl`	SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms. ACM Trans. Design Autom. Electr. Syst. Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Lei He
2011	C	`conf`	A 230mV 8-bit sub-threshold microprocessor for wireless sensor network. VLSI-SoC Wei Jin, Sheng Lu, Weifeng He, Zhigang Mao
2011	C	`conf`	A general statistical estimation for application mapping in Network-on-Chip. VLSI-SoC Naifeng Jing, Weifeng He, Zhigang Mao
2011	C	`conf`	A thermal-aware task mapping flow for coarse-grain dynamic reconfigurable processor. ISCAS Li Xie, Weifeng He, Naifeng Jing, Zhigang Mao
2011	—	`conf`	Automatic compilation flow for a coarse-grained reconfigurable processor. ASICON Hao Wang, Weiguang Sheng, Weifeng He
2011	C	`conf`	Effective multi-standard macroblock prediction VLSI design for reconfigurable multimedia systems. ISCAS Yuliang Tao, Guanghui He, Weifeng He, Qin Wang, Jun Ma, Zhigang Mao
2011	—	`conf`	Efficient temporal task partition for coarse-grain reconfigurable systems based on Simulated Annealing Genetic Algorithm. ASICON Yifan Zhou, Weiguang Sheng, Xie Liu, Weifeng He, Zhigang Mao
2011	A	`conf`	Mitigating FPGA interconnect soft errors by in-place LUT inversion. ICCAD Naifeng Jing, Ju-Yueh Lee, Weifeng He, Zhigang Mao, Lei He
2011	B	`conf`	Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms. FPL Naifeng Jing, Ju-Yueh Lee, Zhe Feng, Weifeng He, Zhigang Mao, Shi-Jie Wen, Rick Wong, Lei He
2011	C	`conf`	Robust design of sub-threshold flip-flop cells for wireless sensor network. VLSI-SoC Wei Jin, Sheng Lu, Weifeng He, Zhigang Mao
2010	—	`conf`	An efficient VLSI architecture for extended variable block sizes motion estimation. SoCC Weifeng He, Weiwei Chen, Zhigang Mao
2010	—	`conf`	Resource constrained mapping of data flow graphs onto coarse-grained reconfigurable array. SoCC Naifeng Jing, Weifeng He, Zhigang Mao
2010	J	`jnl`	Statistical estimation and evaluation for communication mapping in Network-on-Chip. Integr. Naifeng Jing, Weifeng He, Yongxin Zhu, Zhigang Mao
2005	—	`conf`	Efficient frame-level pipelined array architecture for full-search block-matching motion estimation. ISCAS (3) Weifeng He, Yunlong Bi, Zhigang Mao