Wei Zhang

16 papers A* 1A 3B 1C 3Misc 1Journal 6Unranked 1
YearRankTypeTitle / Venue / Authors
2026 J jnl
FIITED: Fine-Grained Embedding Dimension Optimization During Training for Recommender Systems.
IEEE Trans. Computers
Qinyi Luo, Penghan Wang, Wei Zhang, Fan Lai, Jiachen Mao, Xiaohan Wei, Jun Song, Wei-Yu Tsai, Shuai Yang, Yuxi Hu, Xuehai Qian
2026 J jnl
PackInfer: Compute- and I/O-Efficient Attention for Batched LLM Inference.
CoRR
Rui Ning, Wei Zhang, Fan Lai
2025 J jnl
Tempo: Application-aware LLM Serving with Mixed SLO Requirements.
CoRR
Wei Zhang, Zhiyu Wu, Yi Mu, Banruo Liu, Myungjin Lee, Fan Lai
2024 J jnl
Fine-Grained Embedding Dimension Optimization During Training for Recommender Systems.
CoRR
Qinyi Luo, Penghan Wang, Wei Zhang, Fan Lai, Jiachen Mao, Xiaohan Wei, Jun Song, Wei-Yu Tsai, Shuai Yang, Yuxi Hu, Xuehai Qian
2023 A* conf
AdaEmbed: Adaptive Embedding for Large-Scale Recommendation Models.
OSDI
Fan Lai, Wei Zhang, Rui Liu, William Tsai, Xiaohan Wei, Yuxi Hu, Sabin Devkota, Jianyu Huang, Jongsoo Park, Xing Liu, ZeLiang Chen, Ellie Wen, Paul Rivera, Jie You, Chun-cheng Jason Chen, Mosharaf Chowdhury
2021 J jnl
Extending Performance-Energy Trade-offs Via Dynamic Core Scaling.
IEEE Trans. Computers
Wei Zhang, Hang Zhang, John C. Lach
2015 C conf
Dynamic core scaling: Trading off performance and energy beyond DVFS.
ICCD
Wei Zhang, Hang Zhang, John C. Lach
2015 A conf
Reducing dynamic energy of set-associative L1 instruction cache by early tag lookup.
ISLPED
Wei Zhang, Hang Zhang, John C. Lach
2014 C conf
A low-power accuracy-configurable floating point multiplier.
ICCD
Hang Zhang, Wei Zhang, John C. Lach
2014 A conf
Adaptive front-end throttling for superscalar processors.
ISLPED
Wei Zhang, Hang Zhang, John C. Lach
2013 A conf
Sensing nanosecond-scale voltage attacks and natural transients in FPGAs.
FPGA
Kenneth M. Zick, Meeta Srivastav, Wei Zhang, Matthew French
2011 — conf
A hardware-based computational platform for Generalized Laguerre-Volterra MIMO model for neural activities.
EMBC
Will X. Y. Li, Rosa H. M. Chan, Wei Zhang, Ray C. C. Cheung, Dong Song, Theodore W. Berger
2011 B conf
FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Activities.
FPL
Will X. Y. Li, Rosa H. M. Chan, Wei Zhang, C. W. Yu, Ray C. C. Cheung, Dong Song, Theodore W. Berger
2011 Misc conf
FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Spiking Activities.
FCCM
Will X. Y. Li, Ray C. C. Cheung, Wei Zhang, Rosa H. M. Chan, Dong Song, Theodore W. Berger
2011 J jnl
High-Performance and Scalable System Architecture for the Real-Time Estimation of Generalized Laguerre-Volterra MIMO Model From Neural Population Spiking Activity.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Will X. Y. Li, Rosa H. M. Chan, Wei Zhang, Ray C. C. Cheung, Dong Song, Theodore W. Berger
2011 C conf
Rapid single-chip secure processor prototyping on the OpenSPARC FPGA platform.
International Symposium on Rapid System Prototyping
Jakub Szefer, Wei Zhang, Yu-Yuan Chen, David Champagne, King Chan, Will X. Y. Li, Ray C. C. Cheung, Ruby B. Lee