Wei Zhang

246 papers A* 19A 33B 17C 8Misc 7Journal 117Unranked 43
YearRankTypeTitle / Venue / Authors
2026 J jnl
AutoPDR: Circuit-Aware Solver Configuration Prediction for Hardware Model Checking.
CoRR
Guangyu Hu, Chen Chen, Xiaofeng Zhou, Jiaxi Zhang, Wei Zhang, Hongce Zhang
2026 J jnl
CEGraph: Cache-Efficient Management for Streaming Graph Processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fubing Mao, Zihan Xie, Longyu Nie, Yu Zhang, Haikun Liu, Xiaofei Liao, Hai Jin, Wei Zhang, Yapu Guo, Jingkang Liu
2026 — conf
DOME: A Domain-Orchestrated Multi-GPU Optical Network for Rack-Scale Systems.
ASP-DAC
Chongyi Yang, Peiyu Chen, Bohan Hu, Yinyi Liu, Wei Zhang, Jiang Xu
2026 A* conf
DRACO: A Hardware-Efficient Robot Rigid Body Dynamics Accelerator with Precision-Aware Quantization Framework.
HPCA
Xingyu Liu, Jiawei Liang, Yipu Zhang, Linfeng Du, Chaofang Ma, Hui Yu, Jiang Xu, Wei Zhang
2026 J jnl
ESFA: An Efficient Scalable FFT Design Framework on Versal AI Engine.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hao Yang, Linfeng Du, Shangkun Li, Wei Zhang
2026 — conf
EvolveGen : Algorithmic Level Hardware Model Checking Benchmark Generation through Reinforcement Learning.
TACAS (2)
Guangyu Hu, Xiaofeng Zhou, Wei Zhang, Hongce Zhang
2026 J jnl
EvolveGen: Algorithmic Level Hardware Model Checking Benchmark Generation through Reinforcement Learning.
CoRR
Guangyu Hu, Xiaofeng Zhou, Wei Zhang, Hongce Zhang
2026 J jnl
FPPS: An FPGA-Based Point Cloud Processing System.
CoRR
Xiaofeng Zhou, Linfeng Du, Hanwei Fan, Wei Zhang
2026 — conf
Full-Stack System Design and Prototyping for Fully Programmable Electronic-Photonic Neurocomputing.
ASP-DAC
Yinyi Liu, Peiyu Chen, Bohan Hu, Wei Zhang, Jiang Xu
2026 J jnl
Invariance on Manifolds: Understanding Robust Visual Representations for Place Recognition.
CoRR
Jintao Cheng, Weibin Li, Zhijian He, Jin Wu, Chi Man Vong, Wei Zhang
2026 J jnl
LeGend: A Data-Driven Framework for Lemma Generation in Hardware Model Checking.
CoRR
Mingkai Miao, Guangyu Hu, Wei Zhang, Hongce Zhang
2026 J jnl
Rhythm: Learning Interactive Whole-Body Control for Dual Humanoids.
CoRR
Hongjin Chen, Wei Zhang, Pengfei Li, Shihao Ma, Ke Ma, Yujie Jin, Zijun Xu, Xiaohui Wang, Yupeng Zheng, Zining Wang, Jieru Zhao, Yilun Chen, Wenchao Ding
2026 J jnl
VLA-IAP: Training-Free Visual Token Pruning via Interaction Alignment for Vision-Language-Action Models.
CoRR
Jintao Cheng, Haozhe Wang, Weibin Li, Gang Wang, Yipu Zhang, Xiaoyu Tang, Jin Wu, Xieyuanli Chen, Yunhui Liu, Wei Zhang
2025 J jnl
A Pseudo Global Fusion Paradigm-Based Cross-View Network for LiDAR-Based Place Recognition.
CoRR
Jintao Cheng, Jiehao Luo, Xieyuanli Chen, Jin Wu, Rui Fan, Xiaoyu Tang, Wei Zhang
2025 J jnl
AM-Align: Globally Optimal Estimation of Accelerometer-Magnetometer Misalignment.
IEEE Trans. Instrum. Meas.
Xiangcheng Hu, Jin Wu, Bohuan Xue, Yilong Zhu, Mingkai Jia, Yuhua Qi, Yi Jiang, Ping Tan, Wei Zhang
2025 A conf
Automated Design Space Exploration in High-Level Physical Synthesis.
ICCAD
Linfeng Du, Jiawei Liang, Jason Lau, Yuze Chi, Yutong Xie, Chunyou Su, Afzal Ahmad, Zifan He, Jake Ke, Jinming Ge, Jason Cong, Wei Zhang, Licheng Guo
2025 J jnl
DAPO: Design Structure-Aware Pass Ordering in High-Level Synthesis with Graph Contrastive and Reinforcement Learning.
CoRR
Jinming Ge, Linfeng Du, Likith Anaparty, Shangkun Li, Tingyuan Liang, Afzal Ahmad, Vivek Chaturvedi, Sharad Sinha, Zhiyao Xie, Jiang Xu, Wei Zhang
2025 A* conf
Dual-AEB: Synergizing Rule-Based and Multimodal Large Language Models for Effective Emergency Braking.
ICRA
Wei Zhang, Pengfei Li, Junli Wang, Bingchuan Sun, Qihao Jin, Guangjun Bao, Shibo Rui, Yang Yu, Wenchao Ding, Peng Li, Yilun Chen
2025 J jnl
Exploring Rewriting Approaches for Different Conversational Tasks.
CoRR
Md. Mehrab Tanjim, Ryan A. Rossi, Mike Rimer, Xiang Chen, Sungchul Kim, Vaishnavi Muppala, Tong Yu, Zhengmian Hu, Ritwik Sinha, Wei Zhang, Iftikhar Ahamath Burhanuddin, Franck Dernoncourt
2025 B conf
FLEX: Leveraging FPGA-CPU Synergy for Mixed-Cell-Height Legalization Acceleration.
ICPP
Xingyu Liu, Jiawei Liang, Linfeng Du, Yipu Zhang, Chaofang Ma, Hanwei Fan, Jiang Xu, Wei Zhang
2025 J jnl
Fourier Transform Multiple Instance Learning for Whole Slide Image Classification.
CoRR
Anthony Bilic, Guangyu Sun, Ming Li, Md Sanzid Bin Hossain, Yu Tian, Wei Zhang, Laura Brattain, Dexter Hadley, Chen Chen
2025 J jnl
Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems.
CoRR
Benjamin Chen Ming Choong, Tao Luo, Cheng Liu, Bingsheng He, Wei Zhang, Joey Tianyi Zhou
2025 B conf
LLaMCAT: Optimizing Large Language Model Inference with Cache Arbitration and Throttling.
ICPP
Zhongchun Zhou, Chengtao Lai, Wei Zhang
2025 J jnl
MapEval: Towards Unified, Robust and Efficient SLAM Map Evaluation Framework.
IEEE Robotics Autom. Lett.
Xiangcheng Hu, Jin Wu, Mingkai Jia, Hongyu Yan, Yi Jiang, Binqian Jiang, Wei Zhang, Wei He, Ping Tan
2025 A* conf
Matrix Completion with Incomplete Side Information via Orthogonal Complement Projection.
ICML
Gengshuo Chang, Wei Zhang, Lehan Zhang
2025 J jnl
On Similarity Transformation Problems: Globally Optimal Results and Applications.
IEEE Trans. Instrum. Meas.
Jin Wu, Chaoqun Wang, Chong Li, Yi Jiang, Chengxi Zhang, Yulong Huang, Yuhua Qi, Bohuan Xue, Jianhao Jiao, Rui Fan, Wei Zhang
2025 J jnl
Scale, Don't Fine-tune: Guiding Multimodal LLMs for Efficient Visual Place Recognition at Test-Time.
CoRR
Jintao Cheng, Weibin Li, Jiehao Luo, Xiaoyu Tang, Zhijian He, Jin Wu, Yao Zou, Wei Zhang
2025 A conf
SpNeRF: Memory Efficient Sparse Volumetric Neural Rendering Accelerator for Edge Devices.
DATE
Yipu Zhang, Jiawei Liang, Jian Peng, Jiang Xu, Wei Zhang
2025 J jnl
SpNeRF: Memory Efficient Sparse Volumetric Neural Rendering Accelerator for Edge Devices.
CoRR
Yipu Zhang, Jiawei Liang, Jian Peng, Jiang Xu, Wei Zhang
2025 A conf
SpatialMe: Stereo Video Conversion Using Depth-Warping and Blend-Inpainting.
ICME
Jiale Zhang, Qianxi Jia, Yang Liu, Wei Zhang, Wei Wei, Xin Tian
2025 A conf
TAPCA: An Interface-Aware Cache Management Framework for Task Partitioning on CPU-FPGA SoC Platforms.
FPGA
Enlai Li, Zhe Lin, Sharad Sinha, Wei Zhang
2025 J jnl
UMD-Net: A Unified Multi-Task Assistive Driving Network Based on Multimodal Fusion.
IEEE Trans. Intell. Transp. Syst.
Wenzhuo Liu, Yicheng Qiao, Zhiwei Li, Wenshuo Wang, Wei Zhang, Jiayin Zhu, Yanhuan Jiang, Li Wang, Hong Wang, Huaping Liu, Kunfeng Wang
2024 A conf
A Modular Branch Predictor Performance Analysis Framework for Fast Design Space Exploration.
DATE
Ya Wang, Hanwei Fan, Sicheng Li, Tingyuan Liang, Wei Zhang
2024 J jnl
AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang
2024 A* conf
Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS.
DAC
Afzal Ahmad, Linfeng Du, Zhiyao Xie, Wei Zhang
2024 J jnl
Accel-NASBench: Sustainable Benchmarking for Accelerator-Aware NAS.
CoRR
Afzal Ahmad, Linfeng Du, Zhiyao Xie, Wei Zhang
2024 J jnl
Boosting the Convergence of Reinforcement Learning-Based Auto-Pruning Using Historical Data.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jiandong Mu, Mengdi Wang, Feiwen Zhu, Jun Yang, Wei Lin, Wei Zhang
2024 J jnl
Data-Pattern-Based Predictive On-Chip Power Meter in DNN Accelerator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jian Peng, Tingyuan Liang, Jingbo Jiang, Yipu Zhang, Zhe Lin, Zhiyao Xie, Wei Zhang
2024 J jnl
Deep Reinforcement Learning-Based Power Management for Chiplet-Based Multicore Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Xiao Li, Lin Chen, Shixi Chen, Fan Jiang, Chengeng Li, Wei Zhang, Jiang Xu
2024 B conf
DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction.
ASPDAC
Guangyu Hu, Jianheng Tang, Changyuan Yu, Wei Zhang, Hongce Zhang
2024 J jnl
Dual-AEB: Synergizing Rule-Based and Multimodal Large Language Models for Effective Emergency Braking.
CoRR
Wei Zhang, Pengfei Li, Junli Wang, Bingchuan Sun, Qihao Jin, Guangjun Bao, Shibo Rui, Yang Yu, Wenchao Ding, Peng Li, Yilun Chen
2024 A* conf
Explainable Fuzzy Neural Network with Multi-Fidelity Reinforcement Learning for Micro-Architecture Design Space Exploration.
DAC
Hanwei Fan, Ya Wang, Sicheng Li, Tingyuan Liang, Wei Zhang
2024 J jnl
Explainable Fuzzy Neural Network with Multi-Fidelity Reinforcement Learning for Micro-Architecture Design Space Exploration.
CoRR
Hanwei Fan, Ya Wang, Sicheng Li, Tingyuan Liang, Wei Zhang
2024 J jnl
FADO: Floorplan-Aware Directive Optimization Based on Synthesis and Analytical Models for High-Level Synthesis Designs on Multi-Die FPGAs.
ACM Trans. Reconfigurable Technol. Syst.
Linfeng Du, Tingyuan Liang, Xiaofeng Zhou, Jinming Ge, Shangkun Li, Sharad Sinha, Jieru Zhao, Zhiyao Xie, Wei Zhang
2024 A conf
GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network.
FPGA
Chunyou Su, Linfeng Du, Tingyuan Liang, Zhe Lin, Maolin Wang, Sharad Sinha, Wei Zhang
2024 A conf
LCM: LLM-focused Hybrid SPM-cache Architecture with Cache Management for Multi-Core AI Accelerators.
ICS
Chengtao Lai, Zhongchun Zhou, Akash Poptani, Wei Zhang
2024 J jnl
MS-Mapping: An Uncertainty-Aware Large-Scale Multi-Session LiDAR Mapping System.
CoRR
Xiangcheng Hu, Jin Wu, Jianhao Jiao, Binqian Jiang, Wei Zhang, Wenshuo Wang, Ping Tan
2024 J jnl
MS-Mapping: Multi-session LiDAR Mapping with Wasserstein-based Keyframe Selection.
CoRR
Xiangcheng Hu, Jin Wu, Jianhao Jiao, Wei Zhang, Ping Tan
2024 J jnl
MapEval: Towards Unified, Robust and Efficient SLAM Map Evaluation Framework.
CoRR
Xiangcheng Hu, Jin Wu, Mingkai Jia, Hongyu Yan, Yi Jiang, Binqian Jiang, Wei Zhang, Wei He, Ping Tan
2024 A conf
NEOCNN: NTT-Enabled Optical Convolution Neural Network Accelerator.
ICS
Xianbin Li, Yinyi Liu, Fan Jiang, Chengeng Li, Yuxiang Fu, Wei Zhang, Jiang Xu
2024 J jnl
Optimizing for In-Memory Deep Learning With Emerging Memory Technology.
IEEE Trans. Neural Networks Learn. Syst.
Zhehui Wang, Tao Luo, Rick Siow Mong Goh, Wei Zhang, Weng-Fai Wong
2024 B conf
PC-oriented Prediction-based Runtime Power Management for GPGPU using Knowledge Transfer.
SPAA
Lin Chen, Xiao Li, Shixi Chen, Fan Jiang, Chengeng Li, Wei Zhang, Jiang Xu
2024 J jnl
PMGraph: Accelerating Concurrent Graph Queries over Streaming Graphs.
ACM Trans. Archit. Code Optim.
Fubing Mao, Xu Liu, Yu Zhang, Haikun Liu, Xiaofei Liao, Hai Jin, Wei Zhang, Jian Zhou, Yufei Wu, Longyu Nie, Yapu Guo, Zihan Jiang, Jingkang Liu
2024 A conf
PhotonNTT: Energy-Efficient Parallel Photonic Number Theoretic Transform Accelerator.
DATE
Xianbin Li, Jiaqi Liu, Yuying Zhang, Yinyi Liu, Jiaxu Zhang, Chengeng Li, Shixi Chen, Yuxiang Fu, Fengshi Tian, Wei Zhang, Jiang Xu
2024 J jnl
Unveiling the Advantages of Full Coherency Architecture for FPSoC Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Enlai Li, Sharad Sinha, Wei Zhang
2024 J jnl
gem5-NVDLA: A Simulation Framework for Compiling, Scheduling, and Architecture Evaluation on AI System-on-Chips.
ACM Trans. Design Autom. Electr. Syst.
Chengtao Lai, Wei Zhang
2023 A* conf
ACGraph: Accelerating Streaming Graph Processing via Dependence Hierarchy.
DAC
Zihan Jiang, Fubing Mao, Yapu Guo, Xu Liu, Haikun Liu, Xiaofei Liao, Hai Jin, Wei Zhang
2023 J jnl
Accelerating Loop-Oriented RTL Simulation With Code Instrumentation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Fubing Mao, Yapu Guo, Xiaofei Liao, Hai Jin, Wei Zhang, Haikun Liu, Long Zheng, Xu Liu, Zihan Jiang, XiaoHua Zheng
2023 A conf
Cache Side-channel Attacks and Defenses of the Sliding Window Algorithm in TEEs.
DATE
Zili Kou, Sharad Sinha, Wenjian He, Wei Zhang
2023 J jnl
Design and Analysis of RSA and Paillier Homomorphic Cryptosystems Using PSO-Based Evolutionary Computation.
IEEE Trans. Computers
Sathi Sarveswara Reddy, Sharad Sinha, Wei Zhang
2023 — conf
DiffLo: A Graph-based Method for Functional Discrepancy Localization in High-level Synthesis.
ICFPT
Liangji Chen, Tingyuan Liang, Wei Zhang, Sharad Sinha
2023 A conf
FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs.
FPGA
Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang
2023 A conf
FIONA: Photonic-Electronic CoSimulation Framework and Transferable Prototyping for Photonic Accelerator.
ICCAD
Yinyi Liu, Bohan Hu, Zhenguo Liu, Peiyu Chen, Linfeng Du, Jiaqi Liu, Xianbin Li, Wei Zhang, Jiang Xu
2023 J jnl
HL-Pow: Learning-Assisted Pre-RTL Power Modeling and Optimization for FPGA HLS.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhe Lin, Tingyuan Liang, Jieru Zhao, Sharad Sinha, Wei Zhang
2023 J jnl
Introduction to the Special Issue on FPT 2021.
ACM Trans. Reconfigurable Technol. Syst.
Andreas Koch, Wei Zhang
2023 — conf
NeuroPDR: Integrating Neural Networks in the PDR Algorithm for Hardware Model Checking.
MLCAD
Guangyu Hu, Wei Zhang, Hongce Zhang
2023 A* conf
PROPHET: Predictive On-Chip Power Meter in Hardware Accelerator for DNN.
DAC
Jian Peng, Tingyuan Liang, Zhiyao Xie, Wei Zhang
2023 A* conf
PertNAS: Architectural Perturbations for Memory-Efficient Neural Architecture Search.
DAC
Afzal Ahmad, Zhiyao Xie, Wei Zhang
2023 J jnl
Special Issue: "AI Acceleration on FPGAs".
ACM Trans. Embed. Comput. Syst.
Yun Liang, Wei Zhang, Stephen Neuendorffer, Wayne Luk
2023 Misc conf
Tensor-Product-Based Accelerator for Area-efficient and Scalable Number Theoretic Transform.
FCCM
Yuying Zhang, Sathi Sarveswara Reddy, Zili Kou, Sharad Sinha, Wei Zhang
2022 J jnl
AMF-Placer 2.0: Open Source Timing-driven Analytical Mixed-size Placer for Large-scale Heterogeneous FPGA.
CoRR
Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang
2022 A conf
Attack Directories on ARM big.LITTLE Processors.
ICCAD
Zili Kou, Sharad Sinha, Wenjian He, Wei Zhang
2022 J jnl
AutoCellLibX: Automated Standard Cell Library Extension Based on Pattern Mining.
CoRR
Tingyuan Liang, Jingsong Chen, Lei Li, Wei Zhang
2022 — conf
Bayesian Optimization with Clustering and Rollback for CNN Auto Pruning.
ECCV (23)
Hanwei Fan, Jiandong Mu, Wei Zhang
2022 J jnl
FADO: Floorplan-Aware Directive Optimization for High-Level Synthesis Designs on Multi-Die FPGAs.
CoRR
Linfeng Du, Tingyuan Liang, Sharad Sinha, Zhiyao Xie, Wei Zhang
2022 J jnl
Hardware-software co-exploration with racetrack memory based in-memory computing for CNN inference in embedded systems.
J. Syst. Archit.
Benjamin Chen Ming Choong, Tao Luo, Cheng Liu, Bingsheng He, Wei Zhang, Joey Tianyi Zhou
2022 J jnl
Introduction to the Special Issue on Hardware-Assisted Security for Emerging Internet of Things.
ACM J. Emerg. Technol. Comput. Syst.
Saraju P. Mohanty, Jim Plusquellic, Garrett S. Rose, Wei Zhang, Maria K. Michael
2022 — conf
Message from the General Chair and Program Co-Chairs.
FPT
Wei Zhang, Ray C. C. Cheung, Yun Liang, Hiroki Nakahara
2022 A conf
PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs.
DATE
Zhe Lin, Zike Yuan, Jieru Zhao, Wei Zhang, Hui Wang, Yonghong Tian
2022 J jnl
PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs.
CoRR
Zhe Lin, Zike Yuan, Jieru Zhao, Wei Zhang, Hui Wang, Yonghong Tian
2022 — conf
Preface.
FPT
Yun Liang, Hiroki Nakahara, Wei Zhang, Fubing Mao, Ray C. C. Cheung
2021 A conf
AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA.
ICCAD
Tingyuan Liang, Gengjie Chen, Jieru Zhao, Sharad Sinha, Wei Zhang
2021 J jnl
Boosting the Convergence of Reinforcement Learning-based Auto-pruning Using Historical Data.
CoRR
Jiandong Mu, Mengdi Wang, Feiwen Zhu, Jun Yang, Wei Lin, Wei Zhang
2021 — conf
Concentration Gradients Enhancement of Christmas-Tree Structure Based on a Look-Up Table.
ACM Great Lakes Symposium on VLSI
Wei Zhang, Yongxiao Zhou, Tsung-Yi Ho, Hailong Yao
2021 J jnl
Fangorn: Adaptive Execution Framework for Heterogeneous Workloads on Shared Clusters.
Proc. VLDB Endow.
Yingda Chen, Jiamang Wang, Yifeng Lu, Ying Han, Zhiqiang Lv, Xuebin Min, Hua Cai, Wei Zhang, Haochuan Fan, Chao Li, Tao Guan, Wei Lin, Yangqing Jia, Jingren Zhou
2021 B conf
Graph Sampling with Fast Random Walker on HBM-enabled FPGA Accelerators.
FPL
Chunyou Su, Hao Liang, Wei Zhang, Kun Zhao, Baole Ai, Wenting Shen, Zeke Wang
2021 J jnl
Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhe Lin, Sharad Sinha, Wei Zhang
2021 J jnl
High-dimensional Bayesian Optimization for CNN Auto Pruning with Clustering and Rollback.
CoRR
Jiandong Mu, Hanwei Fan, Wei Zhang
2021 A* conf
Load-Step: A Precise TrustZone Execution Control Framework for Exploring New Side-channel Attacks Like Flush+Evict.
DAC
Zili Kou, Wenjian He, Sharad Sinha, Wei Zhang
2021 J jnl
Optimizing for In-memory Deep Learning with Emerging Memory Technology.
CoRR
Zhehui Wang, Tao Luo, Rick Siow Mong Goh, Wei Zhang, Weng-Fai Wong
2021 J jnl
TCL: Transformer-based Dynamic Graph Modelling via Contrastive Learning.
CoRR
Lu Wang, Xiaofu Chang, Shuang Li, Yunfei Chu, Hui Li, Wei Zhang, Xiaofeng He, Le Song, Jingren Zhou, Hongxia Yang
2020 A* conf
A History-Based Auto-Tuning Framework for Fast and High-Performance DNN Design on GPU.
DAC
Jiandong Mu, Mengdi Wang, Lanbo Li, Jun Yang, Wei Lin, Wei Zhang
2020 J jnl
An Ensemble Learning Approach for In-situ Monitoring of FPGA Dynamic Power.
CoRR
Zhe Lin, Sharad Sinha, Wei Zhang
2020 J jnl
BBB-CFI: Lightweight CFI Approach Against Code-Reuse Attacks Using Basic Block Information.
ACM Trans. Embed. Comput. Syst.
Wenjian He, Sanjeev Das, Wei Zhang, Yang Liu
2020 A conf
Boyi: A Systematic Framework for Automatically Deciding the Right Execution Model of OpenCL Applications on FPGAs.
FPGA
Jiantong Jiang, Zeke Wang, Xue Liu, Juan Gómez-Luna, Nan Guan, Qingxu Deng, Wei Zhang, Onur Mutlu
2020 J jnl
Decision Tree Based Hardware Power Monitoring for Run Time Dynamic Power Management in FPGA.
CoRR
Zhe Lin, Wei Zhang, Sharad Sinha
2020 J jnl
Development of a navigation performance evaluation system.
Sci. China Inf. Sci.
Fangfang Zhao, Wei Zhang, Shuzhi Sam Ge
2020 A conf
Energy Efficient In-memory Integer Multiplication Based on Racetrack Memory.
ICDCS
Tao Luo, Wei Zhang, Bingsheng He, Cheng Liu, Douglas L. Maskell
2020 J jnl
Energy Minimization for Multicore Platforms Through DVFS and VR Phase Scaling With Comprehensive Convex Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zuomin Zhu, Wei Zhang, Vivek Chaturvedi, Amit Kumar Singh
2020 B conf
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications.
FPL
Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen
2020 J jnl
FP-Stereo: Hardware-Efficient Stereo Vision for Embedded Applications.
CoRR
Jieru Zhao, Tingyuan Liang, Liang Feng, Wenchao Ding, Sharad Sinha, Wei Zhang, Shaojie Shen
2020 J jnl
Guest Editorial: ACM JETC Special Issue on New Trends in Nanolectronic Device, Circuit, and Architecture Design: Part 2.
ACM J. Emerg. Technol. Comput. Syst.
Wei Zhang, Hai Helen Li, Wujie Wen, Swarup Bhunia
2020 — conf
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis.
ASP-DAC
Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang
2020 J jnl
HL-Pow: A Learning-Based Power Modeling Framework for High-Level Synthesis.
CoRR
Zhe Lin, Jieru Zhao, Sharad Sinha, Wei Zhang
2020 J jnl
Hard-ODT: Hardware-Friendly Online Decision Tree Learning Algorithm and System.
CoRR
Zhe Lin, Sharad Sinha, Wei Zhang
2020 J jnl
Introduction to the Special Issue on New Trends in Nanoelectronic Device, Circuit, and Architecture Design, Part 1.
ACM J. Emerg. Technol. Comput. Syst.
Hai Helen Li, Wei Zhang, Swarup Bhunia, Wujie Wen
2020 — conf
NCPower: Power Modelling for NVM-based Neuromorphic Chip.
ICONS
Zhehui Wang, Huaipeng Zhang, Tao Luo, Weng-Fai Wong, Anh-Tuan Do, Paramasivam Vishnu, Wei Zhang, Rick Siow Mong Goh
2020 J jnl
Optimizing OpenCL-Based CNN Design on FPGA with Comprehensive Design Space Exploration and Collaborative Performance Modeling.
ACM Trans. Reconfigurable Technol. Syst.
Jiandong Mu, Wei Zhang, Hao Liang, Sharad Sinha
2020 J jnl
Performance Modeling and Directives Optimization for High-Level Synthesis on FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He
2020 J jnl
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors.
CoRR
Zhe Lin, Sharad Sinha, Hao Liang, Liang Feng, Wei Zhang
2020 J jnl
Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA.
CoRR
Zhe Lin, Sharad Sinha, Wei Zhang
2020 — conf
iGPU Leak: An Information Leakage Vulnerability on Intel Integrated GPU.
ASP-DAC
Wenjian He, Wei Zhang, Sharad Sinha, Sanjeev Das
2019 — conf
A Cost-Effective CNN Accelerator Design with Configurable PU on FPGA.
ISVLSI
Chi Fung Brian Fong, Jiandong Mu, Wei Zhang
2019 A conf
A Hybrid Data-Consistent Framework for Link-Aware AccessManagement in Emerging CPU-FPGA Platforms.
FPGA
Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
2019 — conf
Accelerate pattern recognition for cyber security analysis.
ASP-DAC
Mohammad Tahghighi, Wei Zhang
2019 J jnl
An Ensemble Learning Approach for In-Situ Monitoring of FPGA Dynamic Power.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Zhe Lin, Sharad Sinha, Wei Zhang
2019 J jnl
Editorial TVLSI Positioning - Continuing and Accelerating an Upward Trajectory.
IEEE Trans. Very Large Scale Integr. Syst.
Massimo Alioto, Magdy S. Abadir, Tughrul Arslan, Chirn Chye Boon, Andreas Burg, Chip-Hong Chang, Meng-Fan Chang, Yao-Wen Chang, Poki Chen, Pasquale Corsonello, Paolo Crovetti, Shiro Dosho, Rolf Drechsler, Ibrahim Abe M. Elfadel, Ruonan Han, Masanori Hashimoto, Chun-Huat Heng, Deukhyoun Heo, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Ajay Joshi, Rajiv V. Joshi, Tanay Karnik, Chulwoo Kim, Tony Tae-Hyoung Kim, Jaydeep P. Kulkarni, Volkan Kursun, Yoonmyung Lee, Hai Helen Li, Huawei Li, Prabhat Mishra, Baker Mohammad, Mehran Mozaffari Kermani, Makoto Nagata, Koji Nii, Partha Pratim Pande, Bipul C. Paul, Vasilis F. Pavlidis, José Pineda de Gyvez, Ioannis Savidis, Patrick Schaumont, Fabio Sebastiano, Anirban Sengupta, Mingoo Seok, Mircea R. Stan, Mark Tehranipoor, Aida Todri-Sanial, Marian Verhelst, Valerio Vignoli, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Jun Zhou, Mark Zwolinski, Stacey Weber
2019 A conf
Hi-ClockFlow: Multi-Clock Dataflow Automation and Throughput Optimization in High-Level Synthesis.
ICCAD
Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang
2019 A* conf
LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA Platforms.
DAC
Liang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
2019 A conf
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis.
DATE
Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
2019 J jnl
Machine Learning Based Routing Congestion Prediction in FPGA High-Level Synthesis.
CoRR
Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang
2019 A* conf
Poly: Efficient Heterogeneous System and Application Management for Interactive Applications.
HPCA
Shuo Wang, Yun Liang, Wei Zhang
2019 — conf
Real-Time Detection and Tracking Using Hybrid DNNs and Space-Aware Color Feature: From Algorithm to System.
ACPR (1)
Liang Feng, Hiroaki Igarashi, Seiya Shibata, Yuki Kobayashi, Takashi Takenaka, Wei Zhang
2019 Misc conf
Towards Efficient and Scalable Acceleration of Online Decision Tree Learning on FPGA.
FCCM
Zhe Lin, Sharad Sinha, Wei Zhang
2019 J jnl
Two-Layer Distributed Formation-Containment Control of Multiple Euler-Lagrange Systems by Output Feedback.
IEEE Trans. Cybern.
Dongyu Li, Wei Zhang, Wei He, Chuanjiang Li, Shuzhi Sam Ge
2018 B conf
A Collaborative Framework for FPGA-based CNN Design Modeling and Optimization.
FPL
Jiandong Mu, Wei Zhang, Hao Liang, Sharad Sinha
2018 Misc conf
CAMAS: Static and Dynamic Hybrid Cache Management for CPU-FPGA Platforms.
FCCM
Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang
2018 J jnl
FlexCL: A Model of Performance and Power for OpenCL Workloads on FPGAs.
IEEE Trans. Computers
Yun Liang, Shuo Wang, Wei Zhang
2018 J jnl
Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Tingyuan Liang, Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang
2018 J jnl
Parallelizing Hardware Tasks on Multicontext FPGA With Efficient Placement and Scheduling Algorithms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Hao Liang, Sharad Sinha, Wei Zhang
2018 J jnl
ROPSentry: Runtime defense against ROP attacks using hardware performance counters.
Comput. Secur.
Sanjeev Das, Bihuan Chen, Mahinthan Chandramohan, Yang Liu, Wei Zhang
2018 C conf
SGXlinger: A New Side-Channel Attack Vector Based on Interrupt Latency Against Enclave Execution.
ICCD
Wenjian He, Wei Zhang, Sanjeev Das, Yang Liu
2018 J jnl
Scalable Light-Weight Integration of FPGA Based Accelerators with Chip Multi-Processors.
IEEE Trans. Multi Scale Comput. Syst.
Zhe Lin, Sharad Sinha, Hao Liang, Liang Feng, Wei Zhang
2018 J jnl
Thermal-Aware Task Mapping on Dynamically Reconfigurable Network-on-Chip Based Multiprocessor System-on-Chip.
IEEE Trans. Computers
Weichen Liu, Lei Yang, Weiwen Jiang, Liang Feng, Nan Guan, Wei Zhang, Nikil D. Dutt
2017 J jnl
A Hybrid Logic Block Architecture in FPGA for Holistic Efficiency.
IEEE Trans. Circuits Syst. II Express Briefs
Tao Luo, Hao Liang, Wei Zhang, Bingsheng He, Douglas L. Maskell
2017 J jnl
A Variation-Aware Adaptive Fuzzy Control System for Thermal Management of Microprocessors.
IEEE Trans. Very Large Scale Integr. Syst.
Yingnan Cui, Wei Zhang, Bingsheng He
2017 A conf
A hybrid approach to cache management in heterogeneous CPU-FPGA platforms.
ICCAD
Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang
2017 A conf
A novel two-stage modular multiplier based on racetrack memory for asymmetric cryptography.
ICCAD
Tao Luo, Bingsheng He, Wei Zhang, Douglas L. Maskell
2017 A conf
COMBA: A comprehensive model-based analysis framework for high level synthesis of real applications.
ICCAD
Jieru Zhao, Liang Feng, Sharad Sinha, Wei Zhang, Yun Liang, Bingsheng He
2017 B conf
Decision tree based hardware power monitoring for run time dynamic power management in FPGA.
FPL
Zhe Lin, Wei Zhang, Sharad Sinha
2017 Misc conf
Dynamic Module Partitioning for Library Based Placement on Heterogeneous FPGAs.
FCCM
Fubing Mao, Wei Zhang, Bingsheng He, SiewKei Lam
2017 A conf
Dynamic Partitioning for Library based Placement on Heterogeneous FPGAs (Abstract Only).
FPGA
Fubing Mao, Wei Zhang, Bingsheng He, SiewKei Lam
2017 B conf
Dynamic module partitioning for library based placement on heterogeneous FPGAs.
RTCSA
Fubing Mao, Wei Zhang, Bingsheng He, SiewKei Lam
2017 J jnl
Editorial.
IEEE Trans. Very Large Scale Integr. Syst.
Krishnendu Chakrabarty, Massimo Alioto, Bevan M. Baas, Chirn Chye Boon, Meng-Fan Chang, Naehyuck Chang, Yao-Wen Chang, Chip-Hong Chang, Shih-Chieh Chang, Poki Chen, Masud H. Chowdhury, Pasquale Corsonello, Ibrahim Abe M. Elfadel, Said Hamdioui, Masanori Hashimoto, Tsung-Yi Ho, Houman Homayoun, Yuh-Shyan Hwang, Rajiv V. Joshi, Tanay Karnik, Mehran Mozaffari Kermani, Chulwoo Kim, Tae-Hyoung Kim, Jaydeep P. Kulkarni, Eren Kursun, Erik Larsson, Hai (Helen) Li, Huawei Li, Patrick P. Mercier, Prabhat Mishra, Makoto Nagata, Arun S. Natarajan, Koji Nii, Partha Pratim Pande, Ioannis Savidis, Mingoo Seok, Sheldon X.-D. Tan, Mark Tehranipoor, Aida Todri-Sanial, Miroslav N. Velev, Xiaoqing Wen, Jiang Xu, Wei Zhang, Zhengya Zhang, Stacey Weber Jackson
2017 Misc conf
FP-DNN: An Automated Framework for Mapping Deep Neural Networks onto FPGAs with RTL-HLS Hybrid Templates.
FCCM
Yijin Guan, Hao Liang, Ningyi Xu, Wenqiang Wang, Shaoshuai Shi, Xi Chen, Guangyu Sun, Wei Zhang, Jason Cong
2017 A* conf
FlexCL: An Analytical Performance Model for OpenCL Workloads on Flexible FPGAs.
DAC
Shuo Wang, Yun Liang, Wei Zhang
2017 J jnl
Fracturable DSP Block for Multi-context Reconfigurable Architectures.
Circuits Syst. Signal Process.
Rakesh Warrier, Shanker Shreejith, Wei Zhang, Chan Hua Vun, Suhaib A. Fahmy
2017 J jnl
HeteroSim: A Heterogeneous CPU-FPGA Simulator.
IEEE Comput. Archit. Lett.
Liang Feng, Hao Liang, Sharad Sinha, Wei Zhang
2017 J jnl
Local-to-global background modeling for moving object detection from non-static cameras.
Multim. Tools Appl.
Aihua Zheng, Lei Zhang, Wei Zhang, Chenglong Li, Jin Tang, Bin Luo
2017 J jnl
Multikernel Data Partitioning With Channel on OpenCL-Based FPGAs.
IEEE Trans. Very Large Scale Integr. Syst.
Zeke Wang, Johns Paul, Bingsheng He, Wei Zhang
2017 A* conf
No-Jump-into-Basic-Block: Enforce Basic Block CFI on the Fly for Real-world Binaries.
DAC
Wenjian He, Sanjeev Das, Wei Zhang, Yang Liu
2017 B conf
PAAS: A system level simulator for heterogeneous computing architectures.
FPL
Tingyuan Liang, Liang Feng, Sharad Sinha, Wei Zhang
2017 J jnl
Pipeline Reconfigurable DSP for Dynamically Reconfigurable Architectures.
Circuits Syst. Signal Process.
Rakesh Warrier, Wei Zhang, Chan Hua Vun
2017 — ed.
Proceedings of the 2017 Workshop on Attacks and Solutions in Hardware Security, ASHES@CCS 2017, Dallas, TX, USA, November 3, 2017
ASHES@CCS
Chip-Hong Chang, Ulrich Rührmair, Wei Zhang
2017 — conf
Two-stage thermal-aware scheduling of task graphs on 3D multi-cores exploiting application and architecture characteristics.
ASP-DAC
Zuomin Zhu, Vivek Chaturvedi, Amit Kumar Singh, Wei Zhang, Yingnan Cui
2016 J jnl
A Fine-Grained Control Flow Integrity Approach Against Runtime Memory Attacks for Embedded Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Sanjeev Das, Wei Zhang, Yang Liu
2016 A conf
A discrete thermal controller for chip-multiprocessors.
DATE
Yingnan Cui, Wei Zhang, Bingsheng He
2016 A* conf
A performance analysis framework for optimizing OpenCL applications on FPGAs.
HPCA
Zeke Wang, Bingsheng He, Wei Zhang, Shunning Jiang
2016 — conf
A racetrack memory based in-memory booth multiplier for cryptography application.
ASP-DAC
Tao Luo, Wei Zhang, Bingsheng He, Douglas L. Maskell
2016 A conf
Accelerating Database Query Processing on OpenCL-based FPGAs (Abstract Only).
FPGA
Zeke Wang, Hui Yan Cheah, Johns Paul, Bingsheng He, Wei Zhang
2016 — conf
Analytical Delay Model for CPU-FPGA Data Paths in Programmable System-on-Chip FPGA.
ARC
Mohammad Tahghighi, Sharad Sinha, Wei Zhang
2016 — conf
Area Efficient Hardware Architecture for Implicitly-Defined Complex Events Processing.
ISVLSI
Mohammad Tahghighi, Wei Zhang, Sharad Sinha
2016 J jnl
Cost-efficient Acceleration of Hardware Trojan Detection Through Fan-Out Cone Analysis and Weighted Random Pattern Technique.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bin Zhou, Wei Zhang, Thambipillai Srikanthan, Jason Teo Kian Jin, Vivek Chaturvedi, Tao Luo
2016 J jnl
Decentralized Thermal-Aware Task Scheduling for Large-Scale Many-Core Systems.
IEEE Trans. Very Large Scale Integr. Syst.
Yingnan Cui, Wei Zhang, Vivek Chaturvedi, Bingsheng He
2016 J jnl
Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst.
Weichen Liu, Wei Zhang, Xuan Wang, Jiang Xu
2016 B conf
HeteroSim: A heterogeneous CPU-FPGA simulator.
FPL
Liang Feng, Hao Liang, Sharad Sinha, Wei Zhang
2016 J jnl
Library-Based Placement and Routing in FPGAs with Support of Partial Reconfiguration.
ACM Trans. Design Autom. Electr. Syst.
Fubing Mao, Yi-Chung Chen, Wei Zhang, Hai (Helen) Li, Bingsheng He
2016 J jnl
Low-Power FPGA Design Using Memoization-Based Approximate Computing.
IEEE Trans. Very Large Scale Integr. Syst.
Sharad Sinha, Wei Zhang
2016 J jnl
Melia: A MapReduce Framework on OpenCL-Based FPGAs.
IEEE Trans. Parallel Distributed Syst.
Zeke Wang, Shuhao Zhang, Bingsheng He, Wei Zhang
2016 — conf
Modular Placement for Interposer based Multi-FPGA Systems.
ACM Great Lakes Symposium on VLSI
Fubing Mao, Wei Zhang, Bo Feng, Bingsheng He, Yuchun Ma
2016 C conf
Online malware defense using attack behavior model.
ISCAS
Sanjeev Das, Hao Xiao, Yang Liu, Wei Zhang
2016 B conf
Relational query processing on OpenCL-based FPGAs.
FPL
Zeke Wang, Johns Paul, Hui Yan Cheah, Bingsheng He, Wei Zhang
2016 J jnl
Semantics-Based Online Malware Detection: Towards Efficient Real-Time Protection Against Malware.
IEEE Trans. Inf. Forensics Secur.
Sanjeev Das, Yang Liu, Wei Zhang, Mahinthan Chandramohan
2016 J jnl
Thermal-Aware Task Scheduling for 3D-Network-on-Chip: A Bottom to Top Scheme.
J. Circuits Syst. Comput.
Yingnan Cui, Wei Zhang, Vivek Chaturvedi, Weichen Liu, Bingsheng He
2015 B conf
A study of data partitioning on OpenCL-based FPGAs.
FPL
Zeke Wang, Bingsheng He, Wei Zhang
2015 J jnl
Actively Alleviate Power Gating-Induced Power/Ground Noise Using Parasitic Capacitance of On-Chip Memories in MPSoC.
IEEE Trans. Very Large Scale Integr. Syst.
Xuan Wang, Jiang Xu, Wei Zhang, Xiaowen Wu, Yaoyao Ye, Zhehui Wang, Mahdi Nikdast, Zhe Wang
2015 — conf
An Efficient Technique for Chip Temperature Optimization of Multiprocessor Systems in the Dark Silicon Era.
HPCC/CSS/ICESS
Mengquan Li, Juan Yi, Weichen Liu, Wei Zhang, Lei Yang, Edwin Hsing-Mean Sha
2015 J jnl
FDR 2.0: A Low-Power Dynamically Reconfigurable Architecture and Its FinFET Implementation.
IEEE Trans. Very Large Scale Integr. Syst.
Ting-Jung Lin, Wei Zhang, Niraj K. Jha
2015 — conf
Hierarchical Library Based Power Estimator for Versatile FPGAs.
MCSoC
Hao Liang, Yi-Chung Chen, Tao Luo, Wei Zhang, Hai Li, Bingsheng He
2015 B conf
Hierarchical library based power estimator for versatile FPGAs.
FPL
Hao Liang, Wei Zhang, Sharad Sinha, Yi-Chung Chen, Hai Li
2015 Misc conf
Improving Data Partitioning Performance on OpenCL-Based FPGAs.
FCCM
Zeke Wang, Bingsheng He, Wei Zhang
2015 J jnl
Leveraging Hotspots and Improving Chip Reliability via Carbon Nanotube Grid Thermal Structure.
IEEE Trans. Very Large Scale Integr. Syst.
Hao Liang, Wei Zhang, Jiale Huang, Shengqi Yang, Pallav Gupta
2015 — conf
Motion Compensation Based Fast Moving Object Detection in Dynamic Background.
CCCV (2)
Wei Zhang, Chenglong Li, Aihua Zheng, Jin Tang, Bin Luo
2015 B conf
Static hardware task placement on multi-context FPGA using hybrid genetic algorithm.
FPL
Hao Liang, Sharad Sinha, Rakesh Warrier, Wei Zhang
2015 — conf
Traffic-Aware Application Mapping for Network-on-Chip Based Multiprocessor System-on-Chip.
HPCC/CSS/ICESS
Lei Yang, Weichen Liu, Weiwen Jiang, Wei Zhang, Mengquan Li, Juan Yi, Duo Liu, Edwin Hsing-Mean Sha
2014 J jnl
A Fine-Grain Dynamically Reconfigurable Architecture Aimed at Reducing the FPGA-ASIC Gaps.
IEEE Trans. Very Large Scale Integr. Syst.
Ting-Jung Lin, Wei Zhang, Niraj K. Jha
2014 Misc conf
A low cost acceleration method for hardware trojan detection based on fan-out cone analysis.
CODES+ISSS
Bin Zhou, Wei Zhang, Thambipillai Srikanthan, J. K. J. Teo
2014 — conf
A low-power pipelined MAC architecture using Baugh-Wooley based multiplier.
GCCE
Rakesh Warrier, Chan Hua Vun, Wei Zhang
2014 — conf
An extended framework for worst-case throughput analysis with router constraint.
APCCAS
Vineeth Mohan, Wenjing Hsu, Wei Zhang, Xiaowen Wu
2014 A conf
BMP: a fast B*-tree based modular placer for FPGAs (abstract only).
FPGA
Fubing Mao, Yi-Chung Chen, Wei Zhang, Hai Li
2014 J jnl
Floorplan Optimization of Fat-Tree-Based Networks-on-Chip for Chip Multiprocessors.
IEEE Trans. Computers
Zhehui Wang, Jiang Xu, Xiaowen Wu, Yaoyao Ye, Wei Zhang, Mahdi Nikdast, Xuan Wang, Zhe Wang
2014 A conf
Hierarchical library-based power estimator for versatile FPGAs (abstract only).
FPGA
Hao Liang, Yi-Chung Chen, Wei Zhang, Hai Li
2014 J jnl
Nonvolatile CBRAM-Crossbar-Based 3-D-Integrated Hybrid Memory for Data Retention.
IEEE Trans. Very Large Scale Integr. Syst.
Yuhao Wang, Hao Yu, Wei Zhang
2014 J jnl
On-chip sensor networks for soft-error tolerant real-time multiprocessor systems-on-chip.
ACM J. Emerg. Technol. Comput. Syst.
Weichen Liu, Xuan Wang, Jiang Xu, Wei Zhang, Yaoyao Ye, Xiaowen Wu, Mahdi Nikdast, Zhehui Wang
2014 C conf
Reconfigurable DSP block design for dynamically reconfigurable architecture.
ISCAS
Rakesh Warrier, Hao Liang, Wei Zhang
2014 — conf
Reconfigurable Dynamic Trusted Platform Module for Control Flow Checking.
ISVLSI
Sanjeev Das, Wei Zhang, Yang Liu
2014 — conf
Soft error mitigation through selection of noninvert implication paths.
AHS
Bin Zhou, Thambipillai Srikanthan, Wei Zhang
2014 — conf
Sum of products: Computation using modular thermometer codes.
ISPACS
Chan Hua Vun, A. Benjamin Premkumar, Wei Zhang
2014 J jnl
Systematic Analysis of Crosstalk Noise in Folded-Torus-Based Optical Networks-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mahdi Nikdast, Jiang Xu, Xiaowen Wu, Wei Zhang, Yaoyao Ye, Xuan Wang, Zhehui Wang, Zhe Wang
2014 — conf
Thermal-aware task scheduling for 3D-network-on-chip: A Bottom-to-Top scheme.
ISIC
Yingnan Cui, Wei Zhang, Vivek Chaturvedi, Weichen Liu, Bingsheng He
2014 C conf
Thermal-aware task scheduling for peak temperature minimization under periodic constraint for 3D-MPSoCs.
RSP
Vivek Chaturvedi, Amit Kumar Singh, Wei Zhang, Thambipillai Srikanthan
2014 — conf
Towards automatic partial reconfiguration in FPGAs.
FPT
Fubing Mao, Wei Zhang, Bingsheng He
2014 J jnl
UNION: A Unified Inter/Intrachip Optical Network for Chip Multiprocessors.
IEEE Trans. Very Large Scale Integr. Syst.
Xiaowen Wu, Yaoyao Ye, Jiang Xu, Wei Zhang, Weichen Liu, Mahdi Nikdast, Xuan Wang
2013 J jnl
3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yaoyao Ye, Jiang Xu, Baihan Huang, Xiaowen Wu, Wei Zhang, Xuan Wang, Mahdi Nikdast, Zhehui Wang, Weichen Liu, Zhe Wang
2013 J jnl
A New RNS based DA Approach for Inner Product Computation.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chan Hua Vun, A. Benjamin Premkumar, Wei Zhang
2013 B conf
A hardware security scheme for RRAM-based FPGA.
FPL
Yi-Chung Chen, Wei Zhang, Hai (Helen) Li
2013 A conf
Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories.
DATE
Xuan Wang, Jiang Xu, Wei Zhang, Xiaowen Wu, Yaoyao Ye, Zhehui Wang, Mahdi Nikdast, Zhe Wang
2013 A* conf
Digital-assisted noise-eliminating training for memristor crossbar-based analog neuromorphic computing engine.
DAC
Beiye Liu, Miao Hu, Hai Li, Zhi-Hong Mao, Yiran Chen, Tingwen Huang, Wei Zhang
2013 J jnl
Formal Worst-Case Analysis of Crosstalk Noise in Mesh-Based Optical Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst.
Yiyuan Xie, Mahdi Nikdast, Jiang Xu, Xiaowen Wu, Wei Zhang, Yaoyao Ye, Xuan Wang, Zhehui Wang, Weichen Liu
2013 J jnl
NBTI-aware circuit node criticality computation.
ACM J. Emerg. Technol. Comput. Syst.
Shengqi Yang, Wenping Wang, Mark Hagan, Wei Zhang, Pallav Gupta, Yu Cao
2013 J jnl
System-Level Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.
IEEE Trans. Very Large Scale Integr. Syst.
Yaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang, Xuan Wang, Mahdi Nikdast, Zhehui Wang, Weichen Liu
2013 — conf
Thermal simulator of 3D-IC with modeling of anisotropic TSV conductance and microchannel entrance effects.
ASP-DAC
Hanhua Qian, Hao Liang, Chip-Hong Chang, Wei Zhang, Hao Yu
2012 — conf
A Look Up Table design with 3D bipolar RRAMs.
ASP-DAC
Yi-Chung Chen, Wei Zhang, Hai Li
2012 J jnl
A Torus-Based Hierarchical Optical-Electronic Network-on-Chip for Multiprocessor System-on-Chip.
ACM J. Emerg. Technol. Comput. Syst.
Yaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang, Weichen Liu, Mahdi Nikdast
2012 C conf
A novel peripheral circuit for RRAM-based LUT.
ISCAS
Yi-Chung Chen, Hai Li, Wei Zhang
2012 J jnl
A physical design tool for carbon nanotube field-effect transistor circuits.
ACM J. Emerg. Technol. Comput. Syst.
Jiale Huang, Minhao Zhu, Shengqi Yang, Pallav Gupta, Wei Zhang, Steven M. Rubin, Gilda Garretón, Jin He
2012 A conf
A thermal and process variation aware MTJ switching model and its applications in soft error analysis.
ICCAD
Peiyuan Wang, Wei Zhang, Rajiv V. Joshi, Rouwaida Kanj, Yiran Chen
2012 C conf
Decentralized agent based re-clustering for task mapping of tera-scale network-on-chip system.
ISCAS
Yingnan Cui, Wei Zhang, Hao Yu
2012 J jnl
Design Exploration of Hybrid CMOS and Memristor Circuit by New Modified Nodal Analysis.
IEEE Trans. Very Large Scale Integr. Syst.
Wei Fei, Hao Yu, Wei Zhang, Kiat Seng Yeo
2012 A conf
Design of low power 3D hybrid memory by non-volatile CBRAM-crossbar with block-level data-retention.
ISLPED
Yuhao Wang, Chun Zhang, Hao Yu, Wei Zhang
2012 C conf
Distributed thermal-aware task scheduling for 3D Network-on-Chip.
ICCD
Yingnan Cui, Wei Zhang, Hao Yu
2012 — conf
Fine-grained dynamic voltage scaling on OLED display.
ASP-DAC
Xiang Chen, Jian Zheng, Yiran Chen, Wei Zhang, Hai Li
2012 B conf
Non-volatile 3D stacking RRAM-based FPGA.
FPL
Yi-Chung Chen, Wenhua Wang, Hai Li, Wei Zhang
2012 J jnl
SRAM-Based NATURE: A Dynamically Reconfigurable FPGA Based on 10T Low-Power SRAMs.
IEEE Trans. Very Large Scale Integr. Syst.
Ting-Jung Lin, Wei Zhang, Niraj K. Jha
2012 — conf
uBRAM-based run-time reconfigurable FPGA and corresponding reconfiguration methodology.
FPT
Yi-Chung Chen, Wenhua Wang, Wei Zhang, Hai Li
2011 — conf
3D-HIM: A 3D High-density Interleaved Memory for bipolar RRAM design.
NANOARCH
Yi-Chung Chen, Hai Li, Wei Zhang, Robinson E. Pino
2011 — conf
A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC.
ISVLSI
Weichen Liu, Jiang Xu, Xuan Wang, Yu Wang, Wei Zhang, Yaoyao Ye, Xiaowen Wu, Mahdi Nikdast, Zhehui Wang
2011 — conf
A NoC Traffic Suite Based on Real Applications.
ISVLSI
Weichen Liu, Jiang Xu, Xiaowen Wu, Yaoyao Ye, Xuan Wang, Wei Zhang, Mahdi Nikdast, Zhehui Wang
2011 A conf
Case study: Alleviating hotspots and improving chip reliability via carbon nanotube thermal interface.
DATE
Wei Zhang, Jiale Huang, Shengqi Yang, Pallav Gupta
2011 J jnl
Coroutine-Based Synthesis of Efficient Embedded Software From SystemC Models.
IEEE Embed. Syst. Lett.
Weichen Liu, Jiang Xu, Jogesh K. Muppala, Wei Zhang, Xiaowen Wu, Yaoyao Ye
2011 — conf
Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip.
ISVLSI
Yaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang, Xuan Wang, Mahdi Nikdast, Zhehui Wang, Weichen Liu
2011 — conf
NEMS based thermal management for 3D many-core system.
NANOARCH
Xiwei Huang, Hao Yu, Wei Zhang
2011 — ch.
Power Dissipation.
Low-Power Variation-Tolerant Design in Nanometer Silicon
Wei Zhang, James Williamson, Li Shang
2010 — conf
A Hierarchical Hybrid Optical-Electronic Network-on-Chip.
ISVLSI
Mo Kwai Hung, Yaoyao Ye, Xiaowen Wu, Wei Zhang, Weichen Liu, Jiang Xu
2010 A* conf
Crosstalk noise and bit error rate analysis for optical network-on-chip.
DAC
Yiyuan Xie, Mahdi Nikdast, Jiang Xu, Wei Zhang, Qi Li, Xiaowen Wu, Yaoyao Ye, Xuan Wang, Weichen Liu
2010 J jnl
Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture.
ACM J. Emerg. Technol. Comput. Syst.
Wei Zhang, Niraj K. Jha, Li Shang
2010 — conf
UNION: A unified inter/intra-chip optical network for chip multiprocessors.
NANOARCH
Xiaowen Wu, Yaoyao Ye, Wei Zhang, Weichen Liu, Mahdi Nikdast, Xuan Wang, Jiang Xu
2009 — conf
A Low-power Low-cost Optical Router for Optical Networks-on-Chip in Multiprocessor Systems-on-Chip.
ISVLSI
Huaxi Gu, Mo Kwai Hung Morton, Jiang Xu, Wei Zhang
2009 J jnl
A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow.
ACM J. Emerg. Technol. Comput. Syst.
Wei Zhang, Niraj K. Jha, Li Shang
2009 J jnl
A hybrid nano/CMOS dynamically reconfigurable system - Part I: Architecture.
ACM J. Emerg. Technol. Comput. Syst.
Wei Zhang, Niraj K. Jha, Li Shang
2009 A conf
A low-power fat tree-based optical Network-On-Chip for multiprocessor system-on-chip.
DATE
Huaxi Gu, Jiang Xu, Wei Zhang
2009 J jnl
Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture.
ACM J. Emerg. Technol. Comput. Syst.
Wei Zhang, Niraj K. Jha, Li Shang
2009 J jnl
Double-Data-Rate, Wave-Pipelined Interconnect for Asynchronous NoCs.
IEEE Micro
Jiang Xu, Wayne H. Wolf, Wei Zhang
2007 A* conf
NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture.
DAC
Wei Zhang, Li Shang, Niraj K. Jha
2006 A* conf
NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture.
DAC
Wei Zhang, Niraj K. Jha, Li Shang
2005 C conf
ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology.
ICCD
Wei Zhang, Niraj K. Jha
test_files/hello
← Index test_files/hello binary
Binary file: 15960 bytes total. Showing the first 4096 bytes as hex.
00000000  7f 45 4c 46 02 01 01 00  00 00 00 00 00 00 00 00  |.ELF............|
00000010  03 00 3e 00 01 00 00 00  60 10 00 00 00 00 00 00  |..>.....`.......|
00000020  40 00 00 00 00 00 00 00  98 36 00 00 00 00 00 00  |@........6......|
00000030  00 00 00 00 40 00 38 00  0d 00 40 00 1f 00 1e 00  |[email protected]...@.....|
00000040  06 00 00 00 04 00 00 00  40 00 00 00 00 00 00 00  |........@.......|
00000050  40 00 00 00 00 00 00 00  40 00 00 00 00 00 00 00  |@.......@.......|
00000060  d8 02 00 00 00 00 00 00  d8 02 00 00 00 00 00 00  |................|
00000070  08 00 00 00 00 00 00 00  03 00 00 00 04 00 00 00  |................|
00000080  18 03 00 00 00 00 00 00  18 03 00 00 00 00 00 00  |................|
00000090  18 03 00 00 00 00 00 00  1c 00 00 00 00 00 00 00  |................|
000000a0  1c 00 00 00 00 00 00 00  01 00 00 00 00 00 00 00  |................|
000000b0  01 00 00 00 04 00 00 00  00 00 00 00 00 00 00 00  |................|
000000c0  00 00 00 00 00 00 00 00  00 00 00 00 00 00 00 00  |................|
000000d0  28 06 00 00 00 00 00 00  28 06 00 00 00 00 00 00  |(.......(.......|
000000e0  00 10 00 00 00 00 00 00  01 00 00 00 05 00 00 00  |................|
000000f0  00 10 00 00 00 00 00 00  00 10 00 00 00 00 00 00  |................|
00000100  00 10 00 00 00 00 00 00  75 01 00 00 00 00 00 00  |........u.......|
00000110  75 01 00 00 00 00 00 00  00 10 00 00 00 00 00 00  |u...............|
00000120  01 00 00 00 04 00 00 00  00 20 00 00 00 00 00 00  |......... ......|
00000130  00 20 00 00 00 00 00 00  00 20 00 00 00 00 00 00  |. ....... ......|
00000140  f4 00 00 00 00 00 00 00  f4 00 00 00 00 00 00 00  |................|
00000150  00 10 00 00 00 00 00 00  01 00 00 00 06 00 00 00  |................|
00000160  b8 2d 00 00 00 00 00 00  b8 3d 00 00 00 00 00 00  |.-.......=......|
00000170  b8 3d 00 00 00 00 00 00  58 02 00 00 00 00 00 00  |.=......X.......|
00000180  60 02 00 00 00 00 00 00  00 10 00 00 00 00 00 00  |`...............|
00000190  02 00 00 00 06 00 00 00  c8 2d 00 00 00 00 00 00  |.........-......|
000001a0  c8 3d 00 00 00 00 00 00  c8 3d 00 00 00 00 00 00  |.=.......=......|
000001b0  f0 01 00 00 00 00 00 00  f0 01 00 00 00 00 00 00  |................|
000001c0  08 00 00 00 00 00 00 00  04 00 00 00 04 00 00 00  |................|
000001d0  38 03 00 00 00 00 00 00  38 03 00 00 00 00 00 00  |8.......8.......|
000001e0  38 03 00 00 00 00 00 00  30 00 00 00 00 00 00 00  |8.......0.......|
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