Wei Zhang - RankMe

157 papers A* 4A 11B 6C 20Misc 9Journal 59Unranked 45

Year	Rank	Type	Title / Venue / Authors
2021	J	`jnl`	Cache Leakage Reduction Techniques for Hybrid SPM-Cache Architectures. J. Circuits Syst. Comput. Hao Wen, Wei Zhang
2020	—	`conf`	Denial of Service in CPU-GPU Heterogeneous Architectures. HPEC Hao Wen, Wei Zhang
2020	—	`conf`	Packing Narrow-Width Operands to Improve Energy Efficiency of General-Purpose GPU Computing. HPEC Xin Wang, Wei Zhang
2020	J	`jnl`	Reducing CPU-GPU Interferences to Improve CPU Performance in Heterogeneous Architectures. J. Comput. Sci. Eng. Hao Wen, Wei Zhang
2020	C	`conf`	pacSCA: A Profiling-Assisted Correlation-based Side-Channel Attack on GPUs. ICCD Xin Wang, Wei Zhang
2019	—	`conf`	A Collaborative Neurodynamic Approach to Sparse Coding. ISNN (1) Hangjun Che, Jun Wang, Wei Zhang
2019	—	`conf`	An Efficient Profiling-Based Side-Channel Attack on Graphics Processing Units. NCS Xin Wang, Wei Zhang
2019	—	`conf`	Cracking Randomized Coalescing Techniques with An Efficient Profiling-Based Side-Channel Attack to GPU. HASP@ISCA Xin Wang, Wei Zhang
2019	—	`conf`	Execution Units Power-Gating to Improve Energy Efficiency of GPGPUs. iThings/GreenCom/CPSCom/SmartData Xin Wang, Wei Zhang
2019	—	`conf`	Heterogeneous Cache Hierarchy Management for Integrated CPU-GPU Architecture. HPEC Hao Wen, Wei Zhang
2019	—	`conf`	Improving Parallelism of Breadth First Search (BFS) Algorithm for Accelerated Performance on GPUs. HPEC Hao Wen, Wei Zhang
2018	J	`jnl`	Cache-Aware SPM Allocation Algorithms for Performance and Energy Optimization on Hybrid SPM-Cache Architecture. J. Comput. Sci. Eng. Lan Wu, Wei Zhang
2018	J	`jnl`	Cache-Aware SPM Allocation to Reduce Worst-Case Execution Time for Hybrid SPM-Caches. J. Circuits Syst. Comput. Lan Wu, Wei Zhang
2018	—	`conf`	Energy-Efficient DNN Computing on GPUs Through Register File Management. HPEC Xin Wang, Wei Zhang
2018	J	`jnl`	Estimating the Worst-Case Execution Time of the Shared Data Cache in Integrated CPU-GPU Architectures. J. Comput. Sci. Eng. Yijie Huangfu, Wei Zhang
2018	—	`conf`	Exploiting GPU with 3D Stacked Memory to Boost Performance for Data-Intensive Applications. HPEC Hao Wen, Wei Zhang
2018	J	`jnl`	Exploring GPU Data Cache Leakage Management Techniques. J. Comput. Sci. Eng. Hao Wen, Wei Zhang
2018	J	`jnl`	Improving CPU and GPU Performance through Sample-Based Dynamic LLC Bypassing. J. Comput. Sci. Eng. Xin Wang, Wei Zhang
2018	J	`jnl`	Packing Narrow-Width Operands to Improve GPU Performance. J. Comput. Sci. Eng. Xin Wang, Wei Zhang
2018	C	`conf`	Reducing Inter-Application Interferences in Integrated CPU-GPU Heterogeneous Architecture. ICCD Hao Wen, Wei Zhang
2018	—	`conf`	Regression Based WCET Analysis For Sampling Based Motion Planning. HPEC Hao Wen, Wei Zhang
2018	—	`conf`	WCET Analysis of GPU L1 Data Caches. HPEC Yijie Huangfu, Wei Zhang
2017	—	`conf`	A Sample-Based Dynamic CPU and GPU LLC Bypassing Method for Heterogeneous CPU-GPU Architectures. TrustCom/BigDataSE/ICESS Xin Wang, Wei Zhang
2017	B	`conf`	Drowsy Register Files for Reducing GPU Leakage Energy. ICPADS Xin Wang, Wei Zhang
2017	J	`jnl`	Enhancing GPU Performance by Efficient Hardware-Based and Hybrid L1 Data Cache Bypassing. J. Comput. Sci. Eng. Yijie Huangfu, Wei Zhang
2017	—	`conf`	GPU Register Packing: Dynamically Exploiting Narrow-Width Operands to Improve Performance. TrustCom/BigDataSE/ICESS Xin Wang, Wei Zhang
2017	—	`conf`	Leakage energy reduction for hard real-time caches. HPEC Yijie Huangfu, Wei Zhang
2017	C	`conf`	Static WCET Analysis of GPUs with Predictable Warp Scheduling. ISORC Yijie Huangfu, Wei Zhang
2017	—	`conf`	WCET analysis of the shared data cache in integrated CPU-GPU architectures. HPEC Yijie Huangfu, Wei Zhang
2017	J	`jnl`	Warp-Based Load/Store Reordering to Improve GPU Time Predictability. J. Comput. Sci. Eng. Yijie Huangfu, Wei Zhang
2016	C	`conf`	Cache locking vs. partitioning for real-time computing on integrated CPU-GPU processors. IPCCC Xin Wang, Wei Zhang
2016	J	`jnl`	Priority L2 cache design for time predictability. Int. J. Embed. Syst. Jun Yan, Wei Zhang
2016	C	`conf`	Warp-Based Load/Store Reordering to Improve GPU Data Cache Time Predictability and Performance. ISORC Yijie Huangfu, Wei Zhang
2015	B	`conf`	Boosting GPU Performance by Profiling-Based L1 Data Cache Bypassing. CCGRID Yijie Huangfu, Wei Zhang
2015	—	`conf`	Cache-aware SPM allocation algorithms for hybrid SPM-cache architectures. ISQED Lan Wu, Wei Zhang
2015	J	`jnl`	Exploiting Static Non-Uniform Cache Architectures for Hard Real-Time Computing. J. Comput. Sci. Eng. Yiqiang Ding, Wei Zhang
2015	—	`conf`	Exploring shared memory and cache to improve GPU performance and energy efficiency. ISQED Hao Wen, Wei Zhang
2015	C	`conf`	Hardware-Based Performance Enhancement Guaranteed Caches. ISORC Yijie Huangfu, Wei Zhang
2015	—	`conf`	Hardware-Based and Hybrid L1 Data Cache Bypassing to Improve GPU Performance. HPCC/CSS/ICESS Yijie Huangfu, Wei Zhang
2015	J	`jnl`	Profiling-based L1 data cache bypassing to improve GPU performance and energy efficiency. SIGBED Rev. Yijie Huangfu, Wei Zhang
2015	C	`conf`	Real-Time GPU Computing: Cache or No Cache? ISORC Yijie Huangfu, Wei Zhang
2015	J	`jnl`	Scratchpad Memory Architectures and Allocation Algorithms for Hard Real-Time Multicore Processors. J. Comput. Sci. Eng. Yu Liu, Wei Zhang
2014	C	`conf`	A Real-Time Instruction Cache with High Average-Case Performance. ISORC Yijie Huangfu, Wei Zhang
2014	—	`conf`	Bounding the Worst-Case Execution Time of Static NUCA Caches. HPCC/CSS/ICESS Yiqiang Ding, Wei Zhang
2014	—	`conf`	Characterizing Energy Consumption of Real-Time and Media Benchmarks on Hybrid SPM-Caches. HPCC/CSS/ICESS Lan Wu, Yiqiang Ding, Wei Zhang
2014	J	`jnl`	Comparing Separate and Statically-Partitioned Caches for Time-Predictable Multicore Processors. J. Comput. Sci. Eng. Lan Wu, Yiqiang Ding, Wei Zhang
2014	—	`conf`	Compiler-directed leakage energy reduction for instruction scratch-pad memories. ISQED Yijie Huangfu, Wei Zhang
2014	—	`conf`	Exploiting Hybrid SPM-Cache Architectures to Reduce Energy Consumption for Embedded Computing. HPCC/CSS/ICESS Wei Zhang, Lan Wu
2014	J	`jnl`	Exploiting Standard Deviation of CPI to Evaluate Architectural Time-Predictability. J. Comput. Sci. Eng. Wei Zhang, Yiqiang Ding
2014	C	`conf`	Hop-Based Priority Scheduling to Improve Worst-Case Inter-core Communication Latency. EUC Yiqiang Ding, Wei Zhang
2014	C	`conf`	Improving Energy Efficiency with Dynamic Compiler-Directed Function Unit Power Control. EUC Yu Sun, Wei Zhang
2014	J	`jnl`	PEG-C: Performance Enhancement Guaranteed Cache for Hard Real-Time Systems. IEEE Embed. Syst. Lett. Yijie Huangfu, Wei Zhang
2014	—	`conf`	Performance Implication of Multicore Cache Locking on General-Purpose Processors. HPCC/CSS/ICESS Matthew Loach, Wei Zhang
2014	Misc	`conf`	Reducing cache leakage energy for hybrid SPM-cache architectures. CASES Hao Wen, Wei Zhang
2014	J	`jnl`	Two-Level Scratchpad Memory Architectures to Achieve Time Predictability and High Performance. J. Comput. Sci. Eng. Yu Liu, Wei Zhang
2014	C	`conf`	WCET analysis of static NUCA caches. IPCCC Yiqiang Ding, Wei Zhang
2014	C	`conf`	Worst-case performance guaranteed data cache. IPCCC Yijie Huangfu, Wei Zhang
2013	J	`jnl`	Bounding Worst-Case DRAM Performance on Multicore Processors. J. Comput. Sci. Eng. Yiqiang Ding, Lan Wu, Wei Zhang
2013	C	`conf`	Compiler-based approach to reducing leakage energy of instruction scratch-pad memories. ICCD Yijie Huangfu, Wei Zhang
2013	J	`jnl`	Counter-Based Approaches for Efficient WCET Analysis of Multicore Processors with Shared Caches. J. Comput. Sci. Eng. Yiqiang Ding, Wei Zhang
2013	C	`conf`	Defend GPUs against DoS attacks. IPCCC Wei Zhang
2013	—	`conf`	Hybrid SPM-cache architectures to achieve high time predictability and performance. ASAP Wei Zhang, Yiqiang Ding
2013	J	`jnl`	Multicore Real-Time Scheduling to Reduce Inter-Thread Cache Interferences. J. Comput. Sci. Eng. Yiqiang Ding, Wei Zhang
2013	—	`conf`	On the interactions between real-time scheduling and inter-thread cached interferences for multicore processors. ISQED Yiqiang Ding, Wei Zhang
2013	J	`jnl`	Overview of Real-Time Java Computing. J. Comput. Sci. Eng. Yu Sun, Wei Zhang
2013	C	`conf`	Reducing worst-case execution time of hybrid SPM-caches. IPCCC Lan Wu, Wei Zhang
2013	—	`conf`	Standard deviation of CPI: A new metric to evaluate architectural time predictability. ASAP Wei Zhang, Yiqiang Ding
2013	J	`jnl`	Static worst-case lifetime estimation of wireless sensor networks: A case study on VigilNet. J. Syst. Archit. Yu Liu, Wei Zhang
2012	J	`jnl`	A Model Checking Based Approach to Bounding Worst-Case Execution Time for Multicore Processors. ACM Trans. Embed. Comput. Syst. Lan Wu, Wei Zhang
2012	J	`jnl`	Architectural time-predictability factor (ATF): a metric to evaluate time predictability of processors. SIGBED Rev. Yiqiang Ding, Wei Zhang
2012	—	`conf`	Exploiting SPM-aware Scheduling on EPIC architectures for high-performance real-time systems. HPEC Yu Liu, Wei Zhang
2012	C	`conf`	Exploiting multi-level scratchpad memories for time-predictable multicore computing. ICCD Yu Liu, Wei Zhang
2012	J	`jnl`	Multicore-Aware Code Co-Positioning to Reduce WCET on Dual-Core Processors with Shared Instruction Caches. J. Comput. Sci. Eng. Yiqiang Ding, Wei Zhang
2012	J	`jnl`	On-line Trace Based Automatic Parallelization of Java Programs on Multicore Platforms. J. Comput. Sci. Eng. Yu Sun, Wei Zhang
2012	J	`jnl`	Static Timing Analysis of Shared Caches for Multicore Processors. J. Comput. Sci. Eng. Wei Zhang, Jun Yan
2012	J	`jnl`	Time-Predictable Java Dynamic Compilation on Multicore Processors. J. Comput. Sci. Eng. Yu Sun, Wei Zhang
2011	J	`jnl`	An Interference Matrix Based Approach to Bounding Worst-Case Inter-Thread Cache Interferences and WCET for Multi-Core Processors. J. Comput. Sci. Eng. Jun Yan, Wei Zhang
2011	J	`jnl`	Bounding Worst-Case Performance for Multi-Core Processors with Shared L2 Instruction Caches. J. Comput. Sci. Eng. Jun Yan, Wei Zhang
2011	J	`jnl`	Computing and Reducing Transient Error Propagation in Registers. J. Comput. Sci. Eng. Jun Yan, Wei Zhang
2011	J	`jnl`	Exploiting Instruction Reuse to Improve the Performance of Dual Instruction Execution. J. Circuits Syst. Comput. Abhishek Pillai, Wei Zhang
2011	Misc	`conf`	Exploiting time predictable two-level scratchpad memory for real-time systems. SAC Yu Liu, Wei Zhang
2011	C	`conf`	Multicore-Aware Code Positioning to Improve Worst-Case Performance. ISORC Yiqiang Ding, Wei Zhang
2011	—	`conf`	On-Line Trace Based Automatic Parallelization of Java Programs on Multicore Platforms. Interaction between Compilers and Computer Architectures Yu Sun, Wei Zhang
2011	Misc	`conf`	Stack distance based worst-case instruction cache performance analysis. SAC Yu Liu, Wei Zhang
2011	—	`conf`	Static Worst-Case Lifetime Estimation of Vigil Net. GreenCom Yu Liu, Wei Zhang
2011	C	`conf`	Work in progress - Course development of programming for general-purpose multicore processors. FIE Wei Zhang
2010	—	`conf`	A time-predictable dual-core prototype on FPGA. ACM Southeast Regional Conference Satya Mohan Raju Gudidevuni, Wei Zhang
2010	J	`jnl`	Design and implementation of hybrid multicore simulators. Int. J. Embed. Syst. Jun Yan, Wei Zhang
2010	—	`conf`	Improving the static real-time scheduling on multicore processors by reducing worst-case inter-thread cache interferences. ACM Southeast Regional Conference Yiqiang Ding, Wei Zhang
2010	J	`jnl`	Loop-Based Instruction Prefetching to Reduce the Worst-Case Execution Time. IEEE Trans. Computers Yiqiang Ding, Wei Zhang
2010	J	`jnl`	Replica victim caching to improve cache reliability against transient errors. Int. J. High Perform. Syst. Archit. Wei Zhang
2010	J	`jnl`	Static Worst-Case Energy and Lifetime Estimation of Wireless Sensor Networks. J. Comput. Sci. Eng. Yu Liu, Wei Zhang, Kemal Akkaya
2010	B	`conf`	Time-Predictable L2 Cache Design for High-Performance Real-Time Systems. RTCSA Jun Yan, Wei Zhang
2010	J	`jnl`	Time-dependent density functional theory study on the hydrogen bonding-induced twisted intramolecular charge-transfer excited states of 2-(4'- J. Comput. Chem. Shu-Hui Yin, Yufang Liu, Wei Zhang, Ming-Xing Guo, Peng Song
2009	B	`conf`	Accurately Estimating Worst-Case Execution Time for Multi-core Processors with Shared Direct-Mapped Instruction Caches. RTCSA Wei Zhang, Jun Yan
2009	J	`jnl`	Boosting the Performance of Software-Based Transient Errors Tolerant Techniques through Compiler Optimizations. J. Circuits Syst. Comput. Wei Zhang
2009	J	`jnl`	Bounding Worst-Case Data Cache Performance by Using Stack Distance. J. Comput. Sci. Eng. Yu Liu, Wei Zhang
2009	J	`jnl`	Computing and Minimizing Cache Vulnerability to Transient Errors. IEEE Des. Test Comput. Wei Zhang
2009	B	`conf`	Exploiting Multi-core Processors to Improve Time Predictability for Real-Time Java Computing. RTCSA Yu Sun, Wei Zhang
2009	Misc	`conf`	Exploiting stack distance to estimate worst-case data cache performance. SAC Yu Liu, Wei Zhang
2009	J	`jnl`	Improving Java performance and energy dissipation through efficient code caching. Des. Autom. Embed. Syst. Yu Sun, Wei Zhang
2009	J	`jnl`	Optimizing Instruction Prefetching to Improve Worst-Case Performance for Real-Time Applications. J. Comput. Sci. Eng. Yiqiang Ding, Jun Yan, Wei Zhang
2009	C	`conf`	Static worst-case energy and lifetime estimation of wireless sensor networks. IPCCC Yu Liu, Wei Zhang, Kemal Akkaya
2009	J	`jnl`	Studying Energy-Oriented Dynamic Optimizations in Java Virtual Machines. J. Circuits Syst. Comput. Yu Sun, Wei Zhang
2008	J	`jnl`	A time-predictable VLIW processor and its compiler support. Real Time Syst. Jun Yan, Wei Zhang
2008	—	`conf`	Adaptive Drowsy Cache Control for Java Applications. EUC (1) Yu Sun, Wei Zhang
2008	J	`jnl`	Analyzing the worst-case execution time for instruction caches with prefetching. ACM Trans. Embed. Comput. Syst. Jun Yan, Wei Zhang
2008	Misc	`conf`	Efficient code caching to improve performance and energy consumption for java applications. CASES Yu Sun, Wei Zhang
2008	J	`jnl`	Exploiting virtual registers to reduce pressure on real registers. ACM Trans. Archit. Code Optim. Jun Yan, Wei Zhang
2008	A	`conf`	Improving code caching performance for Java applications. IPDPS Yu Sun, Wei Zhang
2008	A	`conf`	On the Energy Efficiency of Java Virtual Machine. ESA Yu Sun, Wei Zhang
2008	A	`conf`	WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches. IEEE Real-Time and Embedded Technology and Applications Symposium Jun Yan, Wei Zhang
2007	—	`conf`	An Area-Efficient Approach to Improving Register File Reliability against Transient Errors. AINA Workshops (1) Mallik Kandala, Wei Zhang, Laurence Tianruo Yang
2007	J	`jnl`	Compiler-Assisted Leakage Energy Reduction for Cache Memories. Adv. Comput. Wei Zhang
2007	—	`conf`	Detecting VLIW Hard Errors Cost-Effectively through a Software-Based Approach. AINA Workshops (1) Abhishek Pillai, Wei Zhang, Dimitrios Kagaris
2007	J	`jnl`	Evaluating instruction cache vulnerability to transient errors. SIGARCH Comput. Archit. News Jun Yan, Wei Zhang
2007	—	`conf`	Exploring Functional Unit Design Space of VLIW Processors for Optimizing Both Performance and Energy Consumption. AINA Workshops (1) Abhishek Pillai, Wei Zhang, Laurence Tianruo Yang
2007	J	`jnl`	Hybrid multi-core architecture for boosting single-threaded performance. SIGARCH Comput. Archit. News Jun Yan, Wei Zhang
2007	A*	`conf`	Real-time Accurate Object Detection using Multiple Resolutions. ICCV Wei Zhang, Gregory J. Zelinsky, Dimitris Samaras
2007	J	`jnl`	Reducing branch predictor leakage energy by exploiting loops. ACM Trans. Embed. Comput. Syst. Wei Zhang, Bramha Allu
2007	—	`conf`	Virtual Registers: Reducing Register Pressure Without Enlarging the Register File. HiPEAC Jun Yan, Wei Zhang
2007	B	`conf`	WCET analysis of instruction caches with prefetching. LCTES Jun Yan, Wei Zhang
2006	J	`jnl`	Compiler-guided next sub-bank prediction for reducing instruction cache leakage energy. J. Embed. Comput. Wei Zhang
2006	J	`jnl`	Reducing Instruction Translation Look-Aside Buffer Energy Through Compiler-Directed Resizing. J. Low Power Electron. Bramha Allu, Wei Zhang
2006	J	`jnl`	Reducing dynamic and leakage energy in VLIW architectures. ACM Trans. Embed. Comput. Syst. Wei Zhang, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
2006	—	`conf`	The Impact of Cache Organization in Optimizing Microprocessor Power Consumption. CDES Nagm Mohamed, Nazeih Botros, Wei Zhang
2005	—	`conf`	A Computational Model of Eye Movements during Object Class Detection. NIPS Wei Zhang, Hyejin Yang, Dimitris Samaras, Gregory J. Zelinsky
2005	Misc	`conf`	Compiler-guided register reliability improvement against soft errors. EMSOFT Jun Yan, Wei Zhang
2005	—	`conf`	Computing Cache Vulnerability to Transient Errors and Its Implication. DFT Wei Zhang
2005	J	`jnl`	Exploiting loop behavior for data cache leakage reduction. J. Embed. Comput. Wei Zhang
2005	J	`jnl`	Exploiting the replication cache to improve performance for multiple-issue microprocessors. SIGARCH Comput. Archit. News Bramha Allu, Wei Zhang
2005	—	`conf`	Object Class Recognition Using Multiple Layer Boosting with Heterogeneous Features. CVPR (2) Wei Zhang, Bing Yu, Gregory J. Zelinsky, Dimitris Samaras
2005	J	`jnl`	Reducing data cache leakage energy using a compiler-based approach. ACM Trans. Embed. Comput. Syst. Wei Zhang, Mahmut T. Kandemir, Mustafa Karaköy, Guangyu Chen
2005	J	`jnl`	Replication Cache: A Small Fully Associative Cache to Improve Data Cache Reliability. IEEE Trans. Computers Wei Zhang
2005	—	`conf`	The Role of Top-down and Bottom-up Processes in Guiding Eye Movements during Visual Search. NIPS Gregory J. Zelinsky, Wei Zhang, Bing Yu, Xin Chen, Dimitris Samaras
2004	—	`conf`	Compiler-Directed Data Cache Leakage Reduction. ISVLSI Wei Zhang
2004	A	`conf`	Enhancing data cache reliability by the addition of a small fully-associative replication cache. ICS Wei Zhang
2004	Misc	`conf`	Loop-based leakage control for branch predictors. CASES Wei Zhang, Bramha Allu
2004	J	`jnl`	Reducing instruction cache energy consumption using a compiler-based strategy. ACM Trans. Archit. Code Optim. Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
2004	—	`conf`	Replica Victim Caching to Improve Reliability of In-Cache Replication. Asia-Pacific Computer Systems Architecture Conference Wei Zhang
2004	Misc	`conf`	Static next sub-bank prediction for drowsy instruction cache. CASES Bramha Allu, Wei Zhang
2003	A	`conf`	A compiler approach for reducing data cache energy. ICS Wei Zhang, Mustafa Karaköy, Mahmut T. Kandemir, Guangyu Chen
2003	A	`conf`	Compiler Support for Reducing Leakage Energy Consumption. DATE Wei Zhang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Vivek De
2003	C	`conf`	Compiler-Directed Management of Instruction Accesses. DSD Guilin Chen, Guangyu Chen, Ismail Kadayif, Wei Zhang, Mahmut T. Kandemir, Ibrahim Kolcu, Ugur Sezer
2003	A	`conf`	Data Space Oriented Scheduling in Embedded Systems. DATE Mahmut T. Kandemir, Guangyu Chen, Wei Zhang, Ibrahim Kolcu
2003	—	`ch.`	Data Space Oriented Scheduling. Embedded Software for SoC Mahmut T. Kandemir, Guangyu Chen, Wei Zhang, Ibrahim Kolcu
2003	—	`ch.`	Dynamic Parallelization of Array Based On-Chip Multiprocessor Applications. Embedded Software for SoC Mahmut T. Kandemir, Wei Zhang, Mustafa Karaköy
2003	—	`ch.`	Energy-Aware Parameter Passing. Embedded Software for SoC Mahmut T. Kandemir, Ibrahim Kolcu, Wei Zhang
2003	A	`conf`	ICR: In-Cache Replication for Enhancing Data Cache Reliability. DSN Wei Zhang, Sudhanva Gurumurthi, Mahmut T. Kandemir, Anand Sivasubramaniam
2003	A	`conf`	Implementation and Evaluation of an On-Demand Parameter-Passing Strategy for Reducing Energy. DATE Mahmut T. Kandemir, Ibrahim Kolcu, Wei Zhang
2003	A*	`conf`	Interprocedural optimizations for improving data cache performance of array-intensive embedded applications. DAC Wei Zhang, Guangyu Chen, Mahmut T. Kandemir, Mustafa Karaköy
2003	A	`conf`	Masking the Energy Behavior of DES Encryption. DATE Hendra Saputra, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Richard R. Brooks, Soontae Kim, Wei Zhang
2003	Misc	`conf`	Performance, energy, and reliability tradeoffs in replicating hot cache lines. CASES Wei Zhang, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin
2003	A	`conf`	Runtime Code Parallelization for On-Chip Multiprocessors. DATE Mahmut T. Kandemir, Wei Zhang, Mustafa Karaköy
2002	—	`conf`	Compiler-directed cache polymorphism. LCTES-SCOPES Jie S. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Hendra Saputra, Wei Zhang
2002	A*	`conf`	Compiler-directed instruction cache leakage optimization. MICRO Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin
2001	A*	`conf`	Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. MICRO Wei Zhang, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai