Wei Shi - RankMe

25 papers A* 2A 1Journal 9Unranked 13

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	An Energy-Efficient and Artifact-Resilient ASIC for Simultaneous Neural Recording and Optogenetic Stimulation. IEEE Trans. Biomed. Circuits Syst. Linran Zhao, Yan Gong, Raymond G. Stephany, Wei Shi, Wen Li, Yaoyao Jia
2025	—	`conf`	MOTTO: A Mixture-of-Experts Framework for Multi-Treatment, Multi-Outcome Treatment Effect Estimation. KDD (2) Yiling Liu, Wei Shi, Chen Fu, Ziyang Jiang, Zhigang Hua, David E. Carlson
2025	J	`jnl`	NeuroFlare: An mm IEEE J. Solid State Circuits Linran Zhao, Yan Gong, Xiang Liu, Wei Shi, Yiming Han, Wen Li, Yaoyao Jia
2025	—	`conf`	Session-Level Dynamic Ad Load Optimization using Offline Robust Reinforcement Learning. KDD (1) Tao Liu, Qi Xu, Wei Shi, Zhigang Hua, Shuang Yang
2025	J	`jnl`	Synergizing Deconfounding and Temporal Generalization For Time-series Counterfactual Outcome Estimation. CoRR Yiling Liu, Juncheng Dong, Chen Fu, Wei Shi, Ziyang Jiang, Zhigang Hua, David E. Carlson
2024	—	`conf`	33.9 A Miniature Neural Interface Implant with a 95% Charging Efficiency Optical Stimulator and an 81.9dB SNDR ΔΣM-Based Recording Frontend. ISSCC Linran Zhao, Wei Shi, Yan Gong, Xiang Liu, Wen Li, Yaoyao Jia
2024	A	`conf`	Ads Supply Personalization via Doubly Robust Learning. CIKM Wei Shi, Chen Fu, Qi Xu, Sanjian Chen, Jizhe Zhang, Qinqin Zhu, Zhigang Hua, Shuang Yang
2024	A*	`conf`	PVTSizing: A TuRBO-RL-Based Batch-Sampling Optimization Framework for PVT-Robust Analog Circuit Synthesis. DAC Zichen Kong, Xiyuan Tang, Wei Shi, Yiheng Du, Yibo Lin, Yuan Wang
2023	J	`jnl`	A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier. IEEE J. Solid State Circuits Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Zongnan Wang, Wei Shi, David Z. Pan, Nan Sun
2023	—	`conf`	A Wireless Implantable Opto-Electro Neural Interface ASIC for Simultaneous Neural Recording and Stimulation. CICC Linran Zhao, Yan Gong, Wei Shi, Raymond Stephany, Wen Li, Yaoyao Jia
2022	—	`conf`	A 0.37mm CICC Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, Raviteja Theertham, Shanthi Pavan, Lu Jie, Nan Sun
2022	J	`jnl`	An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ahmet Faruk Budak, Miguel Gandara, Wei Shi, David Z. Pan, Nan Sun, Bo Liu
2022	—	`conf`	Generative-Adversarial-Network-Guided Well-Aware Placement for Analog Circuits. ASP-DAC Keren Zhu, Hao Chen, Mingjie Liu, Xiyuan Tang, Wei Shi, Nan Sun, David Z. Pan
2022	—	`conf`	RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL. MLCAD Wei Shi, Hanrui Wang, Jiaqi Gu, Mingjie Liu, David Z. Pan, Song Han, Nan Sun
2022	J	`jnl`	RobustAnalog: Fast Variation-Aware Analog Circuit Design Via Multi-task RL. CoRR Wei Shi, Hanrui Wang, Jiaqi Gu, Mingjie Liu, David Z. Pan, Song Han, Nan Sun
2021	—	`conf`	10.4 A 3.7mW 12.5MHz 81dB-SNDR 4th-Order CTDSM with Single-OTA and 2nd-Order NS-SAR. ISSCC Wei Shi, Jiaxin Liu, Abhishek Mukherjee, Xiangxing Yang, Xiyuan Tang, Linxiao Shen, Wenda Zhao, Nan Sun
2021	—	`conf`	A 0.4-to-40MS/s 75.7dB-SNDR Fully Dynamic Event-Driven Pipelined ADC with 3-Stage Cascoded Floating Inverter Amplifier. ISSCC Xiyuan Tang, Xiangxing Yang, Jiaxin Liu, Wei Shi, David Z. Pan, Nan Sun
2021	—	`conf`	A 79dB-SNDR 167dB-FoM Bandpass ΔΣ ADC Combining N-Path Filter with Noise-Shaping SAR. ISSCC Linxiao Shen, Zijie Gao, Xiangxing Yang, Wei Shi, Nan Sun
2020	—	`conf`	9.5 A 13.5b-ENOB Second-Order Noise-Shaping SAR with PVT-Robust Closed-Loop Dynamic Amplifier. ISSCC Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, David Z. Pan, Nan Sun
2020	J	`jnl`	A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier. IEEE J. Solid State Circuits Xiyuan Tang, Xiangxing Yang, Wenda Zhao, Chen-Kai Hsu, Jiaxin Liu, Linxiao Shen, Abhishek Mukherjee, Wei Shi, Shaolan Li, David Z. Pan, Nan Sun
2020	J	`jnl`	An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier. IEEE J. Solid State Circuits Xiyuan Tang, Linxiao Shen, Begum Kasap, Xiangxing Yang, Wei Shi, Abhishek Mukherjee, David Z. Pan, Nan Sun
2020	A*	`conf`	Closing the Design Loop: Bayesian Optimization Assisted Hierarchical Analog Layout Synthesis. DAC Mingjie Liu, Keren Zhu, Xiyuan Tang, Biying Xu, Wei Shi, Nan Sun, David Z. Pan
2019	—	`conf`	A 0.01mm ISSCC Linxiao Shen, Yi Shen, Xiyuan Tang, Chen-Kai Hsu, Wei Shi, Shaolan Li, Wenda Zhao, Abhishek Mukherjee, Nan Sun
2019	J	`jnl`	A Two-Step ADC With a Continuous-Time SAR-Based First Stage. IEEE J. Solid State Circuits Linxiao Shen, Nan Sun, Yi Shen, Zhelu Li, Wei Shi, Xiyuan Tang, Shaolan Li, Wenda Zhao, Mantian Zhang, Zhangming Zhu
2019	—	`conf`	An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier. VLSI Circuits Xiyuan Tang, Begum Kasap, Linxiao Shen, Xiangxing Yang, Wei Shi, Nan Sun