Wei Mao

49 papers A 4C 1Journal 21Unranked 23
YearRankTypeTitle / Venue / Authors
2026 J jnl
Collaborative Design of FeRAM via a Joint Ferroelectric Device and Circuit Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Bo Li, Junfeng Tan, Can Liu, Kai Chen, Tingjie Yang, Huanning Zhang, Xueyang Bai, Wei Mao, Jiuren Zhou, Xiao Yu, Ran Cheng, Guoyong Shi, Bing Chen, Yan Liu, Genquan Han
2025 A conf
A 20.98TOPS/W Energy-Efficient Binary BERT Model on Group Vector Systolic CIM Accelerator.
ISLPED
Dingbang Liu, Ziyi Guan, Qilong Chen, Jingyun Gu, Jiaqi Yang, Kai Li, Wei Mao, Ngai Wong, Changwen Chen, Hao Yu
2025 J jnl
A 28-nm 135.19 TOPS/W Bootstrapped-SRAM Compute-in-Memory Accelerator With Layer-Wise Precision and Sparsity.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wei Mao, Dingbang Liu, Haoxiang Zhou, Fuyi Li, Kai Li, Qiuping Wu, Jiaqi Yang, Quan Cheng, Liuyang Zhang, Hao Yu
2025 — conf
A Layer-wised Mixed-Precision CIM Accelerator with Bit-level Sparsity-aware ADCs for NAS-Optimized CNNs.
ASP-DAC
Haoxiang Zhou, Zikun Wei, Dingbang Liu, Liuyang Zhang, Chenchen Ding, Jiaqi Yang, Wei Mao, Hao Yu
2025 J jnl
A parallel computing-in-memory accelerator utilizing FeRAM array with retention loss correction.
Sci. China Inf. Sci.
Can Liu, Zhihao Shen, Wei Mao, Bo Li, Xiaomeng Lv, Fuyi Li, Peng Xiao, Haiqiao Hong, Shirui Zhao, Siying Zheng, Xiaoxi Li, Xiao Yu, Jiuren Zhou, Bing Chen, Yan Liu, Genquan Han
2025 — conf
Circuit-Agent: A Large Language Model Based Circuit Agent Framework for Analog/Mixed-signal Circuit Design Automation.
AICAS
Tingjie Yang, Bo Li, Yongfu Li, Wei Mao, Genquan Han
2025 — conf
Hardware-Aware Optimization of Large Language Models for Enhanced Throughput on Arm CPUs.
AICAS
Xingyu Zhu, Longhao Chen, Cheng Zhang, Pengcheng Yang, Tingjie Yang, Guosheng Yu, Evens Pan, Xiguang Wu, Bo Li, Wei Mao, Genquan Han
2025 — conf
OPAMP-Free Ferroelectric Capacitive Computing-in-Memory Accelerator for Energy-Efficient Binary Neural Networks.
SOCC
Jingyun Gu, Can Liu, Yuqing Chen, Zhihao Shen, Wei Mao, Genquan Han, Lei He, Jiang Xu
2025 — conf
Optimizing Inference Performance for Large Language Models on ARMv9 Architecture.
AICAS
Longhao Chen, Cheng Zhang, Huiyuan Zhang, Chi Wang, Yina Zhao, Xiaoxi Li, Xiguang Wu, Wei Mao, Genquan Han
2024 J jnl
A Low-Power Charge-Domain Bit-Scalable Readout System for Fully-Parallel Computing-in-Memory Accelerators.
IEEE Trans. Circuits Syst. II Express Briefs
Wei Mao, Fuyi Li, Jun Liu, Rui Xiao, Kejie Huang, Yongfu Li, Hao Yu, Yan Liu, Genquan Han
2024 J jnl
A Low-Power DNN Accelerator With Mean-Error-Minimized Approximate Signed Multiplier.
IEEE Open J. Circuits Syst.
Laimin Du, Leibin Ni, Xiong Liu, Guanqi Peng, Kai Li, Wei Mao, Hao Yu
2024 J jnl
A Reconfigurable Processing Element for Multiple-Precision Floating/Fixed-Point HPC.
IEEE Trans. Circuits Syst. II Express Briefs
Boyu Li, Kai Li, Jiajun Zhou, Yuan Ren, Wei Mao, Hao Yu, Ngai Wong
2024 — conf
AICAS Grand Challenge 2024: Software and Hardware Co-optimization for General Large Language Model Inference on CPU.
AICAS
Junfeng Tan, Guosheng Yu, Jianing Li, Xiaohan Ma, Fang Bao, Evens Pan, David Bian, Yongfu Li, Yuan Du, Li Du, Bo Li, Wei Mao
2024 — conf
Accurate Charge-Domain Bootstrapped Computing-in-Memory SRAM Design with Wide Programmable Output Voltage Range.
SOCC
Fuyi Li, Yu Xia, Shuai Xiao, Pengcheng Yang, Xingyu Zhu, Bo Li, Jiuren Zhou, Genquan Han, Wei Mao
2024 J jnl
Chip-Based Electronic System for Quantum Key Distribution.
Entropy
Siyuan Zhang, Wei Mao, Shaobo Luo, Shihai Sun
2024 J jnl
V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation.
IEEE Open J. Circuits Syst.
Chao Wang, Yicong Shao, Jiajie Huang, Wangzilu Lu, Zhiwen Gu, Longfan Li, Yuhang Zhang, Jian Zhao, Wei Mao, Yongfu Li
2023 J jnl
A Low-Power Sparse Convolutional Neural Network Accelerator With Pre-Encoding Radix-4 Booth Multiplier.
IEEE Trans. Circuits Syst. II Express Briefs
Quan Cheng, Liuyao Dai, Mingqiang Huang, Ao Shen, Wei Mao, Masanori Hashimoto, Hao Yu
2023 J jnl
APCCAS 2022 Guest Editorial Special Issue Based on the 18th Asia Pacific Conference on Circuits and Systems.
IEEE Trans. Circuits Syst. I Regul. Pap.
Xiaojin Zhao, Hailong Jiao, Wei Mao
2023 — conf
Grand Challenge on Software and Hardware Co-Optimization for E-Commerce Recommendation System.
AICAS
Jianing Li, Jiabin Liu, Xingyuan Hu, Yuhang Zhang, Guosheng Yu, Shimeng Qian, Wei Mao, Li Du, Yongfu Li, Yuan Du
2023 — conf
RISC-V based Fully-Parallel SRAM Computing-in-Memory Accelerator with High Hardware Utilization and Data Reuse Rate.
AICAS
Haoxiang Zhou, Haiqiao Hong, Dingbang Liu, Hang Liu, Yu Xia, Kai Li, Jun Liu, Shaobo Luo, Wei Mao, Hao Yu
2023 — conf
V2Va: An Efficient Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation.
APCCAS
Yicong Shao, Chao Wang, Jiajie Huang, Wangzilu Lu, Zhiwen Gu, Longfan Li, Yuhang Zhang, Jian Zhao, Wei Mao, Yongfu Li
2022 J jnl
A 703.4-GOPs/W Binary SegNet Processor With Computing-Near-Memory Architecture for Road Detection.
IEEE Des. Test
Haoran Lyu, Fengwei An, Shirui Zhao, Wei Mao, Hao Yu
2022 J jnl
A Configurable Floating-Point Multiple-Precision Processing Element for HPC and AI Converged Computing.
IEEE Trans. Very Large Scale Integr. Syst.
Wei Mao, Kai Li, Quan Cheng, Liuyao Dai, Boyu Li, Xinang Xie, He Li, Longyang Lin, Hao Yu
2022 J jnl
A Fall Detection Network by 2D/3D Spatio-temporal Joint Models with Tensor Compression on Edge.
ACM Trans. Embed. Comput. Syst.
Shuwei Li, Changhai Man, Ao Shen, Ziyi Guan, Wei Mao, Shaobo Luo, Rumin Zhang, Hao Yu
2022 J jnl
A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap.
Mingqiang Huang, Yucen Liu, Changhai Man, Kai Li, Quan Cheng, Wei Mao, Hao Yu
2022 — conf
A Low-Power Approximate Multiplier with Sign-Focus Compressor and Error Compensation.
APCCAS
Laimin Du, Leibin Ni, Xiong Liu, Wei Mao, Hao Yu
2022 A conf
A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge.
DATE
Kai Li, Junzhuo Zhou, Yuhang Wang, Junyi Luo, Zhengke Yang, Shuxin Yang, Wei Mao, Mingqiang Huang, Hao Yu
2022 — conf
A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing.
AICAS
Kai Li, Junzhuo Zhou, Boyu Li, Shuxing Yang, Sixiao Huang, Shaobo Luo, Wei Mao, Hao Yu
2022 J jnl
A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing.
IEEE Trans. Circuits Syst. II Express Briefs
Kai Li, Wei Mao, Junzhuo Zhou, Boyu Li, Zhengke Yang, Shuxing Yang, Laimin Du, Sixiao Huang, Hao Yu
2022 J jnl
ANT-UNet: Accurate and Noise-Tolerant Segmentation for Pathology Image Processing.
ACM J. Emerg. Technol. Comput. Syst.
Yufei Chen, Tingtao Li, Qinming Zhang, Wei Mao, Nan Guan, Mei Tian, Hao Yu, Cheng Zhuo
2022 — conf
An Energy-Efficient Bit-Split-and-Combination Systolic Accelerator for NAS-Based Multi-Precision Convolution Neural Networks.
ASP-DAC
Liuyao Dai, Quan Cheng, Yuhang Wang, Gengbin Huang, Junzhuo Zhou, Kai Li, Wei Mao, Hao Yu
2022 J jnl
An Energy-Efficient Mixed-Bit CNN Accelerator With Column Parallel Readout for ReRAM-Based In-Memory Computing.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Dingbang Liu, Haoxiang Zhou, Wei Mao, Jun Liu, Yuliang Han, Changhai Man, Qiuping Wu, Zhiru Guo, Mingqiang Huang, Shaobo Luo, Mingsong Lv, Quan Chen, Hao Yu
2022 — conf
An Energy-Efficient Mixed-Bit ReRAM-based Computing-in-Memory CNN Accelerator with Fully Parallel Readout.
APCCAS
Dingbang Liu, Wei Mao, Haoxiang Zhou, Jun Liu, Qiuping Wu, Haiqiao Hong, Hao Yu
2022 J jnl
An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst.
Wei Mao, Liuyao Dai, Kai Li, Quan Cheng, Yuhang Wang, Laimin Du, Shaobo Luo, Mingqiang Huang, Hao Yu
2022 — conf
BaseFormer: Transformer based Base-Caller for Fast and Accurate Next Generation Sequencing.
EMBC
Shuwei Li, Zhiru Guo, Ao Shen, Zheqi Yu, Wei Mao, Shaobo Luo, Hao Yu
2022 — conf
Hierarchical DNN with Heterogeneous Computing Enabled High-Performance DNA Sequencing.
APCCAS
Shaobo Luo, Zhiyuan Xie, Gengxin Chen, Lei Cui, Mei Yan, Xiwei Huang, Shuwei Li, Changhai Man, Wei Mao, Hao Yu
2021 A conf
A Reconfigurable Multiple-Precision Floating-Point Dot Product Unit for High-Performance Computing.
DATE
Wei Mao, Kai Li, Xinang Xie, Shirui Zhao, He Li, Hao Yu
2021 A conf
A Video-based Fall Detection Network by Spatio-temporal Joint-point Model on Edge Devices.
DATE
Ziyi Guan, Shuwei Li, Yuan Cheng, Changhai Man, Wei Mao, Ngai Wong, Hao Yu
2021 — conf
Multiple-Precision Floating-Point Dot Product Unit for Efficient Convolution Computation.
AICAS
Kai Li, Wei Mao, Xinang Xie, Quan Cheng, Huan Xie, Zhenjiang Dong, Hao Yu
2020 — conf
Energy-Efficient Machine Learning Accelerator for Binary Neural Networks.
ACM Great Lakes Symposium on VLSI
Wei Mao, Zhihua Xiao, Peng Xu, Hongwei Ren, Dingbang Liu, Shirui Zhao, Fengwei An, Hao Yu
2019 J jnl
A 74-μW 11-Mb/s Wireless Vital Signs Monitoring SoC for Three-Lead ECG, Respiration Rate, and Body Temperature.
IEEE Trans. Biomed. Circuits Syst.
Yuxuan Luo, Kok-Hin Teng, Yongfu Li, Wei Mao, Yong Lian, Chun-Huat Heng
2019 J jnl
A Low Power 12-bit 1-kS/s SAR ADC for Biomedical Signal Processing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wei Mao, Yongfu Li, Chun-Huat Heng, Yong Lian
2018 J jnl
High Dynamic Performance Current-Steering DAC Design With Nested-Segment Structure.
IEEE Trans. Very Large Scale Integr. Syst.
Wei Mao, Yongfu Li, Chun-Huat Heng, Yong Lian
2017 — conf
A 93μW 11Mbps wireless vital signs monitoring SoC with 3-lead ECG, bio-impedance, and body temperature.
A-SSCC
Yuxuan Luo, Kok-Hin Teng, Yongfu Li, Wei Mao, Chun-Huat Heng, Yong Lian
2017 C conf
Zero-bias true random number generator using LFSR-based scrambler.
ISCAS
Wei Mao, Yongfu Li, Chun-Huat Heng, Yong Lian
2016 — conf
A fast transient LDO based on dual loop FVF with high PSRR.
APCCAS
Lei Wang, Wei Mao, Chundong Wu, Alan Chang, Yong Lian
2016 — conf
A self biased full range current sensor for buck regulator.
APCCAS
Chundong Wu, Wang Ling Goh, Wei Mao, Lei Wang, Yat-Hei Lam, Alan Chang, Yong Lian
2016 — conf
Dynamic mapping method for static and dynamic performance improvement on current-steering digital-to-analog converter.
APCCAS
Wei Mao, Yongfu Li, Chun-Huat Heng, Yong Lian
2014 — conf
An ultra-low voltage comparator with improved comparison time and reduced offset voltage.
APCCAS
Yongfu Li, Wei Mao, Zhe Zhang, Yong Lian