Wei Hwang - RankMe

114 papers A 5C 20Misc 3Journal 30Unranked 56

Year	Rank	Type	Title / Venue / Authors
2022	—	`conf`	Memory-Centric Fusion-based CNN Accelerator with 3D-NoC and 3D-DRAM. ISOCC Wei Lu, Pei-Yu Ge, Po-Tsang Huang, Hung-Ming Chen, Wei Hwang
2021	J	`jnl`	An Energy-Efficient 3D Cross-Ring Accelerator With 3D-SRAM Cubes for Hybrid Deep Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. Wei Lu, Po-Tsang Huang, Hung-Ming Chen, Wei Hwang
2021	—	`conf`	An Energy-Efficient Ring-Based CIM Accelerator using High-Linearity eNVM for Deep Neural Networks. ISOCC Po-Tsang Huang, Ting-Wei Liu, Wei Lu, Yu-Hsien Lin, Wei Hwang
2021	J	`jnl`	Energy-Efficient Accelerator Design With Tile-Based Row-Independent Compressed Memory for Sparse Compressed Convolutional Neural Networks. IEEE Open J. Circuits Syst. Po-Tsang Huang, I-Chen Wu, Chin-Yang Lo, Wei Hwang
2020	—	`conf`	Energy-Efficient Accelerator Design with 3D-SRAM and Hierarchical Interconnection Architecture for Compact Sparse CNNs. AICAS Chin-Yang Lo, Po-Tsang Huang, Wei Hwang
2020	—	`conf`	Hierarchical Active Voltage Regulation for Heterogeneous TSV 3D-ICs. SoCC Po-Tsang Huang, Tzung-Han Tsai, Po-Jen Yang, Wei Hwang, Hung-Ming Chen
2019	—	`conf`	28nm 0.3V 1W2R Sub-Threshold FIFO Memory for Multi-Sensor IoT Applications. SoCC Huan-Jan Tseng, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang
2019	—	`conf`	An Energy-Efficient Accelerator with Relative- Indexing Memory for Sparse Compressed Convolutional Neural Network. AICAS I-Chen Wu, Po-Tsang Huang, Chin-Yang Lo, Wei Hwang
2018	—	`conf`	0.4V Reconfigurable Near-Threshold TCAM in 28nm High-k Metal-Gate CMOS Process. SoCC Yun-Sheng Chan, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang
2018	—	`conf`	28nm near/sub-threshold dual-port FIFO memory for shared queues in multi-sensor applications. VLSI-DAT Yi-Chun Wu, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Wei-Chang Wang, Wei Hwang, Ching-Te Chuang
2017	J	`jnl`	A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. Shang-Lin Wu, Kuang-Yu Li, Po-Tsang Huang, Wei Hwang, Ming-Hsien Tu, Sheng-Chi Lung, Wei-Sheng Peng, Huan-Shun Huang, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang
2017	C	`conf`	An implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable μ-needle array and flexible interposer. ISCAS Po-Tsang Huang, Yu-Chieh Huang, Shang-Lin Wu, Yu-Chen Hu, Ming-Wei Lu, Ting-Wei Sheng, Fung-Kai Chang, Chun-Pin Lin, Nien-Shang Chang, Hung-Lieh Chen, Chi-Shi Chen, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou
2017	J	`jnl`	Digital Buck Converter With Switching Loss Reduction Scheme for Light Load Efficiency Enhancement. IEEE Trans. Very Large Scale Integr. Syst. Chung-Shiang Wu, Hui-Hsuan Lee, Po-Hung Chen, Wei Hwang
2017	J	`jnl`	Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes. IEEE Trans. Biomed. Circuits Syst. Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou
2017	—	`conf`	Wide-I/O 3D-staked DRAM controller for near-data processing system. VLSI-DAT Yu-Hsuan Lin, Shih-Fan Peng, Wei Hwang
2016	C	`conf`	An ultra-high-density 256-channel/25mm2 neural sensing microsystem using TSV-embedded neural probes. ISCAS Yu-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Yu-Chen Hu, Yan-Huei You, Ming Chen, Yan-Yu Huang, Hsiao-Chun Chang, Yen-Han Lin, Jeng-Ren Duann, Tzai-Wen Chiu, Wei Hwang, Kuan-Neng Chen, Ching-Te Chuang, Jin-Chern Chiou
2016	—	`conf`	Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application. SoCC Ming Chen, Po-Tsang Huang, Shang-Lin Wu, Wei Hwang, Ching-Te Chuang
2015	—	`conf`	All digitally controlled linear voltage regulator with PMOS strength self-calibration for ripple reduction. VLSI-DAT Yi-Ping Kuo, Po-Tsang Huang, Chung-Shiang Wu, Yu-Jie Liang, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang
2015	C	`conf`	An all-digital power management unit with 90% power efficiency and ns-order voltage transition time for DVS operation in low power sensing SoC applications. ISCAS Chung-Shiang Wu, Kai-Chun Lin, Yi-Ping Kuo, Po-Hung Chen, Yuan-Hua Chu, Wei Hwang
2015	—	`conf`	Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology. CICC Henry Hsieh, Sang H. Dhong, Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, Ping-Lin Yang, Kevin Huang, Min-Jer Wang, Wei Hwang
2015	—	`conf`	Energy-efficient gas recognition system with event-driven power control. SoCC Chun-Ying Huang, Po-Tsang Huang, Chih-Chao Yang, Ching-Te Chuang, Wei Hwang
2015	—	`conf`	Low power algorithm-architecture co-design of fast Independent Component Analysis (FICA) for multi-gas sensor applications. VLSI-DAT Chih-Chao Yang, Po-Tsang Huang, Chun-Ying Huang, Ching-Te Chuang, Wei Hwang
2014	—	`conf`	0.339fJ/bit/search energy-efficient TCAM macro design in 40nm LP CMOS. A-SSCC Po-Tsang Huang, Shu-Lin Lai, Ching-Te Chuang, Wei Hwang, Jason Huang, Angelo Hu, Paul Kan, Michael Jia, Kimi Lv, Bright Zhang
2014	—	`conf`	18.6 2.5D heterogeneously integrated bio-sensing microsystem for multi-channel neural-sensing applications. ISSCC Po-Tsang Huang, Lei-Chun Chou, Teng-Chieh Huang, Shang-Lin Wu, Tang-Shuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Kuan-Neng Chen, Jin-Chern Chiou, Ching-Te Chuang, Wei Hwang, Kuo-Hua Chen, Chi-Tsung Chiu, Ming-Hsiang Cheng, Yueh-lung Lin, Ho-Ming Tong
2014	J	`jnl`	2.5D Heterogeneously Integrated Microsystem for High-Density Neural Sensing Applications. IEEE Trans. Biomed. Circuits Syst. Po-Tsang Huang, Shang-Lin Wu, Yu-Chieh Huang, Lei-Chun Chou, Teng-Chieh Huang, Tang-Hsuan Wang, Yu-Rou Lin, Chuan-An Cheng, Wen-Wei Shen, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Ho-Ming Tong
2014	—	`conf`	A 0.42V Vccmin ASIC-compatible pulse-latch solution as a replacement for a traditional master-slave flip-flop in a digital SOC. CICC Sang H. Dhong, Richard Guo, Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Kevin Huang, Min-Jer Wang, Wei Hwang
2014	—	`conf`	A 16kB tile-able SRAM macro prototype for an operating window of 4.8GHz at 1.12V VDD to 10 MHz at 0.5V in a 28-nm HKMG CMOS. CICC Ming-Zhang Kuo, Henry Hsieh, Sang H. Dhong, Ping-Lin Yang, Cheng-Chung Lin, Ryan Tseng, Kevin Huang, Min-Jer Wang, Wei Hwang
2014	J	`jnl`	A 40 nm 512 kb Cross-Point 8 T Pipeline SRAM With Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist. IEEE Trans. Circuits Syst. I Regul. Pap. Nan-Chun Lien, Li-Wei Chu, Chien-Hen Chen, Hao-I Yang, Ming-Hsien Tu, Paul-Sen Kan, Yong-Jyun Hu, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang
2014	C	`conf`	Energy-efficient configurable discrete wavelet transform for neural sensing applications. ISCAS Tang-Hsuan Wang, Po-Tsang Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang
2014	—	`conf`	Energy-efficient low-noise 16-channel analog-front-end circuit for bio-potential acquisition. VLSI-DAT Shang-Lin Wu, Po-Tsang Huang, Teng-Chieh Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang
2014	J	`jnl`	Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors. IEEE Trans. Circuits Syst. II Express Briefs Dao-Ping Wang, Hon-Jarn Lin, Ching-Te Chuang, Wei Hwang
2014	—	`conf`	PVT-aware digital controlled voltage regulator design for ultra-low-power (ULP) DVFS systems. SoCC Pei-Chen Wu, Yi-Ping Kuo, Chung-Shiang Wu, Ching-Te Chuang, Yuan-Hua Chu, Wei Hwang
2014	—	`conf`	Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video. SoCC Chih-Yuan Chang, Po-Tsang Huang, Yi-Chun Chen, Tian-Sheuan Chang, Wei Hwang
2013	—	`conf`	A 40nm 1.0Mb 6T pipeline SRAM with digital-based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS tracking and Adaptive Voltage Detector for boosting control. SoCC Wei-Nan Liao, Nan-Chun Lien, Chi-Shin Chang, Li-Wei Chu, Hao-I Yang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Hsien Tu, Huan-Shun Huang, Jian-Hao Wang, Paul-Sen Kan, Yong-Jyun Hu
2013	C	`conf`	A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist. ISCAS Chi-Shin Chang, Hao-I Yang, Wei-Nan Liao, Yi-Wei Lin, Nan-Chun Lien, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun Huang, Yong-Jyun Hu, Paul-Sen Kan, Cheng-Yo Cheng, Wei-Chang Wang, Jian-Hao Wang, Kuen-Di Lee, Chia-Cheng Chen, Wei-Chiang Shih
2013	J	`jnl`	A Two-Write and Two-Read Multi-Port SRAM with Shared Write Bit-Line Scheme and Selective Read Path for Low Power Operation. J. Low Power Electron. Dao-Ping Wang, Hon-Jarn Lin, Wei Hwang
2013	—	`conf`	A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range. SoCC Mei-Wei Chen, Ming-Hung Chang, Pei-Chen Wu, Yi-Ping Kuo, Chun-Lin Yang, Yuan-Hua Chu, Wei Hwang
2013	—	`conf`	Area-power-efficient 11-bit SAR ADC with delay-line enhanced tuning for neural sensing applications. BioCAS Teng-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang, Wei Hwang
2013	—	`conf`	Low temperature (<180 °C) bonding for 3D integration. 3DIC Yan-Pin Huang, Ruoh-Ning Tzeng, Yu-San Chien, Ming-Shaw Shy, Teu-Hua Lin, Kuo-Hua Chen, Ching-Te Chuang, Wei Hwang, Chi-Tsung Chiu, Ho-Ming Tong, Kuan-Neng Chen
2013	C	`conf`	Near-/Sub-Vth process, voltage, and temperature (PVT) sensors with dynamic voltage selection. ISCAS Ming-Hung Chang, Shang-Yuan Lin, Pei-Chen Wu, Olesya Zakoretska, Ching-Te Chuang, Kuan-Neng Chen, Chen-Chao Wang, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang
2013	—	`conf`	Through-silicon-via-based double-side integrated microsystem for neural sensing applications. ISSCC Chih-Wei Chang, Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Shih-Wei Lee, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Yen-Chi Lee, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong
2012	J	`jnl`	A 0.33-V, 500-kHz, 3.94-µW 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist. IEEE Trans. Circuits Syst. II Express Briefs Chien-Yu Lu, Ming-Hsien Tu, Hao-I Yang, Ya-Ping Wu, Huan-Shun Huang, Yuh-Jiun Lin, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang
2012	J	`jnl`	A 0.4 V 520 nW 990 J. Low Power Electron. Ming-Hung Chang, Shang-Yuan Lin, Wei Hwang
2012	—	`conf`	A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs. VLSI-DAT Wei-Hung Du, Po-Tsang Huang, Ming-Hung Chang, Wei Hwang
2012	J	`jnl`	A 45 nm 10T Dual-Port SRAM with Shared Bit-Line Scheme for Low Power Operation. J. Low Power Electron. Dao-Ping Wang, Wei Hwang
2012	A	`conf`	A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist. ISLPED Yi-Wei Lin, Hao-I Yang, Geng-Cing Lin, Chi-Shin Chang, Ching-Te Chuang, Wei Hwang, Chia-Cheng Chen, Willis Shih, Huan-Shun Huang
2012	—	`conf`	A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist. SoCC Yung-Wei Lin, Hao-I Yang, Mao-Chih Hsia, Yi-Wei Lin, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
2012	J	`jnl`	All Digital Linear Voltage Regulator for Super- to Near-Threshold Operation. IEEE Trans. Very Large Scale Integr. Syst. Wei-Chih Hsieh, Wei Hwang
2012	—	`conf`	An all-digital Read Stability and Write Margin characterization scheme for CMOS 6T SRAM array. VLSI-DAT Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih
2012	—	`conf`	An energy-efficient level converter with high thermal variation immunity for sub-threshold to super-threshold operation. SoCC Mei-Wei Chen, Ming-Hung Chang, Yuan-Hua Chu, Wei Hwang
2012	J	`jnl`	Design and Iso-Area V IEEE Trans. Circuits Syst. II Express Briefs Ming-Hung Chang, Yi-Te Chiu, Wei Hwang
2012	—	`conf`	Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array. VLSI-DAT Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kuen-Di Lee, Shyh-Jye Jou, Ching-Te Chuang, Wei Hwang
2012	C	`conf`	High-performance 0.6V VMIN 55nm 1.0Mb 6T SRAM with adaptive BL bleeder. ISCAS Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
2012	—	`conf`	On-chip self-calibrated process-temperature sensor for TSV 3D integration. SoCC Tzu-Ting Chiang, Po-Tsang Huang, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Wei Hwang
2012	J	`jnl`	Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks. J. Electr. Comput. Eng. Po-Tsang Huang, Wei Hwang
2012	C	`conf`	Substrate noise suppression technique for power integrity of TSV 3D integration. ISCAS Po-Jen Yang, Po-Tsang Huang, Wei Hwang
2011	A	`conf`	A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS. ISLPED Ming-Hung Chang, Yi-Te Chiu, Shu-Lin Lai, Wei Hwang
2011	J	`jnl`	A 65 nm 0.165 fJ/Bit/Search 256 , ˟, 144 TCAM Macro Design for IPv6 Lookup Tables. IEEE J. Solid State Circuits Po-Tsang Huang, Wei Hwang
2011	—	`conf`	A high-performance low VMIN 55nm 512Kb disturb-free 8T SRAM with adaptive VVSS control. SoCC Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, Chih-Chiang Hsu
2011	J	`jnl`	Adaptive Power Control Technique on Power-Gated Circuitries. IEEE Trans. Very Large Scale Integr. Syst. Wei-Chih Hsieh, Wei Hwang
2011	—	`conf`	An energy-efficient 10T SRAM-based FIFO memory operating in near-/sub-threshold regions. SoCC Wei-Hung Du, Ming-Hung Chang, Hao-Yi Yang, Wei Hwang
2011	J	`jnl`	Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices. IEEE Trans. Very Large Scale Integr. Syst. Hao-I Yang, Wei Hwang, Ching-Te Chuang
2011	J	`jnl`	Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM. IEEE Trans. Circuits Syst. I Regul. Pap. Hao-I Yang, Shyh-Chyi Yang, Wei Hwang, Ching-Te Chuang
2011	J	`jnl`	Impacts of gate-oxide breakdown on power-gated SRAM. Microelectron. J. Hao-I Yang, Wei Hwang, Ching-Te Chuang
2011	A	`conf`	Near-/sub-threshold DLL-based clock generator with PVT-aware locking range compensation. ISLPED Ming-Hung Chang, Chung-Ying Hsieh, Mei-Wei Chen, Wei Hwang
2011	—	`conf`	On-demand memory sub-system for multi-core SoCs. SoCC Po-Tsang Huang, Yung Chang, Wei Hwang
2011	J	`jnl`	Two-Level FIFO Buffer Design for Routers in On-Chip Interconnection Networks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Po-Tsang Huang, Wei Hwang
2010	J	`jnl`	A Low Power Differential Cascode Voltage Switch with Pass Gate Pulsed Latch for Viterbi Decoder. J. Low Power Electron. Po-Tsang Huang, Xin-Ru Lee, Hsie-Chia Chang, Chen-Yi Lee, Wei Hwang
2010	C	`conf`	Fully on-chip temperature, process, and voltage sensors. ISCAS Shi-Wen Chen, Ming-Hung Chang, Wei-Chih Hsieh, Wei Hwang
2010	—	`conf`	High efficiency power management system for solar energy harvesting applications. APCCAS Ming-Hung Chang, Jung-Yi Wu, Wei-Chih Hsieh, Shang-Yuan Lin, You-Wei Liang, Wei Hwang
2010	C	`conf`	Low quiescent current variable output digital controlled voltage regulator. ISCAS Wei-Chih Hsieh, Wei Hwang
2010	—	`conf`	Power noise suppression technique using active decoupling capacitor for TSV 3D integration. SoCC Tien-Hung Lin, Po-Tsang Huang, Wei Hwang
2009	—	`conf`	A 2.1-mW 0.3V-1.0V wide locking range multiphase DLL using self-estimated SAR algorithm. SoCC Yi-Ming Chang, Ming-Hung Chang, Wei Hwang
2009	—	`conf`	An adaptive congestion-aware routing algorithm for mesh network-on-chip platform. SoCC Po-Tsang Huang, Wei Hwang
2009	C	`conf`	Impacts of NBTI and PBTI on Power-gated SRAM with High-k Metal-gate Devices. ISCAS Hao-I Yang, Ching-Te Chuang, Wei Hwang
2008	C	`conf`	"Green" micro-architecture and circuit co-design for ternary content addressable memory. ISCAS Po-Tsang Huang, Shu-Wei Chang, Wen-Yen Liu, Wei Hwang
2008	—	`conf`	A 300-mV 36-muW multiphase dual digital clock output generator with self-calibration. SoCC Ming-Hung Chang, Li-Pu Chuang, I-Ming Chang, Wei Hwang
2008	C	`conf`	A 5.2mW all-digital fast-lock self-calibrated multiphase delay-locked loop. ISCAS Li-Pu Chuang, Ming-Hung Chang, Po-Tsang Huang, Chih-Hao Kan, Wei Hwang
2008	—	`conf`	A fully-differential subthreshold SRAM cell with auto-compensation. APCCAS Mu-Tien Chang, Wei Hwang
2008	—	`conf`	A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. SoCC Mu-Tien Chang, Po-Tsang Huang, Wei Hwang
2008	—	`conf`	In-situ self-aware adaptive power control system with multi-mode power gating network. SoCC Wei-Chih Hsieh, Wei Hwang
2008	—	`conf`	Low Power and Reliable Interconnection with Self-Corrected Green Coding Scheme for Network-on-Chip. NOCS Po-Tsang Huang, Wei-Li Fang, Yin-Ling Wang, Wei Hwang
2008	—	`conf`	Low-power floating bitline 8-T SRAM design with write assistant circuits. SoCC Hao-I Yang, Ssu-Yun Lai, Wei Hwang
2007	C	`conf`	A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock Generation. ISCAS Ming-Hung Chang, Zong-Xi Yang, Wei Hwang
2007	—	`conf`	A 65nm low power 2T1D embedded DRAM with leakage current reduction. SoCC Mu-Tien Chang, Po-Tsang Huang, Wei Hwang
2007	—	`conf`	A flexible two-layer external memory management for H.264/AVC decoder. SoCC Chang-Hsuan Chang, Ming-Hung Chang, Wei Hwang
2007	C	`conf`	Low Power On-Chip Current Monitoring Medium-Grained Adaptive Voltage Control. ISCAS Wei-Chih Hsieh, Wei Hwang
2006	C	`conf`	2-level FIFO architecture design for switch fabrics in network-on-chip. ISCAS Po-Tsang Huang, Wei Hwang
2006	C	`conf`	A 1.7mW all digital phase-locked loop with new gain generator and low power DCO. ISCAS Tzu-Chiang Chao, Wei Hwang
2006	—	`conf`	A Low-Power Reconfigurable Mixed-Radix FFT/IFFT Processor. APCCAS Chi-Chen Lai, Wei Hwang
2006	C	`conf`	A noise-tolerant matchline scheme with XOR-based conditional keeper for energy-efficient TCAM. ISCAS Chung-Hsien Hua, Chi-Wei Peng, Wei Hwang
2006	—	`conf`	Low Power Pre-Comparison Scheme for NOR-Type 10T Content Addressable Memory. APCCAS Po-Tsang Huang, Wei-Keng Chang, Wei Hwang
2006	—	`conf`	On-Chip DC-DC Converter with Frequency Detector for Dynamic Voltage Scaling Technology. APCCAS Jen-Wei Yang, Po-Tsang Huang, Wei Hwang
2005	—	`conf`	Distributed data-retention power gating techniques for column and row co-controlled embedded SRAM. MTDT Chung-Hsien Hua, Tung-Shuan Cheng, Wei Hwang
2005	—	`conf`	Noise-tolerant XOR-based conditional keeper for high fan-in dynamic circuits. ISCAS (1) Chung-Hsien Hua, Wei Hwang, Chih-Kai Chen
2004	J	`jnl`	Power Reduction Technique in Coefficient Multiplications Through Multiplier Characterization. J. VLSI Signal Process. Sangjin Hong, Shu-Shin Chin, Suhwan Kim, Wei Hwang
2003	J	`jnl`	Low-power circuits and technology for wireless digital systems. IBM J. Res. Dev. Stephen V. Kosonocky, Azeez J. Bhavnagarwala, Kenneth Chin, George Gristede, Anne-Marie Haen, Wei Hwang, Mark B. Ketchen, Suhwan Kim, Daniel R. Knebel, Kevin W. Warren, Victor V. Zyuban
2002	—	`conf`	Multiplier architecture power consumption characterization for low-power DSP applications. ICECS Sangjin Hong, Shu-Shin Chin, Suhwan Kim, Wei Hwang
2001	Misc	`conf`	Design Of Provably Correct Storage Arrays. VLSI Design Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann
2001	A	`conf`	Mixed multi-threshold differential cascode voltage switch (MT-DCVS) circuit styles and strategies for low power VLSI design. ISLPED W. Chen, Wei Hwang, Prabhakar Kudva, George Gristede, Stephen V. Kosonocky, Rajiv V. Joshi
2001	—	`conf`	SOI for asynchronous dynamic circuits. ACM Great Lakes Symposium on VLSI Rajiv V. Joshi, Wei Hwang, Ching-Te Chuang
2000	A	`conf`	"Cool low power" 1GHz multi-port register file and dynamic latch in 1.8 V, 0.25 mum SOI and bulk technology (poster session). ISLPED Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ching-Te Chuang
2000	Misc	`conf`	A Low Power 900 MHz Register File (8 Ports, 32 Words x 64 Bits) in 1.8V, 0.25µm SOI Technology. VLSI Design Rajiv V. Joshi, Wei Hwang, S. C. Wilson, Ghavam V. Shahidi, Ching-Te Chuang
2000	—	`conf`	A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications. ACM Great Lakes Symposium on VLSI George Gristede, Wei Hwang
2000	J	`jnl`	A scannable pulse-to-static conversion register array for self-timed circuits. IEEE J. Solid State Circuits Wei Hwang, Rajiv V. Joshi, George Gristede
1999	J	`jnl`	A 500-MHz, 32-word×64-bit, eight-port self-resetting CMOS register file. IEEE J. Solid State Circuits Wei Hwang, Rajiv V. Joshi, Walter H. Henkels
1999	Misc	`conf`	Design Considerations and Implementation of a High Performance Dynamic Register File. VLSI Design Rajiv V. Joshi, Wei Hwang
1999	J	`jnl`	Implementation of a self-resetting CMOS 64-bit parallel adder with enhanced testability. IEEE J. Solid State Circuits Wei Hwang, George Diedrich Gristede, Pia N. Sanda, Shao Y. Wang, David F. Heidel
1998	—	`conf`	Design and implementation of high performance dynamic 64-bit parallel adder with enhanced testability. CICC Wei Hwang, George Diedrich Gristede, Pia N. Sanda, Shao Y. Wang, David F. Heidel
1997	C	`conf`	A Pulse-To-Static Conversion Latch with a Self-Timed Control Circuit. ICCD Wei Hwang, Rajiv V. Joshi, Walter H. Henkels
1997	J	`jnl`	Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems. IEEE J. Solid State Circuits Fang-shi Lai, Wei Hwang
1997	C	`conf`	Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, Toshiaki Kirihata, Akashi Satoh, Seiji Munetoh, Hing Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi
1994	J	`jnl`	Large-signal 2T, 1C DRAM cell: signal and layout analysis. IEEE J. Solid State Circuits Walter H. Henkels, Wei Hwang
1988	J	`jnl`	High-speed sensing scheme for CMOS DRAMs. IEEE J. Solid State Circuits Sang H. Dhong, Nicky Chau-Chun Lu, Wei Hwang, Stephen A. Parke