Wei He - RankMe

37 papers A* 1A 1C 2Misc 1Journal 20Unranked 12

Year	Rank	Type	Title / Venue / Authors
2025	J	`jnl`	A Scalable Private Data Alignment Scheme for Arbitrary Participants Using Oblivious PRF. IEEE Internet Things J. Yuhan Yang, Qian Xu, Wei He, Nandi Shi, Huajie Shen, Bo Yu, Lijun Wei, Jing Wu, Chengnian Long
2025	J	`jnl`	Bootstrapping in approximate fully homomorphic encryption: a research survey. Cybersecur. Huajie Shen, Qian Xu, Bo Yu, Yuhan Yang, Wei He
2025	J	`jnl`	Efficient two-party Private Set Union and circuit-based version for large-scale data set based on novel oblivious filter. J. Syst. Archit. Qian Xu, Huajie Shen, Yuhan Yang, Bo Yu, Wei He
2025	J	`jnl`	Privacy-Preserving Large-Scale Set Intersection: An Efficient Method With Enhanced Security. IEEE Internet Things J. Yuhan Yang, Qian Xu, Huajie Shen, Bo Yu, Wei He, Lijun Wei, Jing Wu, Chengnian Long, Zhenheng Tang, Xiaowen Chu
2025	C	`conf`	Privacy-Preserving Transaction Chain Retrieval and Reconstruction for Collaborative Supervision. ICBC Yuhan Yang, Qian Xu, Huajie Shen, Bo Yu, Wei He, Lijun Wei, Jing Wu, Chengnian Long
2024	A	`conf`	HQsFL: A Novel Training Strategy for Constructing High-performance and Quantum-safe Federated Learning. AsiaCCS Bo Yu, Huajie Shen, Qian Xu, Wei He, Wankui Mao, Qing Zhang, Fan Zhang
2022	J	`jnl`	PipeFL: Hardware/Software co-Design of an FPGA Accelerator for Federated Learning. IEEE Access Zixiao Wang, Biyao Che, Liang Guo, Yang Du, Ying Chen, Jizhuang Zhao, Wei He
2021	J	`jnl`	Decentralized and expressive data publish-subscribe scheme in cloud based on attribute-based keyword search. J. Syst. Archit. Qian Xu, Qing Zhang, Bo Yu, Nandi Shi, Changshuai Wang, Wei He
2021	J	`jnl`	Pushing the Limit of PFA: Enhanced Persistent Fault Analysis on Block Ciphers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Guorui Xu, Fan Zhang, Bolin Yang, Xinjie Zhao, Wei He, Kui Ren
2020	J	`jnl`	Side-Channel Analysis and Countermeasure Design on ARM-Based Quantum-Resistant SIKE. IEEE Trans. Computers Fan Zhang, Bolin Yang, Xiaofei Dong, Sylvain Guilley, Zhe Liu, Wei He, Fangguo Zhang, Kui Ren
2018	J	`jnl`	Highly Scalable Deep Learning Training System with Mixed-Precision: Training ImageNet in Four Minutes. CoRR Xianyan Jia, Shutao Song, Wei He, Yangzihao Wang, Haidong Rong, Feihu Zhou, Liqiang Xie, Zhenyu Guo, Yuanzhou Yang, Liwei Yu, Tiegang Chen, Guangxiao Hu, Shaohuai Shi, Xiaowen Chu
2018	J	`jnl`	Persistent Fault Analysis on Block Ciphers. IACR Trans. Cryptogr. Hardw. Embed. Syst. Fan Zhang, Xiaoxuan Lou, Xinjie Zhao, Shivam Bhasin, Wei He, Ruyi Ding, Samiya Qureshi, Kui Ren
2018	J	`jnl`	The Conflicted Usage of RLUTs for Security-Critical Applications on FPGA. J. Hardw. Syst. Secur. Debapriya Basu Roy, Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Wei He, Debdeep Mukhopadhyay, Zakaria Najm, Xuan Thuy Ngo
2017	—	`conf`	An FPGA-compatible PLL-based sensor against fault injection attack. ASP-DAC Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata
2017	—	`conf`	An electromagnetic fault injection sensor using Hogge phase-detector. ISQED Jakub Breier, Shivam Bhasin, Wei He
2017	J	`jnl`	Attacks in Reality: the Limits of Concurrent Error Detection Codes Against Laser Fault Injection. J. Hardw. Syst. Secur. Jakub Breier, Wei He, Dirmanto Jap, Shivam Bhasin, Anupam Chattopadhyay
2017	J	`jnl`	Extensive Laser Fault Injection Profiling of 65 nm FPGA. J. Hardw. Syst. Secur. Jakub Breier, Wei He, Shivam Bhasin, Dirmanto Jap, Samuel Chef, Hock Guan Ong, Chee Lip Gan
2017	J	`jnl`	Low-cost design of stealthy hardware trojan for bit-level fault attacks on block ciphers. Sci. China Inf. Sci. Fan Zhang, Xinjie Zhao, Wei He, Shivam Bhasin, Shize Guo
2017	J	`jnl`	Multiple Fault Attack on PRESENT with a Hardware Trojan Implementation in FPGA. CoRR Jakub Breier, Wei He
2017	J	`jnl`	Stealthy Hardware Trojan Based Algebraic Fault Analysis of HIGHT Block Cipher. Secur. Commun. Networks Hao Chen, Tao Wang, Fan Zhang, Xinjie Zhao, Wei He, Lumin Xu, Yunfei Ma
2017	J	`jnl`	Transistor level SCA-resistant scheme based on fluctuating power logic. Sci. China Inf. Sci. Liang Geng, Fan Zhang, Jizhong Shen, Wei He, Shivam Bhasin, Xinjie Zhao, Shize Guo
2016	—	`conf`	Bypassing Parity Protected Cryptography using Laser Fault Injection in Cyber-Physical System. CPSS@AsiaCCS Wei He, Jakub Breier, Shivam Bhasin, Anupam Chattopadhyay
2016	—	`conf`	Cheap and Cheerful: A Low-Cost Digital Sensor for Detecting Laser Fault Injection Attacks. SPACE Wei He, Jakub Breier, Shivam Bhasin
2016	—	`conf`	Comprehensive Laser Sensitivity Profiling and Data Register Bit-Flips for Cryptographic Fault Attacks in 65 Nm FPGA. SPACE Wei He, Jakub Breier, Shivam Bhasin, Dirmanto Jap, Hock Guan Ong, Chee Lip Gan
2016	A*	`conf`	PLL to the rescue: a novel EM fault countermeasure. DAC Noriyuki Miura, Zakaria Najm, Wei He, Shivam Bhasin, Xuan Thuy Ngo, Makoto Nagata, Jean-Luc Danger
2016	C	`conf`	Ring Oscillator under Laser: Potential of PLL-based Countermeasure against Laser Fault Injection. FDTC Wei He, Jakub Breier, Shivam Bhasin, Noriyuki Miura, Makoto Nagata
2016	—	`conf`	Supervised and unsupervised machine learning for side-channel based Trojan detection. ASAP Dirmanto Jap, Wei He, Shivam Bhasin
2015	—	`conf`	Dual-rail active protection system against side-channel analysis in FPGAs. ASAP Wei He, Dirmanto Jap
2015	J	`jnl`	Exploiting FPGA Block Memories for Protected Cryptographic Implementations. ACM Trans. Reconfigurable Technol. Syst. Shivam Bhasin, Jean-Luc Danger, Sylvain Guilley, Wei He
2015	—	`conf`	Multiple Fault Attack on PRESENT with a Hardware Trojan Implementation in FPGA. SIoT Jakub Breier, Wei He
2015	Misc	`conf`	Process Variation Evaluation Using RO PUF for Enhancing SCA-Resistant Dual-Rail Implementation. WISA Wei He, Dirmanto Jap, Alexander Herrmann
2015	J	`jnl`	Sophisticated security verification on routing repaired balanced cell-based dual-rail logic against side channel analysis. IET Inf. Secur. Wei He, Shivam Bhasin, Andrés Otero, Tarik Graba, Eduardo de la Torre, Jean-Luc Danger
2014	J	`jnl`	Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic. Microprocess. Microsystems Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2013	—	`conf`	Exploiting FPGA block memories for protected cryptographic implementations. ReCoSoC Shivam Bhasin, Wei He, Sylvain Guilley, Jean-Luc Danger
2012	—	`conf`	An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation. COSADE Wei He, Eduardo de la Torre, Teresa Riesgo
2012	—	`conf`	Automatic generation of identical routing pairs for FPGA implemented DPL logic. ReConFig Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo
2011	—	`conf`	A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations. ReConFig Wei He, Eduardo de la Torre, Teresa Riesgo