Wei Deng - RankMe

138 papers C 7Journal 51Unranked 80

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	8.10 A 180-to-240Gb/s Analog-Intensive PAM-4 Transmitter with 0.70pJ/b Analog Power Efficiency in 65nm CMOS. ISSCC Ziyi Lin, Haikun Jia, Wei Deng, Shitu He, Chang Liu, Zhihua Wang, Baoyong Chi
2026	—	`conf`	A [email protected]@0.9V Deeply Power-Scalable Reconfigurable Series-Resonance/Class-F VCO with Mutual-Inductance Self-Cancellation and Hybrid 8-Shaped Coupling Techniques. ISSCC Juntao Lan, Wei Deng, Haikun Jia, Shiwei Zhang, Zhihua Wang, Baoyong Chi
2026	—	`conf`	A 7.15-to-7.95GHz Magnetically Enhanced Feedforward Waveform-Shaping CMOS Oscillator with Implicit Common-Mode Noise Cancellation Achieving -146.72 dBc/Hz PN@1MHz and 190.6dBc/Hz FoM. ISSCC Rui Ma, Wei Deng, Haikun Jia, Juntao Lan, Zhihua Wang, Baoyong Chi
2026	J	`jnl`	A Cycle-Slip Compensated FMCW Digital PLL With Background Back-Tracking DPD. IEEE J. Solid State Circuits Angxiao Yan, Wei Deng, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Zhihua Wang, Baoyong Chi
2026	J	`jnl`	A D-Band Distributed MIMO FMCW Radar CMOS Transceiver. IEEE J. Solid State Circuits Ruichen Wan, Wei Deng, Qixiu Wu, Haikun Jia, Rui Wu, Angxiao Yan, Haowen Cai, Sanming Hu, Zhihua Wang, Baoyong Chi
2025	—	`conf`	19.9 An 11-to-16.4GHz, 3.4GHz/µs-Slope, 5.32GHz-Chirp-Bandwidth, 0.043%-RMS-Frequency-Error FMCW Digital PLL with Posterior-Segment DPD Featuring 5-Chirp-Cycle Convergence Time. ISSCC Angxiao Yan, Wei Deng, Haikun Jia, Yumeng Yang, Chao Tang, Shiyan Sun, Zhihua Wang, Baoyong Chi
2025	—	`conf`	A 0.18-µs-Locking-Time Fractional-N PLL with Stochastic Gradient Descent Tuning Curve Fitting, Initial Phase Error Zeroing, and Random DSM Achieving 44.4-fs Jitter at Near-Integer Channel. CICC Hongzhuo Liu, Wei Deng, Haikun Jia, Baoyong Chi
2025	—	`conf`	A 104-to-132 GHz 16-way Power Amplifier Using Enhanced Magnetic Coupling Cavity Achieving 21.2 dBm Output Power in 28nm Bulk CMOS. CICC Ziyuan Guo, Wei Deng, Weiqi Zheng, Haikun Jia, Hongliang Wu, Qiuyu Peng, Fuyuan Zhao, Junyang Yin, Dongze Li, Baoyong Chi
2025	C	`conf`	A 112Gb/s Analog-MUX-based PAM-4 Transmitter with Inherent 2-tap FFE in 65nm CMOS. ISCAS Ziyi Lin, Haikun Jia, Shitu He, Wei Deng, Chang Liu, Ruiheng Qiu, Chen Wang, Baoyong Chi
2025	—	`conf`	A 22-to-32 GHz 4-Beam 32-Element Polarization Reconfigurable Fully-Connected Fully-Bidirectional MIMO Transceiver for Emerging Space-Air-Ground-Sea Integrated Network. CICC Junlong Gong, Wei Deng, Shulin Yao, Haikun Jia, Xinyu Jiang, Xiangyu Nie, Dongfang Li, Hongliang Wu, ChuanMing Zhu, Xiangrong Huang, Baoyong Chi
2025	—	`conf`	A 22.0-to-28.4GHz 192.2dBc/Hz FoM and 206.2dBc/Hz FoMA Dual-Core VCO Using Circular-Inverse-Class-F Topology Under Standard Supply Voltage in 65nm CMOS Process. CICC Huanyu Ge, Haikun Jia, Wei Deng, Baoyong Chi
2025	J	`jnl`	A 26-Gb/s 140-GHz OOK CMOS Transmitter and Receiver Chipset for High-Speed Wireless and Dielectric Waveguide Communication. IEEE J. Solid State Circuits Qiuyu Peng, Haikun Jia, Ran Fang, Pingda Guan, Mingxing Deng, Jiamin Xue, Wei Deng, Xin Liang, Baoyong Chi
2025	J	`jnl`	A Digital-Intensive 1TX/2RX IEEE 802.15.4/4z-Compliant Joint-Radar-Communication-Location Transceiver SoC. IEEE J. Solid State Circuits Bufan Zhu, Wei Deng, Ziying Huang, Haikun Jia, Haiyang Jia, Angxiao Yan, Yumeng Yang, Junfeng Liu, Yu Fu, Shiyan Sun, Chao Tang, Lixue Kuang, Lilan Yu, Yue Liu, Xin Liang, Zhihua Wang, Baoyong Chi
2025	J	`jnl`	A Ka-Band Multi-Beam Phased-Array Transmitter With Time-Modulation for PAPR Reduction and Physical Layer Security. IEEE J. Solid State Circuits Ruiyang Jiang, Haikun Jia, Xiangrong Huang, Wei Deng, ChuanMing Zhu, Xintao Li, Zhihua Wang, Baoyong Chi
2025	J	`jnl`	A Low-Spur and Low-Jitter Fractional Output Divider With Self-Adaption Frequency Filtering Technique. IEEE J. Solid State Circuits Yumeng Yang, Wei Deng, Angxiao Yan, Haikun Jia, Junlong Gong, Zhihua Wang, Baoyong Chi
2025	J	`jnl`	A Multi-Core Series-Resonance CMOS Oscillator. IEEE J. Solid State Circuits Shiwei Zhang, Wei Deng, Haikun Jia, Zhihua Wang, Baoyong Chi
2025	J	`jnl`	A Series-Parallel-Resonance Oscillator With a 191.5 dBc/Hz FoM. IEEE Solid State Circuits Lett. Shiwei Zhang, Wei Deng, Haikun Jia, Hongzhuo Liu, Junlong Gong, Qiuyu Peng, Baoyong Chi
2025	J	`jnl`	A Time-Domain Accuracy-Boosted Temperature Compensated Crystal Oscillator. IEEE J. Solid State Circuits Junyang Yin, Wei Deng, Haikun Jia, Sining Pan, Minshuo Wang, Tianyu Chen, Hongdong Zhong, Ziyuan Guo, Zhihua Wang, Baoyong Chi
2025	C	`conf`	A Total Noise Power Based Digital Calibration Method for Continuous-Time Delta-Sigma Modulators. ISCAS Zhuojian Yao, Haikun Jia, Lilan Yu, Junfeng Liu, Yu Fu, Wei Deng, Baoyong Chi
2025	J	`jnl`	A Transformer-Based Series-Resonance CMOS VCO. IEEE J. Solid State Circuits Shiwei Zhang, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiyan Sun, Pingda Guan, Zhihua Wang, Baoyong Chi
2025	J	`jnl`	An Ultra-Low-Jitter Fast-Hopping Fractional-N PLL With LC DTC and Hybrid-Proportional Paths. IEEE J. Solid State Circuits Hongzhuo Liu, Wei Deng, Haikun Jia, Zhihua Wang, Baoyong Chi
2024	—	`conf`	19.5 A 13.7-to-41.5GHz 214.1dBc/Hz FoMT Quad-Core Quad-Mode VCO Using an Oscillation-Mode-Splitting Technique. ISSCC Huanyu Ge, Haikun Jia, Wei Deng, Ruichang Ma, Zhihua Wang, Baoyong Chi
2024	J	`jnl`	28 GHz Compact LNAs With 1.9 dB Minimum NF Using Folded Three-Coil Transformer and Dual-Feedforward Techniques for Phased Array Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Xiangrong Huang, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi, Ziqiang Wang
2024	—	`conf`	A 130-to-170 GHz Reconfigurable Heterodyne/Homodyne Transceiver Achieving 20.5-dBm Psat for Emerging Integrated Wireless Access and Backhaul Networks. A-SSCC Qixiu Wu, Wei Deng, Ziyuan Guo, Haikun Jia, Taikun Ma, Qiuyu Peng, Chang Liu, Baoyong Chi
2024	—	`conf`	A 132-to-163 GHz 4TX/4RX Distributed MIMO FMCW Radar Transceiver with Real-Time Reference-Clock Synchronization Enabling Cooperative Coherent Multistatic Imaging System. VLSI Technology and Circuits Ruichen Wan, Wei Deng, Qixiu Wu, Haikun Jia, W. Rui, Angxiao Yan, Haowen Cai, Sanming Hu, Zhihua Wang, Baoyong Chi
2024	—	`conf`	A 194.9dBc/Hz FoM and 6.8-to-11.6GHz Quad-Core Dual-Mode Class-F VCO Featuring Wideband Flicker Noise Suppression. CICC Huanyu Ge, Haikun Jia, Wei Deng, Ruichang Ma, Baoyong Chi
2024	C	`conf`	A 24.3-to-44.8 GHz Reconfigurable Dual-Band T/R Front-End with An Implicit Switch-based Antenna Interface Supporting 600MSym/s 64QAM. ISCAS Junlong Gong, Wei Deng, Fuyuan Zhao, Haikun Jia, Wenjing Ye, Ruichen Wan, Baoyong Chi
2024	—	`conf`	A 3-to-40 GHz 64QAM/256QAM/4096QAM Zero-IF CMOS Transceiver Chipset for Millimeter-wave Software-defined Radios. A-SSCC Wenjing Ye, Wei Deng, Haikun Jia, Jingling Zhang, Linjun Gu, Fuyuan Zhao, Ruichen Wan, Baoyong Chi
2024	—	`conf`	A 48MHz Temperature Compensated Crystal Oscillator Utilizing Time-Domain Accuracy Boosting Techniques Achieving ±1.4ppm Frequency Stability from -55°C to 115°C. A-SSCC Junyang Yin, Wei Deng, Haikun Jia, Minshuo Wang, Baoyong Chi
2024	J	`jnl`	A Band-Shifting Millimeter-Wave T/R Front-End Using Inductance-Mutation Transformer Technique for Multiband Phased-Array Transceivers. IEEE J. Solid State Circuits Fuyuan Zhao, Wei Deng, Haikun Jia, Wenjing Ye, Ruichen Wan, Zhihua Wang, Baoyong Chi
2024	J	`jnl`	A Compact E-Band Load-Modulation Balanced Power Amplifier in 65-nm CMOS. IEEE J. Solid State Circuits Xiangrong Huang, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi
2024	J	`jnl`	A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces. IEEE J. Solid State Circuits Pingda Guan, Ruichang Ma, Haikun Jia, Wei Deng, Mingxing Deng, Jiamin Xue, Angxiao Yan, Shiyan Sun, Qiuyu Peng, Teerachot Siriburanon, Robert Bogdan Staszewski, Zhihua Wang, Baoyong Chi
2024	—	`conf`	A Fully-Connected Time-Modulated Phased-Array Transmitter Featuring Physical Security Directional Link and Multi-Beam PAPR Reduction. A-SSCC Xiangrong Huang, Haikun Jia, Wei Deng, ChuanMing Zhu, Ruiyang Jiang, Xintao Li, Zhihua Wang, Baoyong Chi
2024	J	`jnl`	A Low-Phase-Noise VCO With Common-Mode Resonance Expansion and Intrinsic Differential 2nd-Harmonic Output Based on a Single Three-Coil Transformer. IEEE J. Solid State Circuits Ziyi Lin, Haikun Jia, Ruichang Ma, Wei Deng, Zhihua Wang, Baoyong Chi
2024	J	`jnl`	A Multireference PLL: Theory and Implementation. IEEE J. Solid State Circuits Hongzhuo Liu, Wei Deng, Haikun Jia, Shiwei Zhang, Shiyan Sun, Zhihua Wang, Baoyong Chi
2024	—	`conf`	An 11.1-to-14.9GHz Digital-Integral Hybrid-Proportional Fractional-N PLL with an LC DTC Achieving 0.52μs Locking Time and 41.3f5 Jitter. CICC Hongzhuo Liu, Wei Deng, Haikun Jia, Baoyong Chi
2024	J	`jnl`	An Enhanced Class-F Dual-Core VCO With Common-Mode-Noise Self-Cancellation and Isolation Technique. IEEE J. Solid State Circuits Qixiu Wu, Wei Deng, Yaqian Sun, Haikun Jia, Hongzhuo Liu, Shiwei Zhang, Zhihua Wang, Baoyong Chi
2024	J	`jnl`	Correction to "A 4.4-GHz 193.2-dB FoM 8-Shaped-Inductor-Based LC-VCO Using Orthogonal-Coupled Triple-Coil Transformer". IEEE Trans. Circuits Syst. II Express Briefs Yaqian Sun, Wei Deng, Haikun Jia, Zhihua Wang, Baoyong Chi
2024	—	`conf`	INVITED PAPER: A 21.5-to-37 GHz Series Doherty CMOS Power Amplifier with Distributed Multi-step Impedance Inverting Network Achieving 28.2%/23.2%/13.2% Peak/OP1dB/6dBPBO PAEs. ICTA Xinyu Jiang, Wei Deng, Junlong Gong, Haikun Jia, Baoyong Chi
2023	—	`conf`	A 10-to-300MHz Fractional Output Divider with -80dBc Worst-Case Fractional Spurs Using Auxiliary-PLL-Based Background 0th/1 ISSCC Yumeng Yang, Wei Deng, Angxiao Yan, Haikun Jia, Junlong Gong, Zhihua Wang, Baoyong Chi
2023	—	`conf`	A 100 MHz-Reference, 10.3-to-11.1 GHz Quadrature PLL with 33.7-fsrms Jitter and -83.9 dBc Reference Spur Level using a -130.8 dBc/Hz Phase Noise at 1MHz offset Folded Series-Resonance VCO in 65nm CMOS. CICC Shiwei Zhang, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiyan Sun, Pingda Guan, Baoyong Chi
2023	J	`jnl`	A 24-30-GHz Four-Element Phased Array Transceiver With Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter for 5G Communication. IEEE Trans. Very Large Scale Integr. Syst. Xiangrong Huang, Haikun Jia, Shengnan Dong, Wei Deng, Zhihua Wang, Baoyong Chi
2023	—	`conf`	A 25.0-to-35.9GHz Dual-Layer Quad-Core Dual-Mode VCO with 189.1dBc/Hz FoM and 200.2dBc/Hz FoMT at 1MHz Offset in 65nm CMOS. CICC Pingda Guan, Haikun Jia, Wei Deng, Ruichang Ma, Huabing Liao, Zhihua Wang, Baoyong Chi
2023	—	`conf`	A 26.9-GHz 4-Element Code-Domain Hybrid Beamforming Phased-Array Receiver. A-SSCC Ziyi Lin, Haikun Jia, ChuanMing Zhu, Wei Deng, Huabing Liao, Bao Shi, Lujie Hao, Xiangrong Huang, Baoyong Chi
2023	—	`conf`	A 27-to-31.6 GHz 8-Element Phased-Array Transmitter Front-End with Inter-Element-Interference Cancellation Scheme in 65 nm CMOS. A-SSCC Dongze Li, Wei Deng, Xintao Li, Ruiheng Qiu, Haikun Jia, Xiangrong Huang, Ziyuan Guo, Baoyong Chi
2023	—	`conf`	A 37-to-41.8 GHz Double-Gm-Boosting LNA with 2.9-dB NFmin Using Quadruple-Coupling Transformer for Phased-Array Transceivers. ESSCIRC Dongze Li, Wei Deng, Haikun Jia, Ruiheng Qiu, Xintao Li, Ziyuan Guo, Baoyong Chi
2023	—	`conf`	A 4-Element 4-Beam Ka-Band Phased-Array Receiver Using Mesh Topology in 65 nm CMOS. A-SSCC Xiangrong Huang, Haikun Jia, Wei Deng, ChuanMing Zhu, Zhihua Wang, Xuzhi Liu, Zhiming Chen, Baoyong Chi
2023	—	`conf`	A 4.8-GHz Time-Interleaved Multi-Reference PLL with 16.1-fs Jitter. ESSCIRC Hongzhuo Liu, Wei Deng, Haikun Jia, Shiwei Zhang, Shiyan Sun, Baoyong Chi
2023	C	`conf`	A 6.5-to-8GHz IEEE 802.15.4z-compliant All-Digital UWB Transmitter with Integrated Fast-Settling Master-Slave Regulator. ISCAS Ziying Huang, Wei Deng, Haikun Jia, Bufan Zhu, Angxiao Yan, Baoyong Chi
2023	—	`conf`	A Compact E-Band Load-Modulation Balanced Power Amplifier Using Coupled Transmission-Line Output Network Achieving 22.1-dBm Psat and 34.9%/12.2% Efficiency at Psat/6-dB PBO. A-SSCC Xiangrong Huang, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi
2023	J	`jnl`	A Compact and Low Phase Noise Square-Geometry Quad-Core Class-F VCO Using Parallel Inductor-Sharing Technique. IEEE J. Solid State Circuits Yaqian Sun, Wei Deng, Haikun Jia, Yejun He, Zhihua Wang, Baoyong Chi
2023	J	`jnl`	A D-Band Joint Radar-Communication CMOS Transceiver. IEEE J. Solid State Circuits Wei Deng, Zipeng Chen, Haikun Jia, Pingda Guan, Taikun Ma, Angxiao Yan, Shiyan Sun, Xiangrong Huang, Guopei Chen, Ruichang Ma, Shengnan Dong, Luqiang Duan, Zhihua Wang, Baoyong Chi
2023	—	`conf`	A Fully Integrated Bit-to-Bit 24/48Gb/s QPSK/16-QAM D-Band Transceiver with Mixed-Signal Baseband in 28nm CMOS Technology. A-SSCC Pingda Guan, Haikun Jia, Wei Deng, Ruichang Ma, Mingxing Deng, Jiamin Xue, Angxiao Yan, Shiyan Sun, Zhihua Wang, Baoyong Chi
2023	J	`jnl`	A Low-Phase-Noise Quad-Core Millimeter-Wave Fundamental VCO Using Circular Triple-Coupled Transformer in 65-nm CMOS. IEEE J. Solid State Circuits Haikun Jia, Pingda Guan, Wei Deng, Zhihua Wang, Baoyong Chi
2023	—	`conf`	A Transient Enhancement Digital LDO with Adaptive Ripple Cancelation Based on Optimal Compensation Period Approximation. A-SSCC Angxiao Yan, Wei Deng, Haikun Jia, Shiwei Zhang, Baoyong Chi
2023	—	`conf`	An 11.4-to-16.4GHz FMCW Digital PLL with Cycle-slipping Compensation and Back-tracking DPD Achieving 0.034% RMS Frequency Error under 3.4-GHz Chirp Bandwidth and 960-MHz/μs Chirp Slope. VLSI Technology and Circuits Angxiao Yan, Wei Deng, Haikun Jia, Shiyan Sun, Chao Tang, Bufan Zhu, Yu Fu, Hongzhuo Liu, Baoyong Chi
2023	—	`conf`	An 11.5-to-14.3GHz 192.8dBc/Hz FoM at 1MHz Offset Dual-Core Enhanced Class-F VCO with Common-Mode-Noise Self-Cancellation and Isolation Technique. ISSCC Qixiu Wu, Wei Deng, Haikun Jia, Hongzhuo Liu, Shiwei Zhang, Zhihua Wang, Baoyong Chi
2023	—	`conf`	IEEE ASSCC 2023/ Session 10/ Paper 10.5. A-SSCC Ruichang Ma, Haikun Jia, Hongzhuo Liu, Wei Deng, Zhihua Wang, Baoyong Chi
2023	—	`conf`	INVITED PAPER: A 312.5Mbps-32Gbps JESD204C Wireline Transceiver Back-Compatible with JESD204B in 28nm CMOS. ICTA Shijie Li, Ruichang Ma, Mingxing Deng, Jiamin Xue, Wei Deng, Baoyong Chi, Haikun Jia
2023	—	`conf`	Transceiver SoC for Wireless Indoor Sensing Data-fusion. CICC Bufan Zhu, Wei Deng, Ziying Huang, Haikun Jia, Haiyang Jia, Angxiao Yan, Yumeng Yang, Junfeng Liu, Yu Fu, Shiyan Sun, Chao Tang, Taikun Ma, Jiajie Tang, Baoyong Chi
2022	—	`conf`	A 12.5-to-15.4GHz, -118.9dBc/Hz PN at 1MHz offset, and 191.0dBc/Hz FoM VCO with Common-Mode Resonance Expansion and Simultaneous Differential 2ND-Harmonic Output using a Single Three-Coil Transformer in 65nm CMOS. CICC Ruichang Ma, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi
2022	—	`conf`	A 22.8 GHz to 32.8 GHz Compact Power Amplifier with a 15 dBm Output P1dB and 36.5% Peak PAE in 65-nm CMOS. ICTA Huabing Liao, Haikun Jia, Xiangrong Huang, Bao Shi, Wei Deng, Baoyong Chi, Zhihua Wang
2022	J	`jnl`	A 4.4-GHz 193.2-dB FoM 8-Shaped-Inductor Based LC-VCO Using Orthogonal-Coupled Triple-Coil Transformer. IEEE Trans. Circuits Syst. II Express Briefs Yaqian Sun, Wei Deng, Haikun Jia, Zhihua Wang, Baoyong Chi
2022	—	`conf`	A 4.7GHz Synchronized-Multi-Reference PLL with In-Band Phase Noise Lower than Reference Phase Noise +20logN ESSCIRC Hongzhuo Liu, Wei Deng, Haikun Jia, Shiyan Sun, Qixiu Wu, Jiajie Tang, Zhihua Wang, Baoyong Chi
2022	—	`conf`	A 53.6-to-60.2GHz Many-Core Fundamental Oscillator With Scalable Mesh Topology Achieving -136.0dBc/Hz Phase Noise at 10MHz Offset and 190.3dBc/Hz Peak FoM in 65nm CMOS. ISSCC Haikun Jia, Ruichang Ma, Wei Deng, Zhihua Wang, Baoyong Chi
2022	—	`conf`	A 76-81 GHz FMCW 2TX/3RX Radar Transceiver with Integrated Mixed-Mode PLL and Series-Fed Patch Antenna Array. ASP-DAC Taikun Ma, Wei Deng, Haikun Jia, Yejun He, Baoyong Chi
2022	C	`conf`	A Highly Linearized Ka-band Heterodyne Receiver using a Folded Class-AB Inductive Peaking Mixer and Magnetic-Self-Cancellation-Transformer-Based IF Amplifiers. ISCAS Qixiu Wu, Wei Deng, Haikun Jia, Rui Wu, Fuyuan Zhao, Baoyong Chi
2022	J	`jnl`	A Self-Adapted Two-Point Modulation Type-II Digital PLL for Fast Chirp Rate and Wide Chirp-Bandwidth FMCW Signal Generation. IEEE J. Solid State Circuits Wei Deng, Zipeng Chen, Haikun Jia, Angxiao Yan, Shiyan Sun, Guopei Chen, Zhihua Wang, Baoyong Chi
2021	J	`jnl`	A 0.85mm IEEE Trans. Circuits Syst. I Regul. Pap. Zheng Sun, Hanli Liu, Hongye Huang, Dexian Tang, Dingxin Xu, Tohru Kaneko, Zheng Li, Jian Pang, Rui Wu, Wei Deng, Atsushi Shirane, Kenichi Okada
2021	—	`conf`	A 11.1-to-14.2 GHz Self-adapted Two-point Modulation Dual-path Type-II Digital PLL Concurrently Achieving 124.7-MHz/μs Chirp Rate and 2.27-GHz Bandwidth. VLSI Circuits Wei Deng, Zipeng Chen, Haikun Jia, Shiyan Sun, Guopei Chen, Zhihua Wang, Baoyong Chi
2021	—	`conf`	A 122-168GHz Radar/Communication Fusion-Mode Transceiver with 30GHz Chirp Bandwidth, 13dBm Psat, and 8.3dBm OP1dB in 28nm CMOS. VLSI Circuits Zipeng Chen, Wei Deng, Haikun Jia, Pingda Guan, Taikun Ma, Shiyan Sun, Xiangrong Huang, Guopei Chen, Ruichang Ma, Shengnan Dong, Luqiang Duan, Zhihua Wang, Baoyong Chi
2021	—	`conf`	A 24-30GHz 4-Element Phased Array Transceiver with Low Insertion Loss Compact T/R Switch and Bidirectional Phase Shifter in 65 nm CMOS Technology. A-SSCC Xiangrong Huang, Haikun Jia, Shengnan Dong, Wei Deng, Zhihua Wang, Baoyong Chi
2021	—	`conf`	A 33.5-37.5 GHz 4-Element Phased-Array Transceiver Front-End with High-Accuracy Low-Variation 6-bit Resolution 360° Phase Shift and 0~31.5 dB Gain Control in 65 nm CMOS. A-SSCC Pingda Guan, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi
2021	—	`conf`	A 60GHz 186.5dBc/Hz FoM Quad-Core Fundamental VCO Using Circular Triple-Coupled Transformer with No Mode Ambiguity in 65nm CMOS. ISSCC Haikun Jia, Wei Deng, Pingda Guan, Zhihua Wang, Baoyong Chi
2021	—	`conf`	A C-band FMCW Radar Transmitter with a 22 dBm Output Power Series-stacking CMCD PA for Long-distance Detection in 180-nm CMOS Technology. ICTA Xiangrong Huang, Wei Deng, Haikun Jia, Yuhui Wei, Zhihua Wang, Baoyong Chi
2021	J	`jnl`	A Fully Synthesizable Fractional-N MDLL With Zero-Order Interpolation-Based DTC Nonlinearity Calibration and Two-Step Hybrid Phase Offset Calibration. IEEE Trans. Circuits Syst. I Regul. Pap. Bangan Liu, Yuncheng Zhang, Junjun Qiu, Huy Cu Ngo, Wei Deng, Kengo Nakata, Toru Yoshioka, Jun Emmei, Jian Pang, Aravind Tharayil Narayanan, Haosheng Zhang, Teruki Someya, Atsushi Shirane, Kenichi Okada
2021	—	`conf`	A Highly Integrated Energy-efficient CMOS Millimeter-wave Transceiver with Direct-modulation Digital Transmitter, Quadrature Phased-coupled Frequency Synthesizer and Substrate-Integrated Waveguide E-shaped Patch Antenna. ASP-DAC Wei Deng, Zheng Song, Ruichang Ma, Haikun Jia, Baoyong Chi
2021	—	`conf`	An 8.2-to-21.5 GHz Dual-Core Quad-Mode Orthogonal-Coupled VCO with Concurrently Dual-Output using Parallel 8-Shaped Resonator. CICC Wei Deng, Haikun Jia, Rui Wu, Shiyan Sun, Chenggang Li, Zhihua Wang, Baoyong Chi
2021	—	`conf`	An Ultra-Compact 16-to-45 GHz Power Amplifier within A Single Inductor Footprint Using Folded Transformer Technique. CICC Pingda Guan, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi
2021	—	`conf`	Optimization methods for high inductance-density inductors for high speed integrated circuits. ICTA Ziyue Dang, Haikun Jia, Wei Deng, Zhihua Wang, Baoyong Chi
2020	C	`conf`	A 35-GHz TX and RX CMOS Front-Ends for Ka-Band FMCW Phased-Array Radar Transceivers. ISCAS Wei Deng, Rui Wu, Zhijie Chen, Manlai Ding, Baoyong Chi
2020	J	`jnl`	A 35-GHz TX and RX Front End With High TX Output Power for Ka-Band FMCW Phased-Array Radar Transceivers in CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. Wei Deng, Rui Wu, Zhijie Chen, Manlai Ding, Haikun Jia, Baoyong Chi
2020	—	`conf`	A 44-52 GHz Reflection-type Phase Shifter with 1.4° Phase Resolution in 28nm CMOS Process. ICTA Shengnan Dong, Zipeng Chen, Haikun Jia, Wei Deng, Baoyong Chi
2020	—	`conf`	A 53.1-to-64.5 GHz In-Phase Coupled Quadrature Injection-Locked Oscillator with Transformer-Based I/Q-Phase Differential Injection Scheme. ICTA Chenggang Li, Rui Wu, Haikun Jia, Wei Deng, Baoyong Chi
2020	J	`jnl`	A 77-GHz Mixed-Mode FMCW Generator Based on a Vernier TDC With Dual Rising-Edge Fractional-Phase Detector. IEEE Trans. Circuits Syst. I Regul. Pap. Jianxi Wu, Wei Deng, Zipeng Chen, Wei Zheng, Yibo Liu, Shufu Wang, Nan Qi, Baoyong Chi
2020	J	`jnl`	A CMOS 76-81-GHz 2-TX 3-RX FMCW Radar Transceiver Based on Mixed-Mode PLL Chirp Generator. IEEE J. Solid State Circuits Taikun Ma, Wei Deng, Zipeng Chen, Jianxi Wu, Wei Zheng, Shufu Wang, Nan Qi, Yibo Liu, Baoyong Chi
2020	C	`conf`	A FoM of -191 dB, 4.4-GHz LC-VCO Integrating an 8-Shaped Inductor with an Orthogonal-Coupled Tail-Filtering Inductor. ISCAS Yaqian Sun, Wei Deng, Baoyong Chi
2020	J	`jnl`	A U-Band PLL Using Implicit Distributed Resonators for Sub-THz Wireless Transceivers in 40 nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs Zipeng Chen, Wei Deng, Haikun Jia, Yibo Liu, Jianxi Wu, Pingda Guan, Jinyu Zhu, Luhong Mao, Zhihua Wang, Baoyong Chi
2020	J	`jnl`	An Energy-Efficient 10-Gb/s CMOS Millimeter-Wave Transceiver With Direct-Modulation Digital Transmitter and I/Q Phase-Coupled Frequency Synthesizer. IEEE J. Solid State Circuits Wei Deng, Zheng Song, Ruichang Ma, Jianfu Lin, Yutian Li, Jialiang Ye, Shangcheng Kong, Sanming Hu, Haikun Jia, Baoyong Chi
2019	J	`jnl`	A 265- $\mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS. IEEE J. Solid State Circuits Hanli Liu, Atsushi Shirane, Kenichi Okada, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya
2019	—	`conf`	A 265μW Fractional-N Digital PLL with Seamless Automatic Switching Subsampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65nm CMOS. ISSCC Hanli Liu, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada
2019	—	`conf`	An HDL-described Fully-synthesizable Sub-GHz IoT Transceiver with Ring Oscillator based Frequency Synthesizer and Digital Background EVM Calibration. CICC Bangan Liu, Yuncheng Zhang, Junjun Qiu, Wei Deng, Zule Xu, Haosheng Zhang, Jian Pang, Yun Wang, Rui Wu, Teruki Someya, Atsushi Shirane, Kenichi Okada
2018	—	`conf`	A 0.85mm ESSCIRC Zheng Sun, Hanli Liu, Dexian Tang, Hongye Huang, Tohru Kaneko, Rui Wu, Wei Deng, Kenichi Okada
2018	—	`conf`	A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOS. ISSCC Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada, Akira Matsuzawa
2018	—	`conf`	A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. CICC Bangan Liu, Huy Cu Ngo, Kengo Nakata, Wei Deng, Yuncheng Zhang, Junjun Qiu, Toru Yoshioka, Jun Emmei, Haosheng Zhang, Jian Pang, Aravind Tharayil Narayanan, Dongsheng Yang, Hanli Liu, Kenichi Okada, Akira Matsuzawa
2018	J	`jnl`	A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS. IEICE Trans. Electron. Hanli Liu, Teerachot Siriburanon, Kengo Nakata, Wei Deng, Ju Ho Son, Dae Young Lee, Kenichi Okada, Akira Matsuzawa
2018	J	`jnl`	A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS. IEEE J. Solid State Circuits Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Zhijie Chen, Wei Deng, Rui Wu, Kenichi Okada
2018	J	`jnl`	A Sub-mW Fractional-N ADPLL With FOM of -246 dB for IoT Applications. IEEE J. Solid State Circuits Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada
2018	—	`conf`	An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS. ISSCC Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Wei Deng, Rui Wu, Kenichi Okada, Akira Matsuzawa
2017	J	`jnl`	A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI. IEICE Trans. Electron. Aravind Tharayil Narayanan, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa
2017	—	`conf`	An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. ASP-DAC Dongsheng Yang, Wei Deng, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa
2016	J	`jnl`	A 0.0055mm IEICE Trans. Electron. Dongsheng Yang, Tomohiro Ueno, Wei Deng, Yuki Terashima, Kengo Nakata, Aravind Tharayil Narayanan, Rui Wu, Kenichi Okada, Akira Matsuzawa
2016	J	`jnl`	A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture. IEEE J. Solid State Circuits Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016	J	`jnl`	A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB. IEEE J. Solid State Circuits Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng, Kenichi Okada, Akira Matsuzawa
2016	J	`jnl`	A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad. IEEE J. Solid State Circuits Teerachot Siriburanon, Satoshi Kondo, Makihiko Katsuragi, Hanli Liu, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa
2016	—	`conf`	An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB. ESSCIRC Dongsheng Yang, Wei Deng, Bangan Liu, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa
2016	—	`conf`	An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection. ASP-DAC Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	14.1 A 0.048mm ISSCC Wei Deng, Dongsheng Yang, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture. ISSCC Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular. ESSCIRC Teerachot Siriburanon, Hanli Liu, Kengo Nakata, Wei Deng, Ju Ho Son, Dae Young Lee, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection. ASP-DAC Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa
2015	J	`jnl`	A 60-GHz CMOS Transmitter with Gain-Enhanced On-Chip Antenna for Short-Range Wireless Interconnections. IEICE Trans. Electron. Rui Wu, Wei Deng, Shinji Sato, Takuichi Hirano, Ning Li, Takeshi Inoue, Hitoshi Sakane, Kenichi Okada, Akira Matsuzawa
2015	J	`jnl`	A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit. IEICE Trans. Electron. Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa
2015	J	`jnl`	A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique. IEEE J. Solid State Circuits Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB. ESSCIRC Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng, Kenichi Okada, Akira Matsuzawa
2015	J	`jnl`	A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI. IEICE Electron. Express Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Rui Wu, Bangan Liu, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	A tail-current modulated VCO with adaptive-bias scheme. ASP-DAC Aravind Tharayil Narayanan, Wei Deng, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	An HDL-synthesized gated-edge-injection PLL with a current output DAC. ASP-DAC Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	15.1 A 0.0066mm ISSCC Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	A 0.011 mm A-SSCC Aravind Tharayil Narayanan, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	A 0.015-mm A-SSCC Rui Wu, Qinghong Bu, Wei Deng, Kenichi Okada, Akira Matsuzawa
2014	J	`jnl`	A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios. IEEE J. Solid State Circuits Wei Deng, Shoichi Hara, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2014	J	`jnl`	A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration. IEEE J. Solid State Circuits Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. ASP-DAC Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	A pulse-driven LC-VCO with a figure-of-merit of -192dBc/Hz. ESSCIRC Aravind Tharayil Narayanan, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits. ASP-DAC Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa
2013	—	`conf`	A 0.022mm ISSCC Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2013	—	`conf`	A 13.2% locking-range divide-by-6, 3.1mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs. ESSCIRC Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2013	J	`jnl`	A 20 GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60 GHz Frequency Synthesizer. IEICE Trans. Electron. Teerachot Siriburanon, Takahiro Sato, Ahmed Musa, Wei Deng, Kenichi Okada, Akira Matsuzawa
2013	J	`jnl`	A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers. IEEE J. Solid State Circuits Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2013	—	`conf`	A fractional-N harmonic injection-locked frequency synthesizer with 10MHz-6.6GHz quadrature outputs for software-defined radios. ASP-DAC Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2013	—	`conf`	A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers. ASP-DAC Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2013	J	`jnl`	Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing. IEEE J. Solid State Circuits Wei Deng, Kenichi Okada, Akira Matsuzawa
2012	J	`jnl`	A 0.5-V, 0.05-to-3.2 GHz LC-Based Clock Generator for Substituting Ring Oscillators under Low-Voltage Condition. IEICE Trans. Electron. Wei Deng, Kenichi Okada, Akira Matsuzawa
2012	—	`conf`	A 58.1-to-65.0GHz frequency synthesizer with background calibration for millimeter-wave TDD transceivers. ESSCIRC Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2012	—	`conf`	A PVT-robust feedback class-C VCO using an oscillation swing enhancement technique. ASP-DAC Wei Deng, Kenichi Okada, Akira Matsuzawa
2011	—	`conf`	A feedback class-C VCO with robust startup condition over PVT variations and enhanced oscillation swing. ESSCIRC Wei Deng, Kenichi Okada, Akira Matsuzawa
2011	—	`conf`	An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generation. ASP-DAC Wei Deng, Kenichi Okada, Akira Matsuzawa