Wei Cao

36 papers B 5C 2Journal 11Unranked 18
YearRankTypeTitle / Venue / Authors
2026 J jnl
An Agile Deployment System for Password Recovery on FPGA.
IEEE Trans. Computers
Liming Deng, Guowei Zhu, Xitian Fan, Guangwei Xie, Mingqian Sun, Xuegong Zhou, Wei Cao, Fan Zhang, Xinsheng Yu
2025 J jnl
AHCA: Agile Design Framework for Hashcat Acceleration Based on FPGA.
ACM Trans. Reconfigurable Technol. Syst.
Liming Deng, Guowei Zhu, Xitian Fan, Wei Cao, Xuegong Zhou, Fan Zhang, Shaobo Yang
2025 C conf
Agile Design Flow for Cryptographic Hardware Accelerators.
ICCD
Liming Deng, Guowei Zhu, Wei Cao, Xitian Fan, Xuegong Zhou
2025 J jnl
DVHetero: A Framework for Designing and Validating Heterogeneous SoC with RISC-V Processor and CGRA.
ACM Trans. Reconfigurable Technol. Syst.
Guowei Zhu, Liming Deng, Kaisen Zhang, Wang Fan, Boyin Jin, Wei Cao, Fengzhe Zhang, Xuegong Zhou, Fan Zhang, Xinsheng Yu
2024 J jnl
Qubit-Wise Architecture Search Method for Variational Quantum Circuits.
CoRR
Jialin Chen, Zhiqiang Cai, Ke Xu, Di Wu, Wei Cao
2023 C conf
Unified Accelerator for Attention and Convolution in Inference Based on FPGA.
ISCAS
Tianyang Li, Fan Zhang, Xitian Fan, JianLiang Shen, Wei Guo, Wei Cao
2022 J jnl
Acceleration of Rotated Object Detection on FPGA.
IEEE Trans. Circuits Syst. II Express Briefs
Xitian Fan, Guangwei Xie, Zhongcheng Huang, Wei Cao, Lingli Wang
2021 — conf
A High-Precision Flexible Symmetry-Aware Architecture for Element-Wise Activation Functions.
FPT
Xuan Feng, Yue Li, Yu Qian, Jingbo Gao, Wei Cao, Lingli Wang
2021 — conf
LETA: A lightweight exchangeable-track accelerator for efficientnet based on FPGA.
FPT
Jingbo Gao, Yu Qian, Yihan Hu, Xitian Fan, Wai-Shing Luk, Wei Cao, Lingli Wang
2021 J jnl
MRI-based brain tumor segmentation using FPGA-accelerated neural network.
BMC Bioinform.
Siyu Xiong, Guoqing Wu, Xitian Fan, Xuan Feng, Zhongcheng Huang, Wei Cao, Xuegong Zhou, Shijin Ding, Jinhua Yu, Lingli Wang, Zhifeng Shi
2021 J jnl
SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator.
IEEE Trans. Very Large Scale Integr. Syst.
Di Wu, Xitian Fan, Wei Cao, Lingli Wang
2020 — conf
A Low-Cost Reconfigurable Nonlinear Core for Embedded DNN Applications.
FPT
Yue Li, Wei Cao, Xuegong Zhou, Lingli Wang
2019 — conf
A High Performance FPGA-Based Accelerator Design for End-to-End Speaker Recognition System.
FPT
Mingjun Jiao, Yue Li, Pengbo Dang, Wei Cao, Lingli Wang
2019 J jnl
RNA: An Accurate Residual Network Accelerator for Quantized and Reconstructed Deep Neural Networks.
IEICE Trans. Inf. Syst.
Cheng Luo, Wei Cao, Lingli Wang, Philip H. W. Leong
2019 — conf
SpWMM: A High-Performance Sparse-Winograd Matrix-Matrix Multiplication Accelerator for CNNs.
FPT
Di Wu, Wei Cao, Lingli Wang
2018 B conf
A Novel Low-Communication Energy-Efficient Reconfigurable CNN Acceleration Architecture.
FPL
Di Wu, Jin Chen, Wei Cao, Lingli Wang
2018 — conf
High Throughput CNN Accelerator Design Based on FPGA.
FPT
Liang Xie, Xitian Fan, Wei Cao, Lingli Wang
2018 B conf
RNA: An Accurate Residual Network Accelerator for Quantized and Reconstructed Deep Neural Networks.
FPL
Cheng Luo, Yuhua Wang, Wei Cao, Philip H. W. Leong, Lingli Wang
2018 J jnl
Stream Processing Dual-Track CGRA for Object Inference.
IEEE Trans. Very Large Scale Integr. Syst.
Xitian Fan, Di Wu, Wei Cao, Wayne Luk, Lingli Wang
2017 B conf
Accelerating low bit-width convolutional neural networks with embedded FPGA.
FPL
Li Jiao, Cheng Luo, Wei Cao, Xuegong Zhou, Lingli Wang
2016 B conf
A high performance FPGA-based accelerator for large-scale convolutional neural networks.
FPL
Huimin Li, Xitian Fan, Li Jiao, Wei Cao, Xuegong Zhou, Lingli Wang
2016 B conf
DT-CGRA: Dual-track coarse-grained reconfigurable architecture for stream applications.
FPL
Xitian Fan, Huimin Li, Wei Cao, Lingli Wang
2016 — conf
High performance Deformable Part Model accelerator based on FPGA.
FPT
Qi Zhan, Min Gao, Li Jiao, Wei Cao, Xuegong Zhou, Lingli Wang
2015 — conf
Implementation of high performance hardware architecture of face recognition algorithm based on local binary pattern on FPGA.
ASICON
Yangjie Zhang, Wei Cao, Lingli Wang
2013 — conf
A hardware implementation of Bag of Words and Simhash for image recognition.
FPT
Shengye Wang, Chen Liang, Xuegong Zhou, Wei Cao, Chenlu Wu, Xitian Fan, Lingli Wang
2013 — conf
A novel structure of dynamic configurable scan chain bypassing unconcerned segments on the fly.
ASICON
Shengye Wang, Wei Cao, Lingli Wang, Na Wang, Ping Tao
2013 — conf
A reconfigurable floating-point FFT architecture.
ASICON
Chenlu Wu, Wei Cao, Xuegong Zhou, Lingli Wang, Fang Wang, Baodi Yuan
2013 — conf
An FPGA-cluster-accelerated match engine for content-based image retrieval.
FPT
Chen Liang, Chenlu Wu, Xuegong Zhou, Wei Cao, Shengye Wang, Lingli Wang
2013 — conf
Implementation of high performance hardware architecture of OpenSURF algorithm on FPGA.
FPT
Xitian Fan, Chenlu Wu, Wei Cao, Xuegong Zhou, Shengye Wang, Lingli Wang
2011 J jnl
A Reconfigurable Multi-Transform VLSI Architecture Supporting Video Codec Design.
IEEE Trans. Circuits Syst. II Express Briefs
Kanwen Wang, Jialin Chen, Wei Cao, Ying Wang, Lingli Wang, Jiarong Tong
2011 — conf
A coarse-grained reconfigurable computing unit.
ASICON
Kanwen Wang, Shuai Chen, Wei Cao, Lingli Wang, Jiarong Tong
2011 — conf
A permutation network for configurable and scalable FFT processors.
ASICON
Shuai Chen, Jialin Chen, Kanwen Wang, Wei Cao, Lingli Wang
2008 — conf
A high-performance reconfigurable 2-D transform architecture for H.264.
ICECS
Wei Cao, Hui Hou, Jinmei Lai, Jiarong Tong, Hao Min
2008 J jnl
A high-performance reconfigurable VLSI architecture for vbsme in H.264.
IEEE Trans. Consumer Electron.
Wei Cao, Hui Hou, Jiarong Tong, Jinmei Lai, Hao Min
2008 — conf
A novel dynamic reconfigurable VLSI architecture for H.264 transforms.
APCCAS
Wei Cao, Hui Hou, Jinmei Lai, Jiarong Tong, Hao Min
2008 — conf
High-speed and memory-efficient architecture for 2-D 1-Level discrete wavelet transform.
ICECS
Hui Hou, Wei Cao, Fan-jiong Zhang, Jinmei Lai, Jiarong Tong