Wei-Zen Chen - RankMe

68 papers A 2C 7Journal 30Unranked 29

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A Simultaneous Bidirectional Link With 6-12.8-Gb/s Forward and 12-25.6-Gb/s Backward Channels for System Chips Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. Hao-Kai Mo, Yu-ping Huang, You-Cheng Tu, Wei-Zen Chen
2025	A	`conf`	Clock and Power Supply-Aware High Accuracy Phase Interpolator Layout Synthesis. DATE Siou-Sian Lin, Shih-Yu Chen, Yu-ping Huang, Tzu-Chuan Lin, Hung-Ming Chen, Wei-Zen Chen
2025	C	`conf`	Dynamic ADC and Equalizer Adaptation with Background SNR Monitoring for a DSP-Based PAM-4 Receiver. ISCAS You-Cheng Tu, Rui-Yong Kuo, Wei-Zen Chen
2025	J	`jnl`	Guest Editorial Introduction to the Special Section on the 2024 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits Wei-Zen Chen, Benton H. Calhoun, Chia-Hsiang Yang, Shreyas Sen, Jun Yang
2024	J	`jnl`	A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction. IEEE Open J. Circuits Syst. Yu-ping Huang, Yu-Sian Lu, Wei-Zen Chen
2023	J	`jnl`	A 103 fJ/b/dB, 10-26 Gb/s Receiver With a Dual Feedback Nested Loop CDR for Wide Bandwidth Jitter Tolerance Enhancement. IEEE J. Solid State Circuits Yao-Chia Liu, Wei-Zen Chen, Yuan-Sheng Lee, Yu-Hsiang Chen, Shawn Ming, Ying-Hsi Lin
2023	J	`jnl`	A Reference-Free Phase Noise Measurement Circuit Achieving 24.2-fs Periodic Jitter Sensitivity and 275-fsrms Resolution With Background Self-Calibration. IEEE J. Solid State Circuits Wei-Jhih Jian, Wei-Zen Chen
2022	—	`conf`	A Reference-Free Phase Noise Measurement Circuit Achieving 24.2 fs Periodic Jitter Sensitivity and 275 fsrms Resolution with Background Self-Calibration. VLSI Technology and Circuits Wei-Jhih Jian, Wei-Zen Chen
2021	—	`conf`	A 1.68-23.2 Gb/s Reference-Less Half-Rate Receiver with an ISI-Tolerant Unlimited Range Frequency Detector. A-SSCC Yu-ping Huang, Yi-Wei Chang, Wei-Zen Chen
2021	—	`conf`	A 10 GHz Dual-Loop PLL with Active Noise Cancellation Achieving 12dB Spur and 29% Noise Reduction. A-SSCC Yu-Sian Lu, Cheng-Lung Lee, Wei-Zen Chen
2021	J	`jnl`	A 32 Gb/s PAM-4 Optical Transceiver With Active Back Termination in 40 nm CMOS Technology. IEEE Open J. Circuits Syst. Wei-Hsiang Ho, Yi-Hsun Hsieh, Boris Murmann, Wei-Zen Chen
2021	J	`jnl`	A 50 Gb/s PAM-4 Transmitter With Feedforward Equalizer and Background Phase Error Calibration. IEEE Trans. Circuits Syst. II Express Briefs Yu-Ting Lin, Ting-Wei Xu, Wei-Zen Chen
2021	—	`conf`	A Single-Channel 1.75GS/s, 6-Bit Flash-Assisted SAR ADC with Self-Adaptive Timer and On-Chip Offset Calibration. A-SSCC Yu-Sian Liao, Wei-Zen Chen
2021	—	`conf`	F6: Optical and Electrical Transceivers for 400GbE and Beyond. ISSCC Tony Chan Carusone, Sudip Shekhar, Yohan Frans, Wei-Zen Chen, Thomas Toifl, Munehiko Nagatani, Franz Dielacher, William Redman-White
2021	J	`jnl`	Introduction to the Special Section on the 2020 Asian Solid-State Circuits Conference (A-SSCC). IEEE J. Solid State Circuits Robert Chen-Hao Chang, Wei-Zen Chen, Jun Deguchi
2021	—	`conf`	Session 11 Overview: Advanced Wireline Links and Techniques Wireline Subcommittee. ISSCC Mike Shuo-Wei Chen, Wei-Zen Chen, Amir Amirkhany
2020	C	`conf`	A 32 Gb/s PAM-4 Optical Transceiver with Active Back Termination in 40 nm CMOS Technology. ISCAS Wei-Hsiang Ho, Yi-Hsun Hsieh, Boris Murmann, Wei-Zen Chen
2020	—	`conf`	A 50 Gb/s PAM-4 Transmitter with Feedforward Equalizer and Background Phase Error Calibration. A-SSCC Yu-Ting Lin, Wei-Zen Chen
2020	—	`conf`	A Millimeter-Wave Frequency Synthesizer for 60 GHz Wireless Interconnect. VLSI-DAT Yong-Yu Lin, Fan-ta Chen, Wei-Zen Chen
2020	J	`jnl`	Exploring Multiple Analog Placements With Partial-Monotonic Current Paths and Symmetry Constraints Using PCP-SP. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Abhishek Patyal, Po-Cheng Pan, K. A. Asha, Hung-Ming Chen, Wei-Zen Chen
2019	J	`jnl`	A 25-Gb/s, 2.1-pJ/bit, Fully Integrated Optical Receiver With a Baud-Rate Clock and Data Recovery. IEEE J. Solid State Circuits Yuan-Sheng Lee, Wei-Hsiang Ho, Wei-Zen Chen
2018	C	`conf`	A 20-Gb/s, 2.4 pJ/bit, Fully Integrated Optical Receiver with a Baud-Rate Clock and Data Recovery. ISCAS Yuan-Sheng Lee, Wei-Zen Chen
2018	—	`conf`	A 40 Gb/s PAM-4 Receiver with 2-Tap DFE Based on Automatically Non-Even Level Tracking. A-SSCC Chia-Tse Hung, Yu-ping Huang, Wei-Zen Chen
2017	J	`jnl`	A 25 Gb/s 1.13 pJ/b -10.8 dBm Input Sensitivity Optical Receiver in 40 nm CMOS. IEEE J. Solid State Circuits Shih-Hao Huang, Wei-Zen Chen
2016	—	`conf`	A ΔΣ TDC with sub-ps resolution for PLL built-in phase noise measurement. ESSCIRC Wei-Zen Chen, Po-I Kuo
2016	J	`jnl`	Distortion-characteristic estimation predistorter for high efficiency power amplifiers. IET Signal Process. Zhiyuan Ren, Hsiao-Hwa Chen, Wei-Zen Chen
2015	—	`conf`	A 0.4V 53dB SNDR 250 MS/s time-based CT ΔΣ analog to digital converter. ASICON Hung-Kai Chen, Wei-Zen Chen, Zhiyuan Ren
2015	J	`jnl`	A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression. IEEE Trans. Circuits Syst. I Regul. Pap. Ming-Chiuan Su, Wei-Zen Chen, Pei-Si Wu, Yu-Hsian Chen, Chao-Cheng Lee, Shyh-Jye Jou
2015	—	`conf`	A 25-Gb/s, -10.8-dBm input sensitivity, PD-bandwidth tolerant CMOS optical receiver. VLSIC Shih-Hao Huang, Wei-Zen Chen
2015	J	`jnl`	A 3.12 pJ/bit, 19-27 Gbps Receiver With 2-Tap DFE Embedded Clock and Data Recovery. IEEE J. Solid State Circuits Zheng-Hao Hong, Yao-Chia Liu, Wei-Zen Chen
2015	J	`jnl`	A Low-Jitter Cell-Based Digitally Controlled Oscillator With Differential Multiphase Outputs. IEEE Trans. Very Large Scale Integr. Syst. Ming-Chiuan Su, Shyh-Jye Jou, Wei-Zen Chen
2014	C	`conf`	A 0.6 V, 1.66mW energy harvester and audio driver for tympanic membrane transducer with wirelessly optical signal and power transfer. ISCAS Jhong-Ting Jian, Yu-Lin Song, Chia-Fone Lee, Yuan-Fang Chou, Wei-Zen Chen
2014	J	`jnl`	A 160-GHz Frequency-Translation Phase-Locked Loop With RSSI Assisted Frequency Acquisition. IEEE Trans. Circuits Syst. I Regul. Pap. Wei-Zen Chen, Tai-You Lu, Yan-Ting Wang, Jhong-Ting Jian, Yi-Hung Yang, Kai-Ting Chang
2014	—	`conf`	A 2 × 20-Gb/s, 1.2-pJ/bit, time-interleaved optical receiver in 40-nm CMOS. A-SSCC Shih-Hao Huang, Zheng-Hao Hong, Wei-Zen Chen
2014	—	`conf`	A 3.12 pJ/bit, 19-27 Gbps receiver with 2 Tap-DFE embedded clock and data recovery. A-SSCC Zheng-Hao Hong, Wei-Zen Chen
2014	—	`conf`	An 8 Gbps, 4: 1 transition-aware self-toggling multiplexer. APCCAS Wei-Zen Chen, Yi-Hung Yang
2014	—	`conf`	An automatic synthesis tool for nanometer low dropout regulator using simulation based model and geometric programming. VLSI-DAT Shih-Hsin Hsu, Wei-Zen Chen, Jui-Pin Zheng, Sean S.-Y. Liu, Po-Cheng Pan, Hung-Ming Chen
2013	—	`conf`	A 0.1-3GHz cell-based fractional-N all digital phase-locked loop using ΔΣ noise-shaped phase detector. CICC Yao-Chia Liu, Wei-Zen Chen, Mao-Hsuan Chou, Tsung-Hsien Tsai, Yen-Wei Lee, Min-Shueh Yuan
2013	—	`conf`	A 10Bit, 10MS/s, low power cyclic ADC. ICICDT Chien-Hung Chen, Wei-Zen Chen
2013	—	`conf`	A 10Gbps, 1.24pJ/bit, burst-mode clock and data recovery with jitter suppression. CICC Ming-Chiuan Su, Wei-Zen Chen, Pei-Si Wu, Yu-Hsian Chen, Chao-Cheng Lee, Shyh-Jye Jou
2013	J	`jnl`	Wide Tunning Range 60 GHz VCO and 40 GHz DCO Using Single Variable Inductor. IEEE Trans. Circuits Syst. I Regul. Pap. Tai-You Lu, Chi-Yao Yu, Wei-Zen Chen, Chung-Yu Wu
2012	—	`conf`	A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology. VLSIC Wei-Zen Chen, Tai-You Lu, Yan-Ting Wang, Jhong-Ting Jian, Yi-Hung Yang, Guo-Wei Huang, Wen-De Liu, Chih-Hua Hsiao, Shu-Yu Lin, Jung Yen Liao
2012	J	`jnl`	A 2.4 GHz Reference-Less Receiver for 1 Mbps QPSK Demodulation. IEEE Trans. Circuits Syst. I Regul. Pap. Wei-Zen Chen, Tai-You Lu, Wei-Wen Ou, Shun-Tien Chou, Song-Yu Yang
2012	J	`jnl`	A 3-10 GHz, 14 Bands CMOS Frequency Synthesizer With Spurs Reduction for MB-OFDM UWB System. IEEE Trans. Very Large Scale Integr. Syst. Tai-You Lu, Wei-Zen Chen
2012	C	`conf`	A 40 Gbps optical receiver analog front-end in 65 nm CMOS. ISCAS Shun-Tien Chou, Shih-Hao Huang, Zheng-Hao Hong, Wei-Zen Chen
2011	J	`jnl`	A 10-Gb/s OEIC with Meshed Spatially-Modulated Photo Detector in 0.18-μm CMOS Technology. IEEE J. Solid State Circuits Shih-Hao Huang, Wei-Zen Chen, Yu-Wei Chang, Yang-Tung Huang
2011	A	`conf`	Fast analog layout prototyping for nanometer design migration. ICCAD Yi-Peng Weng, Hung-Ming Chen, Tung-Chieh Chen, Po-Cheng Pan, Chien-Hung Chen, Wei-Zen Chen
2010	C	`conf`	A 2.4 GHz reference-less wireless receiver for 1Mbps QPSK demodulation. ISCAS Wei-Zen Chen, Wei-Wen Ou, Tai-You Lu, Shun-Tien Chou, Song-Yu Yang
2010	J	`jnl`	A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology. IEEE J. Solid State Circuits Song-Yu Yang, Wei-Zen Chen, Tai-You Lu
2009	—	`conf`	A 10-Gbps CMOS single chip optical receiver with 2-D meshed spatially-modulated light detector. CICC Shih-Hao Huang, Wei-Zen Chen
2009	—	`conf`	A 7.1mW 10GHz all-digital frequency synthesizer with dynamically reconfigurable digital loop filter in 90nm CMOS. ISSCC Song-Yu Yang, Wei-Zen Chen
2009	J	`jnl`	A Single-Chip 2.5-Gb/s CMOS Burst-Mode Optical Receiver. IEEE Trans. Circuits Syst. I Regul. Pap. Wei-Zen Chen, Ruei-Ming Gan, Shih-Hao Huang
2008	—	`conf`	A 3-to-10GHz 14-Band CMOS Frequency Synthesizer with Spurs Reduction for MB-OFDM UWB System. ISSCC Tai-You Lu, Wei-Zen Chen
2008	J	`jnl`	Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications. IEEE Trans. Circuits Syst. I Regul. Pap. Wei-Zen Chen, Guan-Sheng Huang
2007	—	`conf`	A 2.5 Gbps CMOS Fully Integrated Optical Receicer with Lateral PIN Detector. CICC Wei-Zen Chen, Shih-Hao Huang
2007	J	`jnl`	A 90-dB Omega 10-Gb/s Optical Receiver Analog Front-End in a 0.18µm CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. Wei-Zen Chen, Da-Shin Lin
2007	J	`jnl`	Three-Dimensional Fully Symmetric Inductors, Transformer, and Balun in CMOS Technology. IEEE Trans. Circuits Syst. I Regul. Pap. Wei-Zen Chen, Wen-Hui Chen, Kuo-Ching Hsu
2006	C	`conf`	A low power programmable PRBS generator and a clock multiplier unit for 10 Gbps serdes applications. ISCAS Wei-Zen Chen, Guan-Sheng Huang
2006	J	`jnl`	Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-μm digital CMOS technology. IEEE Trans. Circuits Syst. I Regul. Pap. Wei-Zen Chen, Chao-Hsin Lu
2005	J	`jnl`	A 1.8-V 10-Gb/s fully integrated CMOS optical receiver analog front-end. IEEE J. Solid State Circuits Wei-Zen Chen, Ying-Lien Cheng, Da-Shin Lin
2005	—	`conf`	Miniaturized 3-dimensional transformer design. CICC Wei-Zen Chen, Kuo-Ching Hsu
2004	—	`conf`	A 1.8 V, 10 Gbps fully integrated CMOS optical receiver analog front end. ESSCIRC Wei-Zen Chen, Ying-Lien Cheng
2004	J	`jnl`	A 2-V 2.3/4.6-GHz dual-band frequency synthesizer in 0.35-μm digital CMOS process. IEEE J. Solid State Circuits Wei-Zen Chen, Jia-Xian Chang, Ying-Jen Hong, Meng-Tzer Wong, Chien-Liang Kuo
2003	—	`conf`	10 GHz quadrature-phase voltage controlled oscillator and prescaler. ESSCIRC Wei-Zen Chen, Chien-Liang Kuo, Chia-Chun Liu
2002	—	`conf`	A 2.5 Gbps CMOS optical receiver analog front-end. CICC Wei-Zen Chen, Chao-Hsin Lu
1999	J	`jnl`	A 2-V, 1.8-GHz BJT phase-locked loop. IEEE J. Solid State Circuits Wei-Zen Chen, Jieh-Tsorng Wu
1998	—	`conf`	A 2 V 1.6 GHz BJT phase-locked loop. CICC Wei-Zen Chen, Jieh-Tsorng Wu
1998	J	`jnl`	A 2-V 2-GHz BJT variable frequency oscillator. IEEE J. Solid State Circuits Wei-Zen Chen, Jieh-Tsorng Wu