Wei-Kai Cheng

25 papers A* 1A 1C 1Misc 1Journal 5Unranked 16
YearRankTypeTitle / Venue / Authors
2024 — conf
Automated Quantization Strategy on CIM.
ICCE-Taiwan
Yu-Shan Huang, Wei-Kai Cheng
2024 — conf
Global Routing Optimization Analysis based on Deep Reinforcement Learning.
APCCAS
Ying-Tzu Chen, Wei-Kai Cheng
2024 — conf
Impact of ADC Bits on CNNs in CIM Architecture.
ICCE-Taiwan
Chia-Hsuan Chang, Wei-Kai Cheng
2023 — conf
Convolutional Neural Network Accelerator for Integrated Winograd and Convolution Computations.
ICCE-Taiwan
Yueh-Fan Lo, Wei-Kai Cheng
2023 — conf
Framework and Quantization Method Design for CIM.
ICCE-Taiwan
Hsin-Yi Pai, Wei-Kai Cheng
2022 — conf
Layer-wise Exploration of Synaptic Array and Weight Mapping on Heterogeneous Tile-based RRAM CIM Architecture.
ISOCC
Hsin-Tzu Wu, Hsin-Yi Pai, Wei-Kai Cheng
2020 — conf
Architecture Design of Overlap-Add FFT on the Convolution Neural Networks.
ICCE-TW
Wei-Kai Cheng, Yuan-Chih Lo, Hsia-Tsung Wang
2020 Misc conf
Co-Optimization of Grid-Based TAM Wire Routing and Test Scheduling with Reconfigurable Wrappers.
VTS
Jui-Hung Hung, Shih-Hsu Huang, Chun-Hua Cheng, Hsu-Yu Kao, Wei-Kai Cheng
2020 — conf
Dataflow Design of Overlap-Add FFT on the Convolution Neural Networks.
ICCE-TW
Wei-Kai Cheng, Xiang-Yi Liu, Tsai-Yu Tsai
2019 — conf
Machine Learning Techniques for Building and Evaluation of Routability-driven Macro Placement.
ICCE-TW
Wei-Kai Cheng, Chih-Shuan Wu
2018 — conf
An Effective Approach for Building Low-Power General Activity-Driven Clock Trees.
ISOCC
Chen-Hsien Lin, Shih-Hsu Huang, Wei-Kai Cheng
2018 — conf
Integration of Retention-aware Refresh and BISR Techniques for DRAM Refresh Power Reduction.
ISOCC
Wei-Kai Cheng, Jian-Kai Chen, Shih-Hsu Huang
2016 J jnl
Architecture and data migration methodology for L1 cache design with hybrid SRAM and volatile STT-RAM configuration.
Microprocess. Microsystems
Wei-Kai Cheng, Yen-Heng Ciou, Po-Yuan Shen
2016 J jnl
Non-Uniform Clock Mesh Synthesis with Clock Gating and Register Clustering.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Wei-Kai Cheng, Jui-Hung Hung, Yi-Hsuan Chiu
2016 C conf
Top-level activity-driven clock tree synthesis with clock skew variation considered.
ISCAS
Te-Jui Wang, Shih-Hsu Huang, Wei-Kai Cheng, Yih-Chih Chou
2016 J jnl
Unified approach for simultaneous functional and timing ECO.
IET Circuits Devices Syst.
Jui-Hung Hung, Yu-Cheng Lin, Wei-Kai Cheng, Tsai-Ming Hsieh
2015 J jnl
A Skew-Window based Methodology for Timing Fixing in Multiple Power Modes.
J. Inf. Sci. Eng.
Wei-Kai Cheng, Po-Han Wu, Yi-Hsuan Chiu
2015 — conf
A logic difference generator with spare cells consideration for ECO synthesis.
ISQED
Jui-Hung Hung, Yu-Cheng Lin, Wei-Kai Cheng, Tsai-Ming Hsieh
2014 A conf
A Data Migration Approach for L1 Cache Design with SRAM and Volatile STT-RAM.
ICS
Wei-Kai Cheng, Yen-Heng Ciou
2012 — conf
A 3D IC designs partitioning algorithm with power consideration.
ISQED
Ho-lin Chang, Hsiang-Cheng Lai, Tsu-Yun Hsueh, Wei-Kai Cheng, Mely Chen Chi
2012 — conf
Memory binding and layer assignment for high-level synthesis of 3D ICs.
APCCAS
Yi-Chun Yen, Jhih-Kai Yang, Wei-Kai Cheng
1999 J jnl
Code generation of nested loops for DSP processors with heterogeneous registers and structural pipelining.
ACM Trans. Design Autom. Electr. Syst.
Wei-Kai Cheng, Youn-Long Lin
1998 — conf
Addressing Optimization for Loop Execution Targeting DSP with Auto-Increment/Decrement Architecture.
ISSS
Wei-Kai Cheng, Youn-Long Lin
1995 A* conf
A Transformation-Based Approach for Storage Optimization.
DAC
Wei-Kai Cheng, Youn-Long Lin
1994 — conf
Code generation for a DSP processor.
HLSS
Wei-Kai Cheng, Youn-Long Lin