Wei-Han Yu

46 papers Journal 30Unranked 16
YearRankTypeTitle / Venue / Authors
2026 J jnl
A 3.51 TOPS/mm
IEEE Trans. Circuits Syst. I Regul. Pap.
Zhongyu Zhao, Rujian Cao, Ka-Fai Un, Wei-Han Yu, Rui Paulo Martins, Pui-In Mak
2026 J jnl
A Multi-Frequency-Excited MIMO Radar Array Architecture Enabling Exponential-Order Improvement in Angular Resolution.
IEEE J. Solid State Circuits
Ruilin Liao, Haoran Wang, Jingzhi Zhang, Wei-Han Yu, Yue Song, Hongyang An, Huihua Liu, Kai Kang
2025 J jnl
A 1.8% FAR, 2 ms Decision Latency, 1.73 nJ/Decision Keywords-Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-IF-Domain Computing and Scalable 5T-SRAM.
IEEE J. Solid State Circuits
Fei Tan, Wei-Han Yu, Jinhai Lin, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak
2025 J jnl
A 28-nm MFCC-Free Keyword Switchable Keyword Spotting (KWS) System With Transferred Training Algorithm.
IEEE Trans. Circuits Syst. II Express Briefs
Fei Tan, Yujia Wang, Wei-Han Yu, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak
2025 J jnl
A 90.7-nW Vibration-Based Condition Monitoring Chip Featuring a Digital Compute-in-Memory- Based DNN Accelerator Using an Ultra-Low-Power 13T-SRAM Cell.
IEEE J. Solid State Circuits
Haochen Zhang, Wei-Han Yu, Zhizhan Yang, Ka-Fai Un, Jun Yin, Rui Paulo Martins, Pui-In Mak
2025 — conf
A 94.8nW Battery-Free Intelligent Silicon Platform Enabling Distributed, Adaptive, and Event-Driven Multimodal Sensing at the Edge.
ISSCC
Haochen Zhang, Wei-Han Yu, Zhongyu Zhao, Zhizhan Yang, Ka-Fai Un, Jun Yin, Rui Paulo Martins, Pui-In Mak
2025 J jnl
A 97.8 GOPS/W FPGA-Based Residual-Block-Aware CNN Accelerator Featuring Multi-Clock PW
IEEE Trans. Circuits Syst. I Regul. Pap.
Jixuan Li, Ke Li, Ka-Fai Un, Wei-Han Yu, Rui Paulo Martins, Pui-In Mak
2025 — conf
A Keyword-Spotting(KWS) Chip Featuring a Bio-Inspired Neuron Model in 65-nm CMOS.
CNIOT
Yantong Liu, Fei Tan, Ka-Fai Un, Wei-Han Yu, Rui Paulo Martins, Pui-In Mak
2025 J jnl
An 800-MHz 8.17-TOPS/W 0.63-TOPS/mm
IEEE J. Solid State Circuits
Jixuan Li, Ke Li, Ka-Fai Un, Wei-Han Yu, Rui Paulo Martins, Pui-In Mak
2025 J jnl
GSLP-CIM: A 28-nm Globally Systolic and Locally Parallel CNN/Transformer Accelerator With Scalable and Reconfigurable eDRAM Compute-in-Memory Macro for Flexible Dataflow.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yi Zhan, Wei-Han Yu, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak
2025 — conf
On the Usage of Genetic Algorithms, Reinforcement Learning and Bayesian Optimisation for RF IC Design Automation.
SMACD
Margarida Lourenço, Bingbing Zhao, Junde Li, Marcelino B. Santos, Pui-In Mak, Rui Paulo Martins, Wei-Han Yu, Fábio Passos
2024 — conf
17.9 A 1.8% FAR, 2ms Decision Latency, 1.73nJ/Decision Keywords Spotting (KWS) Chip Incorporating Transfer-Computing Speaker Verification, Hybrid-Domain Computing and Scalable 5T-SRAM.
ISSCC
Fei Tan, Wei-Han Yu, Jinhai Lin, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak
2024 J jnl
A 0.05-mm
IEEE J. Solid State Circuits
Fei Tan, Wei-Han Yu, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak
2024 — conf
A 10-bit Two-Stage Pipeline SAR ADC in 55nm CMOS for Compute-in-Memory Applications.
APCCAS
Xiapeng Xu, Yongteng Ma, Xuliang Yu, Fanzi Meng, Wei-Han Yu, Liang Zhao
2024 J jnl
A 1024-Channel 268-nW/Pixel 36×36 μm
IEEE J. Solid State Circuits
Moon Hyung Jang, Maddy Hays, Wei-Han Yu, Changuk Lee, Pietro Caragiulo, Athanasios T. Ramkaj, Pingyu Wang, A. J. Phillips, Nick Vitale, Pulkit Tandon, Pumiao Yan, Pui-In Mak, Youngcheol Chae, E. J. Chichilnisky, Boris Murmann, Dante G. Muratore
2024 J jnl
A 119.64 GOPs/W FPGA-Based ResNet50 Mixed-Precision Accelerator Using the Dynamic DSP Packing.
IEEE Trans. Circuits Syst. II Express Briefs
Yaozhong Ou, Wei-Han Yu, Ka-Fai Un, Chi-Hang Chan, Yan Zhu
2024 J jnl
A 28-nm 18.7 TOPS/mm² 89.4-to-234.6 TOPS/W 8b Single-Finger eDRAM Compute-in-Memory Macro With Bit-Wise Sparsity Aware and Kernel-Wise Weight Update/Refresh.
IEEE J. Solid State Circuits
Yi Zhan, Wei-Han Yu, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak
2024 J jnl
A 512-nW 0.003-mm² Forward-Forward Closed Box Trainer for an Analog Voice Activity Detector in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Junde Li, Guoqiang Xin, Wei-Han Yu, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak
2024 — conf
A 5T-SRAM Based Computing-in-Memory Macro Featuring Partial Sum Boosting and Analog Non-Uniform Quantization.
MWSCAS
Guoqiang Xin, Fei Tan, Junde Li, Junren Chen, Wei-Han Yu, Ka-Fai Un, Rui Paulo Martins, Pui-In Mak
2024 J jnl
A ULP Long-Range Active-RF Tag With Automatically Calibrated Antenna-TRX Interface.
IEEE J. Solid State Circuits
Zhizhan Yang, Jun Yin, Wei-Han Yu, Haochen Zhang, Rui Paulo Martins, Pui-In Mak
2024 J jnl
An FPGA-Based Transformer Accelerator With Parallel Unstructured Sparsity Handling for Question-Answering Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Rujian Cao, Zhongyu Zhao, Ka-Fai Un, Wei-Han Yu, Rui Paulo Martins, Pui-In Mak
2024 J jnl
CLUT-CIM: A Capacitance Lookup Table-Based Analog Compute-in-Memory Macro With Signed-Channel Training and Weight Updating for Nonuniform Quantization.
IEEE Trans. Circuits Syst. I Regul. Pap.
Yuzhao Fu, Jixuan Li, Wei-Han Yu, Ka-Fai Un, Chi-Hang Chan, Yan Zhu, Rui Paulo Martins, Pui-In Mak
2024 J jnl
FLEX-CIM: A Flexible Kernel Size 1-GHz 181.6-TOPS/W 25.63-TOPS/mm
IEEE J. Solid State Circuits
Yuzhao Fu, Wei-Han Yu, Ka-Fai Un, Chi-Hang Chan, Yan Zhu, Minglei Zhang, Rui Paulo Martins, Pui-In Mak
2023 — conf
A 1024-Channel 268 nW/pixel 36x36 μm
VLSI Technology and Circuits
Moon Hyung Jang, Wei-Han Yu, Changuk Lee, Maddy Hays, Pingyu Wang, Nick Vitale, Pulkit Tandon, Pumiao Yan, Pui-In Mak, Youngcheol Chae, E. J. Chichilnisky, Boris Murmann, Dante G. Muratore
2023 J jnl
A 47-nW Voice Activity Detector (VAD) Featuring a Short-Time CNN Feature Extractor and an RNN-Based Classifier With a Non-Volatile CAP-ROM.
IEEE J. Solid State Circuits
Jinhai Lin, Ka-Fai Un, Wei-Han Yu, Rui Paulo Martins, Pui-In Mak
2023 — conf
A 47nW Mixed-Signal Voice Activity Detector (VAD) Featuring a Non-Volatile Capacitor-ROM, a Short-Time CNN Feature Extractor and an RNN Classifier.
ISSCC
Jinhai Lin, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2023 — conf
A ULP Long-Range Active-RF Tag with Automatic Antenna-Interface Calibration Achieving 20.5% TX Efficiency at -22dBm EIRP, and -60.4dBm Sensitivity at 17.8nW RX Power.
ISSCC
Zhizhan Yang, Jun Yin, Wei-Han Yu, Haochen Zhang, Pui-In Mak, Rui Paulo Martins
2023 J jnl
An FPGA-Based Transformer Accelerator Using Output Block Stationary Dataflow for Object Recognition Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Zhongyu Zhao, Rujian Cao, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2022 J jnl
A 108-nW 0.8-mm
IEEE J. Solid State Circuits
Feifei Chen, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2022 — conf
A 108nW 0.8mm
ISSCC
Feifei Chen, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2022 — conf
Design and Implementation of a Low Power Switched-Capacitor-Based Analog Feature Extractor for Voice Keyword Spotting.
APCCAS
Feifei Chen, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2021 — conf
A 4-bit Mixed-Signal MAC Array with Swing Enhancement and Local Kernel Memory.
MWSCAS
Wei-Han Yu, Massimo Giordano, Rohan Doshi, Minglei Zhang, Pui-In Mak, Rui Paulo Martins, Boris Murmann
2021 — conf
A 50.4 GOPs/W FPGA-Based MobileNetV2 Accelerator using the Double-Layer MAC and DSP Efficiency Enhancement.
A-SSCC
Jixuan Li, Jiabao Chen, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2021 J jnl
An FPGA-Based Energy-Efficient Reconfigurable Convolutional Neural Network Accelerator for Object Recognition Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Jixuan Li, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2019 J jnl
A 0.2-V Energy-Harvesting BLE Transmitter With a Micropower Manager Achieving 25% System Efficiency at 0-dBm Output and 5.2-nW Sleep Power in 28-nm CMOS.
IEEE J. Solid State Circuits
Shiheng Yang, Jun Yin, Haidong Yi, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2019 J jnl
A 40-Gb/s PAM-4 Transmitter Using a 0.16-pJ/bit SST-CML-Hybrid (SCH) Output Driver and a Hybrid-Path 3-Tap FFE Scheme in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chao Fan, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2018 J jnl
A 0.18-V 382-µW Bluetooth Low-Energy Receiver Front-End With 1.33-nW Sleep Power for Energy-Harvesting Applications in 28-nm CMOS.
IEEE J. Solid State Circuits
Haidong Yi, Wei-Han Yu, Pui-In Mak, Jun Yin, Rui Paulo Martins
2018 — conf
A 0.2V energy-harvesting BLE transmitter with a micropower manager achieving 25% system efficiency at 0dBm output and 5.2nW sleep power in 28nm CMOS.
ISSCC
Jun Yin, Shiheng Yang, Haidong Yi, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2018 J jnl
A 0.7-2.5 GHz, 61% EIRP System Efficiency, Four-Element MIMO TX System Exploiting Integrated Power-Relaxed Power Amplifiers and an Analog Spatial De-Interleaver.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wei-Han Yu, Ka-Fai Un, Pui-In Mak, Rui Paulo Martins
2018 J jnl
A Coin-Battery-Powered LDO-Free 2.4-GHz Bluetooth Low-Energy Transmitter With 34.7% Peak System Efficiency.
IEEE Trans. Circuits Syst. II Express Briefs
Xingqiang Peng, Jun Yin, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2017 — conf
24.4 A 0.18V 382µW bluetooth low-energy (BLE) receiver with 1.33nW sleep power for energy-harvesting applications in 28nm CMOS.
ISSCC
Wei-Han Yu, Haidong Yi, Pui-In Mak, Jun Yin, Rui Paulo Martins
2017 J jnl
A 2.4-GHz ZigBee Transmitter Using a Function-Reuse Class-F DCO-PA and an ADPLL Achieving 22.6% (14.5%) System Efficiency at 6-dBm (0-dBm) P
IEEE J. Solid State Circuits
Xingqiang Peng, Jun Yin, Pui-In Mak, Wei-Han Yu, Rui Paulo Martins
2017 J jnl
A High-Voltage-Enabled Class-D Polar PA Using Interactive AM-AM Modulation, Dynamic Matching, and Power-Gating for Average PAE Enhancement.
IEEE Trans. Circuits Syst. I Regul. Pap.
Wei-Han Yu, Xingqiang Peng, Pui-In Mak, Rui Paulo Martins
2015 J jnl
A Combinatorial Impairment-Compensation Digital Predistorter for a Sub-GHz IEEE 802.11af-WLAN CMOS Transmitter Covering a 10x-Wide RF Bandwidth.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chak-Fong Cheang, Ka-Fai Un, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins
2013 J jnl
A Nonrecursive Digital Calibration Technique for Joint Elimination of Transmitter and Receiver I/Q Imbalances With Minimized Add-On Hardware.
IEEE Trans. Circuits Syst. II Express Briefs
Wei-Han Yu, Chak-Fong Cheang, Pui-In Mak, Weng-Fai Cheng, Ka-Fai Un, U-Wai Lok, Rui Paulo Martins
2012 — conf
A dynamic-range-improved 2.4GHz WLAN class-E PA combining PWPM and cascode modulation.
APCCAS
Yinsidi Jiao, Wei-Han Yu, Pui-In Mak, Rui Paulo Martins