| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2024 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2021 | Misc | conf |
ICMLC
|
| 2019 | A* | conf |
NeurIPS
|
| 2019 | — | conf |
ISOCC
|
| 2014 | J | jnl |
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2013 | J | jnl |
IEEE Trans. Veh. Technol.
|
| 2011 | J | jnl |
Design and implementation of a high-throughput fully parallel complex-valued QR factorisation chips.
IET Circuits Devices Syst.
|
| 2010 | C | conf |
ISCAS
|
| 2009 | — | conf |
IIH-MSP
|
| 2008 | C | conf |
ISCAS
|
| 2007 | — | conf |
Web Intelligence/IAT Workshops
|