Wei-Chung Lo - RankMe

22 papers C 1Journal 6Unranked 15

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A 16nm, 1Mb, 1-to-8b-Configurable 444.21TOPS/W Fully Digital SRAM Compute-in-Memory Macro for Hybrid SNN-CNN Edge Computing. ISSCC Yao-Kai Yeh, Jian-Wei Su, Ting-Hao Hsu, Mai Tseng, Jen-Chun Tien, Ko-Chi Chen, Chih-Yen Yue, Yu-En Lin, Yu-Jia Hu, Le-Jung Hsieh, Jyun-Cheng Bai, Yu-Sheng Kao, Tsung-Han Lou, Hung-Hsi Hsu, De-Qi You, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Ya-Tang Yang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2025	J	`jnl`	CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device. CoRR Yan-Cheng Guo, Tian-Sheuan Chang, Chih-Sheng Lin, Bo-Cheng Chiou, Chih-Ming Lai, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang
2025	J	`jnl`	Miniaturized and Cost-Effective Programmable 2.5D/3.5D Platforms Enabled by Scalable Embedded Active Bridge Chipset. IEEE J. Emerg. Sel. Topics Circuits Syst. Wei Lu, Jie Zhang, Yi-Hui Wei, Hsu-Ming Hsiao, Sih-Han Li, Chao-Kai Hsu, Chih-Cheng Hsiao, Feng-Hsiang Lo, Shyh-Shyuan Sheu, Chin-Hung Wang, Ching-Iang Li, Yung-Sheng Chang, Ming-Ji Dai, Wei-Chung Lo, Shih-Chieh Chang, Hung-Ming Chen, Kuan-Neng Chen, Po-Tsang Huang
2024	J	`jnl`	8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips. IEEE Trans. Circuits Syst. II Express Briefs Jian-Wei Su, Pei-Jung Lu, Ping-Chun Wu, Yen-Chi Chou, Ta-Wei Liu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Hao-Chiao Hong, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2024	J	`jnl`	A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips. IEEE J. Solid State Circuits Ping-Chun Wu, Jian-Wei Su, Li-Yang Hong, Jin-Sheng Ren, Chih-Han Chien, Ho-Yu Chen, Chao-En Ke, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2024	J	`jnl`	An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips. IEEE J. Solid State Circuits Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2024	C	`conf`	CIMR-V: An End-to-End SRAM-based CIM Accelerator with RISC-V for AI Edge Device. ISCAS Yan-Cheng Guo, Tian-Sheuan Chang, Chih-Sheng Lin, Bo-Cheng Chiou, Chih-Ming Lai, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang
2024	—	`conf`	Empowering Local Differential Privacy: A 5718 TOPS/W Analog PUF-Based In-Memory Encryption Macro for Dynamic Edge Security. VLSI Technology and Circuits Chih-Sheng Lin, Bo-Cheng Chiou, Yin-Jia Yang, Jian-Wei Su, Kuo-Hua Tseng, Yun-Ting Ho, Chih-Ming Lai, Sih-Han Li, Tian-Sheuan Chang, Shan-Ming Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Tuo-Hung Hou
2024	—	`conf`	Scalable Embedded Multi-Die Active Bridge (S-EMAB) Chips with Integrated LDOs for Low-Cost Programmable 2.5D/3.5D Packaging Technology. VLSI Technology and Circuits Wei Lu, Jie Zhang, Yi-Hui Wei, Hsu-Ming Hsiao, Sih-Han Li, Chao-Kai Hsu, Chih-Cheng Hsiao, Feng-Hsiang Lo, Shyh-Shyuan Sheu, Chin-Hung Wang, Wei-Chung Lo, Shih-Chieh Chang, Hung-Ming Chen, Kuan-Neng Chen, Po-Tsang Huang
2023	—	`conf`	A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices. ISSCC Ping-Chun Wu, Jian-Wei Su, Li-Yang Hong, Jin-Sheng Ren, Chih-Han Chien, Ho-Yu Chen, Chao-En Ke, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2023	J	`jnl`	A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips. IEEE J. Solid State Circuits Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Tianlong Pan, Chuan-Jia Jhang, Wei-Hsing Huang, Chih-Han Chien, Peng-I Mei, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2023	—	`conf`	U-MRAM: Transistor-Less, High-Speed (10 ns), Low-Voltage (0.6 V), Field-Free Unipolar MRAM for High-Density Data Memory. VLSI Technology and Circuits Ming-Hung Wu, Ming-Chun Hong, Ching Shih, Yao-jen Chang, Yu-Chen Hsin, Shih-Ching Chiu, Kuan-Ming Chen, Yi-Hui Su, Chih-Yao Wang, Shan-Yi Yang, Guan-Long Chen, Hsin-Han Lee, Sk. Ziaur Rahaman, I-Jung Wang, Chen-Yi Shih, Tsun-Chun Chang, Jeng-Hua Wei, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Tuo-Hung Hou
2022	—	`conf`	A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices. ISSCC Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chih-I Wu, Meng-Fan Chang
2022	—	`conf`	A 4K-400K Wide Operating-Temperature-Range MRAM Technology with Ultrathin Composite Free Layer and Magnesium Spacer. VLSI Technology and Circuits Ming-Chun Hong, Yao-jen Chang, Yu-Chen Hsin, Liang-Ming Liu, Kuan-Ming Chen, Yi-Hui Su, Guan-Long Chen, Shan-Yi Yang, I-Jung Wang, Sk. Ziaur Rahaman, Hsin-Han Lee, Shih-Ching Chiu, Chen-Yi Shih, Chih-Yao Wang, Fang-Ming Chen, Jeng-Hua Wei, Shyh-Shyuan Sheu, Wei-Chung Lo, Minn-Tsong Lin, Chih-I Wu, Tuo-Hung Hou
2022	—	`conf`	An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology. VLSI Technology and Circuits Jie Zhang, Wei Lu, Po-Tsang Huang, Sih-Han Li, Tsung-Yi Hung, Shih-Hsien Wu, Ming-Ji Dai, I-Shan Chung, Wen-Chao Chen, Chin-Hung Wang, Shyh-Shyuan Sheu, Hung-Ming Chen, Kuan-Neng Chen, Wei-Chung Lo, Chih-I Wu
2021	—	`conf`	16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips. ISSCC Jian-Wei Su, Yen-Chi Chou, Ruhui Liu, Ta-Wei Liu, Pei-Jung Lu, Ping-Chun Wu, Yen-Lin Chung, Li-Yang Hung, Jin-Sheng Ren, Tianlong Pan, Sih-Han Li, Shih-Chieh Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Chih-I Wu, Xin Si, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang
2021	—	`conf`	A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration. A-SSCC Chih-Sheng Lin, Fu-Cheng Tsai, Jian-Wei Su, Sih-Han Li, Tian-Sheuan Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chih-I Wu, Tuo-Hung Hou
2015	—	`conf`	3D research activities in ITRI. 3DIC Wei-Chung Lo
2013	—	`conf`	Performance and process characteristic of glass interposer with through-glass-via(TGV). 3DIC Chun-Hsien Chien, Hsun Yu, Ching-Kuan Lee, Yu-Min Lin, Ren-Shin Cheng, Chau-Jie Zhan, Peng-Shu Chen, Chang-Chih Liu, Chao-Kai Hsu, Hsiang-Hung Chang, Huan-Chun Fu, Yuan-Chang Lee, Wen-Wei Shen, Cheng-Ta Ko, Wei-Chung Lo, Yung Jean Lu
2011	—	`conf`	Cu-based bonding technology for 3D integration applications. 3DIC Kuan-Neng Chen, Z. Xu, Fei Liu, Cheng-Ta Ko, Chuan-An Cheng, W. C. Huang, H. L. Lin, C. Cabral, Zhi-Cheng Hsiao, N. Klymko, Hsin-Chia Fu, Y. H. Chen, Jian-Qiang Lu, Wei-Chung Lo
2011	—	`conf`	Wafer-level 3D integration with Cu TSV and micro-bump/adhesive hybrid bonding technologies. 3DIC Cheng-Ta Ko, Zhi-Cheng Hsiao, Y. J. Chang, Peng-Shu Chen, J. H. Huang, Hsin-Chia Fu, Y. J. Huang, C. W. Chiang, W. L. Tsat, Y. H. Chen, Wei-Chung Lo, Kuan-Neng Chen
2010	—	`conf`	Wafer-level 3D integration using hybrid bonding. 3DIC Cheng-Ta Ko, Kuan-Neng Chen, Wei-Chung Lo, Chuan-An Cheng, Wen-Chun Huang, Zhi-Cheng Hsiao, Huan-Chun Fu, Yu-Hua Chen