Wei-Bin Yang - RankMe

39 papers C 5Journal 16Unranked 18

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	A Hierarchical Tree-Structured Control Digital Low Drop-out Regulator with Status-Dumping Mechanism. ISOCC Jiann-Chyi Rau, Wei-Bin Yang, Yu-Lung Lo, Chin-Yuan Shih, Cheng-Kai Lin, Che-Chia Chuang
2024	—	`conf`	A Programmable DLL-based Delay Chain. ISOCC Yu-Wei Huang, Cheng-En Wu, Wei-Bin Yang, Jen-Chieh Liu
2024	J	`jnl`	Texture Classification Network Integrating Adaptive Wavelet Transform. CoRR Su-Xi Yu, Jing-Yuan He, Yi Wang, Yu-Jiao Cai, Jun Yang, Bo Lin, Wei-Bin Yang, Jian Ruan
2022	J	`jnl`	A Programmable Multiple Frequencies Clock Generator With Process and Temperature Compensation Circuit for System on Chip Design. IEEE Syst. J. Wei-Bin Yang, Kuo-Ning Chang, Lu-Chun Yeh
2022	J	`jnl`	ThreshNet: An Efficient DenseNet Using Threshold Mechanism to Reduce Connections. IEEE Access Rui-Yang Ju, Ting-Yu Lin, Jia-Hao Jian, Jen-Shiun Chiang, Wei-Bin Yang
2022	J	`jnl`	ThreshNet: An Efficient DenseNet using Threshold Mechanism to Reduce Connections. CoRR Rui-Yang Ju, Ting-Yu Lin, Jia-Hao Jian, Jen-Shiun Chiang, Wei-Bin Yang
2021	J	`jnl`	Asynchronous Digital Low-Dropout Regulator With Dual Adjustment Mode in Ultra-Low Voltage Input. IEEE Access Wei-Bin Yang, Chi-Hsuan Sun, Diptendu Sinha Roy, Yi-Mei Chen
2021	—	`conf`	Asynchronous Domino Binary search Digital LDO. ISPACS Wei-Bin Yang, Shu-Yu Ku, Chun-Wei Wang, Li-Lun Chu
2021	J	`jnl`	Instrumentation of Twin-MCMs based mutual-test. Microelectron. J. Shun Shen Peter Wang, Yin-Tien Wang, Choung-Lii Chao, Wei-Bin Yang
2017	J	`jnl`	A Selectable Discrete-Voltage Output and Fast-Settling Low-Dropout Regulator Using Half Digitally-Assistant Voltage Accelerator. J. Signal Process. Syst. Wei-Bin Yang, Ming-Hao Hong, Jsung Mo Shen
2017	J	`jnl`	Design of Fast-Locked Digitally Controlled Low-Dropout Regulator for Ultra-low Voltage Input. Circuits Syst. Signal Process. Wei-Bin Yang, Yu-Yao Lin, Yu-Lung Lo
2016	J	`jnl`	A 25 MHz crystal less clock generator with background calibration against process and temperature variation. Comput. Electr. Eng. Wei-Bin Yang, Ming-Hao Hong
2015	—	`conf`	Analysis and design considerations of static CMOS logics under process, voltage and temperature variation in UMC 0.18µm CMOS process. ISPACS Wei-Bin Yang, Yu-Yao Lin, Chi-Hsiung Wang, Kuo-Ning Chang, Cing-Huan Chen, Yu-Lung Lo
2013	C	`conf`	A GHz full-division-range programmable divider with output duty-cycle improved. DDECS Yu-Lung Lo, Jhih-Wei Tsai, Han-Ying Liu, Wei-Bin Yang
2013	J	`jnl`	A multiple frequency clock generator using wide operation frequency range phase interpolator. Microelectron. J. Wei-Bin Yang, Chi-Hsiung Wang, Sheng-Shih Yeh, Chao-Cheng Liao
2012	—	`conf`	A 300 mV 10 MHz 4 kb 10T subthreshold SRAM for ultralow-power application. ISPACS Wei-Bin Yang, Chi-Hsiung Wang, I-Ting Chuo, Huang-Hsuan Hsu
2011	J	`jnl`	A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process. Microelectron. J. Wei-Bin Yang, Chao-Cheng Liao, Yung-Chih Liang
2011	—	`conf`	A new temperature independent current controlled oscillator. ISPACS Zheng-Yi Huang, Jen-Shiun Chiang, Wei-Bin Yang, Chi-Hsiung Wang
2011	J	`jnl`	A synthesizable pseudo fractional-N clock generator with improved duty cycle output. Microelectron. J. Wei-Bin Yang, Chang-Yo Hsieh
2010	J	`jnl`	A Pseudo Fractional- IEICE Trans. Electron. Wei-Bin Yang, Yu-Lung Lo, Ting-Sheng Chao
2009	C	`conf`	0.5V 160-MHz 260uW all digital phase-locked loop. DDECS Jen-Chieh Liu, Hong-Yi Huang, Wei-Bin Yang, Kuo-Hsing Cheng
2009	J	`jnl`	Designing an Ultralow-Voltage Phase-Locked Loop Using a Bulk-Driven Technique. IEEE Trans. Circuits Syst. II Express Briefs Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng
2009	—	`conf`	Designing ultra-low voltage PLL Using a bulk-driven technique. ESSCIRC Ting-Sheng Chao, Yu-Lung Lo, Wei-Bin Yang, Kuo-Hsing Cheng
2009	J	`jnl`	High-Speed and Ultra-Low-Voltage Divide-by-4/5 Counter for Frequency Synthesizer. IEICE Trans. Electron. Yu-Lung Lo, Wei-Bin Yang, Ting-Sheng Chao, Kuo-Hsing Cheng
2008	C	`conf`	A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. DDECS Kuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang, Yu-Lung Lo, Wei-Bin Yang, Jiunn-Way Miaw
2007	—	`conf`	A 100 MHz-1 GHz Adaptive Bandwidth PLL Using TDC Technique. ICECS Kuo-Hsing Cheng, Yu-Lung Lo, Ching-Wen Lai, Wei-Bin Yang
2007	C	`conf`	New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode. ISCAS Chung-Yu Chang, Wei-Bin Yang, Ching-Ji Huang, Cheng-Hsing Chien
2006	—	`conf`	A New Dynamic Floating Input D Flip-Flop (DFIDFF) for High Speed and Ultra Low Voltage Divided-by 4/5 Prescaler. ICECS Ting-Sheng Jau, Wei-Bin Yang, Yu-Lung Lo
2006	—	`conf`	A Variable Duty Cycle with High-Resolution Synchronous Mirror Delay. ICECS Kai-Wei Hong, Chien-Hsien Lee, Kuo-Hsing Cheng, Chen-Lung Wu, Wei-Bin Yang
2006	—	`conf`	Analysis and Design of High Performance, Low Power Multiple Ports Register Files. APCCAS Ting-Sheng Jau, Wei-Bin Yang, Chung-Yu Chang
2006	C	`conf`	The new improved pseudo fractional-N clock generator with 50% duty cycle. ISCAS Shu-Chang Kuo, Tzu-Chien Hung, Wei-Bin Yang
2005	—	`conf`	A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. ISCAS (2) Kuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang
2005	—	`conf`	The new approach of programmable pseudo fractional-N clock generator for GHz operation with 50% duty cycle. ECCTD Wei-Bin Yang, Shu-Chang Kuo, Yuan-Hua Chu, Kuo-Hsing Cheng
2004	—	`conf`	A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop. ISCAS (1) Kuo-Hsing Cheng, Wei-Bin Yang, Shu-Chang Kuo
2003	J	`jnl`	A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phase-locked loop. IEEE Trans. Circuits Syst. II Express Briefs Kuo-Hsing Cheng, Wei-Bin Yang, Cheng-Ming Ying
2001	—	`conf`	A CMOS low power voltage controlled oscillator with split-path controller. ICECS Kuo-Hsing Cheng, Lin-Jiunn Tzou, Wei-Bin Yang, Shyh-Shyuan Sheu
2001	—	`conf`	A difference detector PFD for low jitter PLL. ICECS Kuo-Hsing Cheng, Tse-Hua Yao, Shu-Yu Jiang, Wei-Bin Yang
2001	—	`conf`	A low-power high driving ability voltage control oscillator used in PLL. ISCAS (4) Kuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung
1999	—	`conf`	The suggestion for CFS CMOS buffer. ICECS Kuo-Hsing Cheng, Wei-Bin Yang