Wayne Luk - RankMe

729 papers A* 16A 40B 116C 18Misc 76Journal 209Unranked 249

Year	Rank	Type	Title / Venue / Authors
2026	A*	`conf`	Advancing Full-Stack Acceleration for SchröDinger-Style Quantum Simulation. HPCA Shuang Liang, Yuncheng Lu, Ce Guo, Paul H. J. Kelly, Wayne Luk, Hongxiang Fan
2026	A	`conf`	CODESCA: Co-Design for Spectral Clustering Acceleration. FPGA Zhengyan Liu, Ce Guo, Zehuan Zhang, Qiang Liu, Wayne Luk
2026	J	`jnl`	Dynamic Expert Sharing: Decoupling Memory from Parallelism in Mixture-of-Experts Diffusion LLMs. CoRR Hao Mark Chen, Zhiwen Mo, Royson Lee, Qianzhou Wang, Da Li, Shell Xu Hu, Wayne Luk, Timothy M. Hospedales, Hongxiang Fan
2026	—	`conf`	Enhancing Trustworthiness with Mixed Precision: Benchmarks, Opportunities, and Challenges. ASP-DAC Guanxi Lu, Hao Mark Chen, Zhiqiang Que, Wayne Luk, Hongxiang Fan
2026	—	`conf`	FastTTS: Accelerating Test-Time Scaling for Edge LLM Reasoning. ASPLOS (2) Hao Mark Chen, Zhiwen Mo, Guanxi Lu, Shuang Liang, Lingxiao Ma, Wayne Luk, Hongxiang Fan
2026	A	`conf`	HGQ: High Granularity Quantization for Real-time Neural Networks on FPGAs. FPGA Chang Sun, Zhiqiang Que, Thea Aarrestad, Vladimir Loncar, Jennifer Ngadiuba, Wayne Luk, Maria Spiropulu
2026	J	`jnl`	JetFormer: A Scalable and Efficient Transformer for Jet Tagging from Offline Analysis to FPGA Triggers. CoRR Ruoqing Zheng, Chang Sun, Qibin Liu, Lauri Laatu, Arianna Cox, Benedikt Maier, Alexander D. Tapper, José Gabriel F. Coutinho, Wayne Luk, Zhiqiang Que
2026	J	`jnl`	Memory-Efficient and Trustworthy Neural Networks via Random Seed-Based Design. IEEE Access Hiroaki Ito, Hikari Otsuka, Ryota Yasudo, Zhiqiang Que, José Gabriel F. Coutinho, Daichi Fujiki, Masato Motomura, Ce Guo, Wayne Luk
2026	J	`jnl`	VCDF: A Validated Consensus-Driven Framework for Time Series Causal Discovery. CoRR Gene Yu, Ce Guo, Wayne Luk
2026	J	`jnl`	da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAs. ACM Trans. Reconfigurable Technol. Syst. Chang Sun, Zhiqiang Que, Vladimir Loncar, Wayne Luk, Maria Spiropulu
2025	J	`jnl`	A3 : an Analytical Low-Rank Approximation Framework for Attention. CoRR Jeffrey T. H. Wong, Cheng Zhang, Xinye Cao, Pedro Gimenes, George A. Constantinides, Wayne Luk, Yiren Zhao
2025	J	`jnl`	ASPO: Constraint-Aware Bayesian Optimization for FPGA-based Soft Processors. CoRR Haoran Wu, Ce Guo, Wayne Luk, Robert Mullins
2025	J	`jnl`	Accelerating 3D Gaussian Splatting with Neural Sorting and Axis-Oriented Rasterization. CoRR Zhican Wang, Guanghui He, Dantong Liu, Lingjun Gao, Shell Xu Hu, Chen Zhang, Zhuoran Song, Nicholas D. Lane, Wayne Luk, Hongxiang Fan
2025	J	`jnl`	An approach to sociotechnical transparency of social media algorithms using agent-based modelling. AI Ethics Anna Gausen, Ce Guo, Wayne Luk
2025	B	`conf`	Aspo: Constraint-Aware Bayesian Optimization for Fpga-Based Soft Processors. FPL Haoran Wu, Ce Guo, Wayne Luk, Robert Mullins
2025	J	`jnl`	Combating the Memory Walls: Optimization Pathways for Long-Context Agentic LLM Inference. CoRR Haoran Wu, Can Xiao, Jiayi Nie, Xuan Guo, Binglei Lou, Jeffrey T. H. Wong, Zhiwen Mo, Cheng Zhang, Przemyslaw Forys, Wayne Luk, Hongxiang Fan, Jianyi Cheng, Timothy M. Jones, Rika Antonova, Robert Mullins, Aaron Zhao
2025	J	`jnl`	Democratizing Agentic AI with Fast Test-Time Scaling on the Edge. CoRR Hao Mark Chen, Zhiwen Mo, Guanxi Lu, Shuang Liang, Lingxiao Ma, Wayne Luk, Hongxiang Fan
2025	Misc	`conf`	Efficient Adaptable Streaming Aggregation Engine. FCCM Philippos Papaphilippou, Wayne Luk, David Gregg
2025	A*	`conf`	Enhancing LLM-based Quantum Code Generation with Multi-Agent Optimization and Quantum Error Correction. DAC Charlie Campbell, Hao Mark Chen, Wayne Luk, Hongxiang Fan
2025	J	`jnl`	Enhancing LLM-based Quantum Code Generation with Multi-Agent Optimization and Quantum Error Correction. CoRR Charlie Campbell, Hao Mark Chen, Wayne Luk, Hongxiang Fan
2025	J	`jnl`	Enhancing Trustworthiness with Mixed Precision: Benchmarks, Opportunities, and Challenges. CoRR Guanxi Lu, Hao Mark Chen, Zhiqiang Que, Wayne Luk, Hongxiang Fan
2025	—	`conf`	FABS: An Extensible and High-Performance Digital Twin Framework of AI-Driven Financial Systems. ICAIF Angus T. L. Leung, Ce Guo, Wayne Luk
2025	J	`jnl`	FW-Merging: Scaling Model Merging with Frank-Wolfe Optimization. CoRR Hao Mark Chen, Shell Xu Hu, Wayne Luk, Timothy M. Hospedales, Hongxiang Fan
2025	—	`conf`	Hardware-Aware Parallel Prompt Decoding for Memory-Efficient Acceleration of LLM Inference. EMNLP (Findings) Hao Mark Chen, Wayne Luk, Yiu Ka Fai Cedric, Rui Li, Konstantin Mishchenko, Stylianos I. Venieris, Hongxiang Fan
2025	J	`jnl`	JEDI-linear: Fast and Efficient Graph Neural Networks for Jet Tagging on FPGAs. CoRR Zhiqiang Que, Chang Sun, Sudarshan Paramesvaran, Emyr John Clement, Katerina Karakoulaki, Christopher Brown, Lauri Laatu, Arianna Cox, Alexander D. Tapper, Wayne Luk, Maria Spiropulu
2025	J	`jnl`	Learning spatial hearing via innate mechanisms. PLoS Comput. Biol. Yang Chu, Wayne Luk, Dan F. M. Goodman
2025	J	`jnl`	Low-Latency FPGA Control System for Real-Time Neural Network Processing in CCD-Based Trapped-Ion Qubit Measurement. CoRR Binglei Lou, Gautham Duddi Krishnaswaroop, Filip Wojcicki, Ruilin Wu, Richard Rademacher, Zhiqiang Que, Wayne Luk, Philip H. W. Leong
2025	J	`jnl`	MetaML-Pro: Cross-Stage Design Flow Automation for Efficient Deep Learning Acceleration. CoRR Zhiqiang Que, José Gabriel F. Coutinho, Ce Guo, Hongxiang Fan, Wayne Luk
2025	J	`jnl`	On the Existence and Behaviour of Secondary Attention Sinks. CoRR Jeffrey T. H. Wong, Cheng Zhang, Louis Mahon, Wayne Luk, Anton Isopoussu, Yiren Zhao
2025	—	`conf`	Permuting Accumulation Order for Low-Precision Machine Learning. ASAP Ebby Samson, Tony Liu, Wayne Luk, George A. Constantinides
2025	—	`conf`	ProtoHedge: Interpretable Hedging with Market Prototypes. ICAIF Lisa Faloughi, Ce Guo, Wayne Luk
2025	J	`jnl`	ProtoPGTN: A Scalable Prototype-Based Gated Transformer Network for Interpretable Time Series Classification. Inf. Jinjin Huang, Ce Guo, Wayne Luk
2025	—	`conf`	Repurposing Language Models for FX Volatility Forecasting: A Data-Efficient and Context-Aware Approach. ICAIF Quoc Anh Nguyen, Ce Guo, Wayne Luk
2025	—	`conf`	Resource and Phase Awareness for Dynamically Scheduled High-Level Synthesis. HEART Mathias Bouilloud, Lana Josipovic, Wayne Luk
2025	J	`jnl`	Sub-microsecond Transformers for Jet Tagging on FPGAs. CoRR Lauri Laatu, Chang Sun, Arianna Cox, Abhijith Gandrakota, Benedikt Maier, Jennifer Ngadiuba, Zhiqiang Que, Wayne Luk, Maria Spiropulu, Alexander D. Tapper
2025	—	`conf`	Trustworthy Deep Learning Acceleration with Customizable Design Flow Automation. HEART Zhiqiang Que, Hongxiang Fan, Gabriel F. Figueiredo, Ce Guo, Wayne Luk, Ryota Yasudo, Masato Motomura
2025	A*	`conf`	Versatile Cross-platform Compilation Toolchain for Schrödinger-style Quantum Circuit Simulation. DAC Yuncheng Lu, Shuang Liang, Hongxiang Fan, Ce Guo, Wayne Luk, Paul H. J. Kelly
2025	J	`jnl`	Versatile Cross-platform Compilation Toolchain for Schrödinger-style Quantum Circuit Simulation. CoRR Yuncheng Lu, Shuang Liang, Hongxiang Fan, Ce Guo, Wayne Luk, Paul H. J. Kelly
2025	J	`jnl`	da4ml: Distributed Arithmetic for Real-time Neural Networks on FPGAs. CoRR Chang Sun, Zhiqiang Que, Vladimir Loncar, Wayne Luk, Maria Spiropulu
2025	J	`jnl`	hls4ml: A Flexible, Open-Source Platform for Deep Learning Acceleration on Reconfigurable Hardware. CoRR Jan-Frederik Schulte, Benjamin Ramhorst, Chang Sun, Jovan Mitrevski, Nicolò Ghielmetti, Enrico Lupi, Dimitrios Danopoulos, Vladimir Loncar, Javier M. Duarte, David Burnette, Lauri Laatu, Stylianos Tzelepis, Konstantinos Axiotis, Quentin Berthet, Haoyan Wang, Paul White, Suleyman Demirsoy, Marco Colombo, Thea Aarrestad, Sioni Summers, Maurizio Pierini, Giuseppe Di Guglielmo, Jennifer Ngadiuba, Javier Campos, Benjamin Hawks, Abhijith Gandrakota, Farah Fahim, Nhan Tran, George A. Constantinides, Zhiqiang Que, Wayne Luk, Alexander D. Tapper, Duc Hoang, Noah Paladino, Philip C. Harris, Bo-Cheng Lai, Manuel Blanco Valentin, Ryan F. Forelli, Seda Ogrenci, Lino Gerlach, Rian Flynn, Mia Liu, Daniel Diaz, Elham E Khoda, Melissa Quinnan, Russell Solares, Santosh Parajuli, Mark S. Neubauer, Christian Herwig, Ho Fung Tsoi, Dylan S. Rankin, Shih-Chieh Hsu, Scott Hauck
2024	—	`conf`	Accelerating Large-Scale Graph Processing with FPGAs: Lesson Learned and Future Directions. PARMA-DITAM Marco Procaccini, Amin Sahebi, Marco Barbone, Wayne Luk, Georgi Gaydadjiev, Roberto Giorgi
2024	—	`conf`	Accelerating MRI Uncertainty Estimation with Mask-Based Bayesian Neural Network. ASAP Zehuan Zhang, Matej Genci, Hongxiang Fan, Andreas Wetscherek, Wayne Luk
2024	J	`jnl`	Accelerating MRI Uncertainty Estimation with Mask-based Bayesian Neural Network. CoRR Zehuan Zhang, Matej Genci, Hongxiang Fan, Andreas Wetscherek, Wayne Luk
2024	J	`jnl`	Acceleration of Multi-Body Molecular Dynamics With Customized Parallel Dataflow. IEEE Trans. Parallel Distributed Syst. Quan Deng, Qiang Liu, Ming Yuan, Xiaohui Duan, Lin Gan, Jinzhe Yang, Wenlai Zhao, Zhenxiang Zhang, Guiming Wu, Wayne Luk, Haohuan Fu, Guangwen Yang
2024	—	`conf`	Auto-Generating Diverse Heterogeneous Designs. IPDPS (Workshops) Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk
2024	A*	`conf`	Circular Reconfigurable Parallel Processor for Edge Computing : Industrial Product ✶. ISCA Yuan Li, Jianbin Zhu, Yao Fu, Yu Lei, Toshio Nagata, Ryan Braidwood, Haohuan Fu, Juepeng Zheng, Wayne Luk, Hongxiang Fan
2024	J	`jnl`	Design of Fully Spectral CNNs for Efficient FPGA-Based Acceleration. IEEE Trans. Neural Networks Learn. Syst. Shuanglong Liu, Hongxiang Fan, Wayne Luk
2024	J	`jnl`	Efficient Adaptable Streaming Aggregation Engine. CoRR Philippos Papaphilippou, Wayne Luk
2024	J	`jnl`	Enhancing Dropout-based Bayesian Neural Networks with Multi-Exit on FPGA. CoRR Hao Mark Chen, Liam Castelli, Martin Ferianc, Hongyu Zhou, Shuanglong Liu, Wayne Luk, Hongxiang Fan
2024	B	`conf`	Exploring FPGA designs for MX and beyond. FPL Ebby Samson, Naveen Mellempudi, Wayne Luk, George A. Constantinides
2024	J	`jnl`	Exploring FPGA designs for MX and beyond. CoRR Ebby Samson, Naveen Mellempudi, Wayne Luk, George A. Constantinides
2024	J	`jnl`	FPGA-Accelerated Sim-to-Real Control Policy Learning for Robotic Arms. IEEE Trans. Circuits Syst. II Express Briefs Ce Guo, Wayne Luk
2024	—	`conf`	Field-Programmable Dynamic Deep Learning. ICFPT Stewart Denholm, Wayne Luk
2024	A*	`conf`	Hardware-Aware Neural Dropout Search for Reliable Uncertainty Prediction on FPGA. DAC Zehuan Zhang, Hongxiang Fan, Hao Mark Chen, Lukasz Dudziak, Wayne Luk
2024	J	`jnl`	Hardware-Aware Neural Dropout Search for Reliable Uncertainty Prediction on FPGA. CoRR Zehuan Zhang, Hongxiang Fan, Hao Mark Chen, Lukasz Dudziak, Wayne Luk
2024	J	`jnl`	Hardware-Aware Parallel Prompt Decoding for Memory-Efficient Acceleration of LLM Inference. CoRR Hao Mark Chen, Wayne Luk, Ka Fai Cedric Yiu, Rui Li, Konstantin Mishchenko, Stylianos I. Venieris, Hongxiang Fan
2024	J	`jnl`	High-Frequency Financial Market Simulation and Flash Crash Scenarios Analysis: An Agent-Based Modelling Approach. J. Artif. Soc. Soc. Simul. Kang Gao, Perukrishnen Vytelingum, Stephen Weston, Wayne Luk, Ce Guo
2024	J	`jnl`	LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physics. ACM Trans. Embed. Comput. Syst. Zhiqiang Que, Hongxiang Fan, Marcus Loo, He Li, Michaela Blott, Maurizio Pierini, Alexander D. Tapper, Wayne Luk
2024	J	`jnl`	Low Latency Variational Autoencoder on FPGAs. IEEE J. Emerg. Sel. Topics Circuits Syst. Zhiqiang Que, Minghao Zhang, Hongxiang Fan, He Li, Ce Guo, Wayne Luk
2024	—	`conf`	Optimizing DNN Accelerator Compression Using Tolerable Accuracy Loss. ICFPT Zhiqiang Que, Anyan Zhao, José Gabriel F. Coutinho, Ce Guo, Wayne Luk
2024	J	`jnl`	Optimizing VarLiNGAM for Scalable and Efficient Time Series Causal Discovery. CoRR Ziyang Jiao, Ce Guo, Wayne Luk
2024	Misc	`conf`	PCQ: Parallel Compact Quantum Circuit Simulation. FCCM Shuang Liang, Yuncheng Lu, Ce Guo, Wayne Luk, Paul H. J. Kelly
2024	—	`conf`	RAW 2024 Invited Talk-1: Auto-Generating Diverse Heterogeneous Designs. IPDPS (Workshops) Wayne Luk
2024	—	`conf`	Resource-Constraint Bayesian Optimization for Soft Processors on FPGAs. HEART Ce Guo, Haoran Wu, Wayne Luk
2024	J	`jnl`	Robust Time Series Causal Discovery for Agent-Based Model Validation. CoRR Gene Yu, Ce Guo, Wayne Luk
2024	J	`jnl`	Sets are all you need: Ultrafast jet classification on FPGAs for HL-LHC. CoRR Patrick Odagiu, Zhiqiang Que, Javier M. Duarte, Johannes Haller, Gregor Kasieczka, Artur Lobanov, Vladimir Loncar, Wayne Luk, Jennifer Ngadiuba, Maurizio Pierini, Philipp Rincke, Arpita Seksaria, Sioni Summers, Andre Sznajder, Alexander D. Tapper, Thea Klæboe Årrestad
2024	—	`conf`	Trustworthy Codesign by Verifiable Transformations. ITC-Asia Qianzhou Wang, Zhiqiang Que, Wayne Luk
2024	J	`jnl`	Ultrafast jet classification at the HL-LHC. Mach. Learn. Sci. Technol. Patrick Odagiu, Zhiqiang Que, Javier M. Duarte, Johannes Haller, Gregor Kasieczka, Artur Lobanov, Vladimir Loncar, Wayne Luk, Jennifer Ngadiuba, Maurizio Pierini, Philipp Rincke, Arpita Seksaria, Sioni Summers, Andre Sznajder, Alexander D. Tapper, Thea Klæboe Årrestad
2023	J	`jnl`	Advancements in spiking neural network communication and synchronization techniques for event-driven neuromorphic systems. Array Mahyar Shahsavari, David B. Thomas, Marcel van Gerven, Andrew D. Brown, Wayne Luk
2023	—	`conf`	Co-Design of Algorithm and FPGA Accelerator for Conditional Independence Test. ASAP Ce Guo, Wayne Luk, Alexander Warren, Joshua M. Levine, Peter Brookes
2023	—	`conf`	Customisable Processing of Neural Networks for FPGAs. HEART Stewart Denholm, Wayne Luk
2023	—	`conf`	Deeper Hedging: A New Agent-based Model for Effective Deep Hedging. ICAIF Kang Gao, Stephen Weston, Perukrishnen Vytelingum, Namid R. Stillman, Wayne Luk, Ce Guo
2023	J	`jnl`	Distributed large-scale graph processing on FPGAs. J. Big Data Amin Sahebi, Marco Barbone, Marco Procaccini, Wayne Luk, Georgi Gaydadjiev, Roberto Giorgi
2023	—	`conf`	Efficiently Removing Sparsity for High-Throughput Stream Processing. ICFPT Philippos Papaphilippou, Zhiqiang Que, Wayne Luk
2023	J	`jnl`	Event-based high throughput computing: A series of case studies on a massively parallel softcore machine. IET Comput. Digit. Tech. Mark Vousden, Jordan Morris, Graeme McLachlan Bragg, Jonathan Beaumont, Ashur Rafiev, Wayne Luk, David B. Thomas, Andrew D. Brown
2023	J	`jnl`	Experimental Survey of FPGA-Based Monolithic Switches and a Novel Queue Balancer. IEEE Trans. Parallel Distributed Syst. Philippos Papaphilippou, Kentaro Sano, Boma Anantasatya Adhi, Wayne Luk
2023	—	`conf`	Exploring Machine Learning Adoption in Customisable Processor Design. ASICON José Gabriel F. Coutinho, Ce Guo, Tim Todman, Wayne Luk
2023	—	`conf`	Extensible Embedded Hardware Description Languages with Compilation, Simulation and Verification. HEART Omar Tahir, Wayne Luk, Nicolas Wu
2023	B	`conf`	FPGA-Accelerated Causal Discovery with Conditional Independence Test Prioritization. FPL Ce Guo, Diego Cupello, Wayne Luk, Joshua M. Levine, Alexander Warren, Peter Brookes
2023	A*	`conf`	Heterogeneous Reconfigurable Accelerators: Trends and Perspectives. DAC Wayne Luk
2023	J	`jnl`	High-Performance Acceleration of 2-D and 3-D CNNs on FPGAs Using Static Block Floating Point. IEEE Trans. Neural Networks Learn. Syst. Hongxiang Fan, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk
2023	B	`conf`	MetaML: Automating Customizable Cross-Stage Design-Flow for Deep Learning Acceleration. FPL Zhiqiang Que, Shuo Liu, Markus Rognlien, Ce Guo, José Gabriel F. Coutinho, Wayne Luk
2023	J	`jnl`	MetaML: Automating Customizable Cross-Stage Design-Flow for Deep Learning Acceleration. CoRR Zhiqiang Que, Shuo Liu, Markus Rognlien, Ce Guo, José Gabriel F. Coutinho, Wayne Luk
2023	J	`jnl`	Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks. ACM Trans. Reconfigurable Technol. Syst. Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, He Li, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk
2023	J	`jnl`	Special Issue: "AI Acceleration on FPGAs". ACM Trans. Embed. Comput. Syst. Yun Liang, Wei Zhang, Stephen Neuendorffer, Wayne Luk
2023	J	`jnl`	Using Agent-Based Modelling to Evaluate the Impact of Algorithmic Curation on Social Media. ACM J. Data Inf. Qual. Anna Gausen, Wayne Luk, Ce Guo
2023	A*	`conf`	When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA. DAC Hongxiang Fan, Mark Chen, Liam Castelli, Zhiqiang Que, He Li, Kenneth Long, Wayne Luk
2023	J	`jnl`	When Monte-Carlo Dropout Meets Multi-Exit: Optimizing Bayesian Neural Networks on FPGA. CoRR Hongxiang Fan, Hao Chen, Liam Castelli, Zhiqiang Que, He Li, Kenneth Long, Wayne Luk
2022	B	`conf`	A Unified Approach for Managing Heterogeneous Processing Elements on FPGAs. FPL Stewart Denholm, Wayne Luk
2022	J	`jnl`	A fully-customized dataflow engine for 3D earthquake simulation with a complex topography. Sci. China Inf. Sci. Bingwei Chen, Haohuan Fu, Wayne Luk, Guangwen Yang
2022	J	`jnl`	Accelerating Bayesian Neural Networks via Algorithmic and Hardware Optimizations. IEEE Trans. Parallel Distributed Syst. Hongxiang Fan, Martin Ferianc, Zhiqiang Que, Xinyu Niu, Miguel R. D. Rodrigues, Wayne Luk
2022	A	`conf`	Accelerating Constraint-Based Causal Discovery by Shifting Speed Bottleneck. FPGA Ce Guo, Wayne Luk
2022	—	`conf`	Accelerating Transformer Neural Networks on FPGAs for High Energy Physics Experiments. FPT Filip Wojcicki, Zhiqiang Que, Alexander D. Tapper, Wayne Luk
2022	A*	`conf`	Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design. MICRO Hongxiang Fan, Thomas Chau, Stylianos I. Venieris, Royson Lee, Alexandros Kouris, Wayne Luk, Nicholas D. Lane, Mohamed S. Abdelfattah
2022	J	`jnl`	Adaptable Butterfly Accelerator for Attention-based NNs via Hardware and Algorithm Co-design. CoRR Hongxiang Fan, Thomas Chun-Pong Chau, Stylianos I. Venieris, Royson Lee, Alexandros Kouris, Wayne Luk, Nicholas D. Lane, Mohamed S. Abdelfattah
2022	—	`conf`	Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator. ASP-DAC Hongxiang Fan, Martin Ferianc, Zhiqiang Que, He Li, Shuanglong Liu, Xinyu Niu, Wayne Luk
2022	J	`jnl`	Custom Instructions for Networked Processor Templates. IEEE Trans. Circuits Syst. II Express Briefs Tim Todman, Wayne Luk
2022	C	`conf`	Customizable FPGA-based Accelerator for Binarized Graph Neural Networks. ISCAS Ziwei Wang, Zhiqiang Que, Wayne Luk, Hongxiang Fan
2022	A*	`conf`	Enabling fast uncertainty estimation: accelerating bayesian transformers via algorithmic and hardware optimizations. DAC Hongxiang Fan, Martin Ferianc, Wayne Luk
2022	J	`jnl`	FLiMS: A Fast Lightweight 2-Way Merger for Sorting. IEEE Trans. Computers Philippos Papaphilippou, Wayne Luk, Chris Brooks
2022	J	`jnl`	FPGA-Based Acceleration for Bayesian Convolutional Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hongxiang Fan, Martin Ferianc, Zhiqiang Que, Shuanglong Liu, Xinyu Niu, Miguel R. D. Rodrigues, Wayne Luk
2022	—	`ch.`	FPGA-Based Backpropagation Engine for Feed-Forward Neural Networks. Mach. Learn. under Resour. Constraints Vol. 1 (1) Wayne Luk, Ce Guo
2022	—	`conf`	Hardware-Aware Optimizations for Deep Learning Inference on Edge Devices. ARC Markus Rognlien, Zhiqiang Que, José Gabriel F. Coutinho, Wayne Luk
2022	J	`jnl`	Hipernetch: High-Performance FPGA Network Switch. ACM Trans. Reconfigurable Technol. Syst. Philippos Papaphilippou, Jiuxi Meng, Nadeen Gebara, Wayne Luk
2022	J	`jnl`	LL-GNN: Low Latency Graph Neural Networks on FPGAs for Particle Detectors. CoRR Zhiqiang Que, Marcus Loo, Hongxiang Fan, Michaela Blott, Maurizio Pierini, Alexander D. Tapper, Wayne Luk
2022	—	`conf`	Light-Weight Permutation Generator for Efficient Convolutional Neural Network Data Augmentation. ARC Bowen P. Y. Kwan, Ce Guo, Wayne Luk, Peiyong Jiang
2022	C	`conf`	Maximising Parallel Memory Access for Low Latency FPGA Designs. ISCAS Stewart Denholm, Wayne Luk
2022	—	`conf`	Meta-Programming Design-Flow Patterns for Automating Reusable Optimisations. HEART Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk
2022	Misc	`conf`	Mixed-Resource Parallel Processing on FPGAs. FCCM Stewart Denholm, Wayne Luk
2022	—	`conf`	Non-deterministic event brokered computing. HEART Andrew Brown, Tim Todman, Wayne Luk, David B. Thomas, Mark Vousden, Graeme M. Bragg, Jonny Beaumont, Simon W. Moore, Alex Yakovlev, Ashur Rafiev
2022	B	`conf`	Optimizing Graph Neural Networks for Jet Tagging in Particle Physics on FPGAs. FPL Zhiqiang Que, Marcus Loo, Hongxiang Fan, Maurizio Pierini, Alexander D. Tapper, Wayne Luk
2022	A*	`conf`	Optimizing quantum circuit placement via machine learning. DAC Hongxiang Fan, Ce Guo, Wayne Luk
2022	B	`conf`	POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations. FPL Ruizhe Zhao, Jianyi Cheng, Wayne Luk, George A. Constantinides
2022	—	`conf`	Reconfigurable Acceleration of Graph Neural Networks for Jet Identification in Particle Physics. AICAS Zhiqiang Que, Marcus Loo, Wayne Luk
2022	J	`jnl`	Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Andrew Boutros, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Wayne Luk
2022	J	`jnl`	Toward Full-Stack Acceleration of Deep Convolutional Neural Networks on FPGAs. IEEE Trans. Neural Networks Learn. Syst. Shuanglong Liu, Hongxiang Fan, Martin Ferianc, Xinyu Niu, Huifeng Shi, Wayne Luk
2022	—	`conf`	Verifying Hardware Optimizations for Efficient Acceleration. HEART Qianzhou Wang, Yat Wong, Zhiqiang Que, Wayne Luk
2021	A	`conf`	Accelerating Fully Spectral CNNs with Adaptive Activation Functions on FPGA. DATE Shuanglong Liu, Hongxiang Fan, Wayne Luk
2021	—	`conf`	Accelerating Recurrent Neural Networks for Gravitational Wave Experiments. ASAP Zhiqiang Que, Erwei Wang, Umar Marikar, Eric A. Moreno, Jennifer Ngadiuba, Hamza Javed, Bartlomiej Borzyszkowski, Thea Aarrestad, Vladimir Loncar, Sioni Summers, Maurizio Pierini, Peter Y. K. Cheung, Wayne Luk
2021	J	`jnl`	Accelerating Recurrent Neural Networks for Gravitational Wave Experiments. CoRR Zhiqiang Que, Erwei Wang, Umar Marikar, Eric A. Moreno, Jennifer Ngadiuba, Hamza Javed, Bartlomiej Borzyszkowski, Thea Aarrestad, Vladimir Loncar, Sioni Summers, Maurizio Pierini, Peter Y. K. Cheung, Wayne Luk
2021	J	`jnl`	Algorithm and Hardware Co-design for Reconfigurable CNN Accelerator. CoRR Hongxiang Fan, Martin Ferianc, Zhiqiang Que, He Li, Shuanglong Liu, Xinyu Niu, Wayne Luk
2021	J	`jnl`	Analytical Performance Estimation for Large-Scale Reconfigurable Dataflow Platforms. ACM Trans. Reconfigurable Technol. Syst. Ryota Yasudo, José Gabriel de Figueiredo Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker, Ce Guo
2021	—	`conf`	Can We Stop Fake News? Using Agent-Based Modelling to Evaluate Countermeasures for Misinformation on Social Media. ICWSM Workshops Anna Gausen, Wayne Luk, Ce Guo
2021	—	`conf`	Custom enhancements to networked processor templates. ISVLSI Tim Todman, Wayne Luk
2021	B	`conf`	Demonstrating custom SIMD instruction development for a RISC-V softcore. FPL Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk
2021	C	`conf`	Efficient Online 4D Magnetic Resonance Imaging. SBAC-PAD Marco Barbone, Andreas Wetscherek, Thomas Yung, Uwe Oelfke, Wayne Luk, Georgi Gaydadjiev
2021	—	`conf`	Efficient Queue-Balancing Switch for FPGAs. FPT Philippos Papaphilippou, Kentaro Sano, Boma A. Adhi, Wayne Luk
2021	C	`conf`	Efficient Table-Based Polynomial on FPGA. ICCD Marco Barbone, Bas W. Kwaadgras, Uwe Oelfke, Wayne Luk, Georgi Gaydadjiev
2021	J	`jnl`	Enhancing High-Level Synthesis Using a Meta-Programming Approach. IEEE Trans. Computers Jessica Vandebon, José Gabriel de Figueiredo Coutinho, Wayne Luk, Eriko Nurvitadhi
2021	J	`jnl`	Extending the RISC-V ISA for exploring advanced reconfigurable SIMD instructions. CoRR Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk
2021	J	`jnl`	FLiMS: a Fast Lightweight 2-way Merge Sorter. CoRR Philippos Papaphilippou, Wayne Luk, Chris Brooks
2021	—	`conf`	FPGA-accelerated Agent-Based Simulation for COVID-19. AICAS Lei Fu, Ce Guo, Wayne Luk
2021	Misc	`conf`	Flexible Instrumentation for Live On-Chip Debug of Machine Learning Training on FPGAs. FCCM Daniel Holanda Noronha, Zhiqiang Que, Wayne Luk, Steven J. E. Wilton
2021	A*	`conf`	High-Performance FPGA-based Accelerator for Bayesian Neural Networks. DAC Hongxiang Fan, Martin Ferianc, Miguel Rodrigues, Hongyu Zhou, Xinyu Niu, Wayne Luk
2021	J	`jnl`	High-Performance FPGA-based Accelerator for Bayesian Neural Networks. CoRR Hongxiang Fan, Martin Ferianc, Miguel Rodrigues, Hongyu Zhou, Xinyu Niu, Wayne Luk
2021	J	`jnl`	High-Performance FPGA-based Accelerator for Bayesian Recurrent Neural Networks. CoRR Martin Ferianc, Zhiqiang Que, Hongxiang Fan, Wayne Luk, Miguel Rodrigues
2021	J	`jnl`	In-circuit tuning of deep learning designs. J. Syst. Archit. Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Xinyu Niu, Steven J. E. Wilton, Wayne Luk
2021	—	`conf`	Neuromorphic Design Using Reward-based STDP Learning on Event-Based Reconfigurable Cluster Architecture. ICONS Mahyar Shahsavari, David B. Thomas, Andrew D. Brown, Wayne Luk
2021	J	`jnl`	On Predictable Reconfigurable System Design. ACM Trans. Archit. Code Optim. Nils Voss, Bastiaan Kwaadgras, Oskar Mencer, Wayne Luk, Georgi Gaydadjiev
2021	—	`conf`	Optimizing Bayesian Recurrent Neural Networks on an FPGA-based Accelerator. FPT Martin Ferianc, Zhiqiang Que, Hongxiang Fan, Wayne Luk, Miguel Rodrigues
2021	J	`jnl`	Performance-aware programming for intraoperative intensity-based image registration on graphics processing units. Int. J. Comput. Assist. Radiol. Surg. Martin C. W. Leong, Kit-Hang Lee, Bowen P. Y. Kwan, Yui-Lun Ng, Zhiyu Liu, Nassir Navab, Wayne Luk, Ka-Wai Kwok
2021	A	`conf`	Reconfigurable Acceleration of Short Read Mapping with Biological Consideration. FPGA Ho-Cheung Ng, Izaak Coleman, Shuanglong Liu, Wayne Luk
2021	J	`jnl`	Scheduling Hardware-Accelerated Cloud Functions. J. Signal Process. Syst. Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk
2021	B	`conf`	Simodense: a RISC-V softcore optimised for exploring custom SIMD instructions. FPL Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk
2021	Misc	`conf`	Systematically migrating an operational microphysics parameterisation to FPGA technology. FCCM James Stanley Targett, Wayne Luk, Michael Lange, Olivier Marsden
2020	—	`conf`	A Reconfigurable Multithreaded Accelerator for Recurrent Neural Networks. FPT Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk
2020	C	`conf`	Accelerating Simulation for Agent-based Epidemic Models using FPGAs. AICCSA Ce Guo, Wayne Luk, Stephen Weston
2020	—	`conf`	Acceleration of Short Read Alignment with Runtime Reconfiguration. FPT Ho-Cheung Ng, Shuanglong Liu, Izaak Coleman, Ringo S. W. Chu, Man-Chung Yue, Wayne Luk
2020	B	`conf`	An Adaptable High-Throughput FPGA Merge Sorter for Accelerating Database Analytics. FPL Philippos Papaphilippou, Chris Brooks, Wayne Luk
2020	J	`jnl`	An Analysis of Alternating Direction Method of Multipliers for Feed-forward Neural Networks. CoRR Seyedeh Niusha Alavi Foumani, Ce Guo, Wayne Luk
2020	J	`jnl`	An FPGA Accelerated Method for Training Feed-forward Neural Networks Using Alternating Direction Method of Multipliers and LSMR. CoRR Seyedeh Niusha Alavi Foumani, Ce Guo, Wayne Luk
2020	Misc	`conf`	Artisan: a Meta-Programming Approach For Codifying Optimisation Strategies. FCCM Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Tim Todman
2020	—	`conf`	Exploring performance enhancement of event-driven processor networks. FPT Tim Todman, David B. Thomas, Wayne Luk
2020	—	`conf`	Fast and Accurate Training of Ensemble Models with FPGA-based Switch. ASAP Jiuxi Meng, Ce Guo, Nadeen Gebara, Wayne Luk
2020	J	`jnl`	GeDi: applying suffix arrays to increase the repertoire of detectable SNVs in tumour genomes. BMC Bioinform. Izaak Coleman, Giacomo Corleone, James Arram, Ho-Cheung Ng, Luca Magnani, Wayne Luk
2020	J	`jnl`	High performance reconfigurable computing for numerical simulation and deep learning. CCF Trans. High Perform. Comput. Lin Gan, Ming Yuan, Jinzhe Yang, Wenlai Zhao, Wayne Luk, Guangwen Yang
2020	A	`conf`	High-Performance FPGA Network Switch Architecture. FPGA Philippos Papaphilippou, Jiuxi Meng, Wayne Luk
2020	Misc	`conf`	High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression. FCCM Hiroki Nakahara, Zhiqiang Que, Wayne Luk
2020	—	`conf`	Improving Performance Estimation for FPGA-Based Accelerators for Convolutional Neural Networks. ARC Martin Ferianc, Hongxiang Fan, Ringo S. W. Chu, Jakub Stano, Wayne Luk
2020	J	`jnl`	Learning Absolute Sound Source Localisation With Limited Supervisions. CoRR Yang Chu, Wayne Luk, Dan Goodman
2020	J	`jnl`	Mapping Large LSTMs to FPGAs with Weight Reuse. J. Signal Process. Syst. Zhiqiang Que, Yongxin Zhu, Hongxiang Fan, Jiuxi Meng, Xinyu Niu, Wayne Luk
2020	—	`conf`	On the challenges in programming mixed-precision deep neural networks. MAPL@PLDI Ruizhe Zhao, Wayne Luk, Chao Xiong, Xinyu Niu, Kuen Hung Tsoi
2020	C	`conf`	Optimizing FPGA-Based CNN Accelerator Using Differentiable Neural Architecture Search. ICCD Hongxiang Fan, Martin Ferianc, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk
2020	—	`conf`	Optimizing Fully Spectral Convolutional Neural Networks on FPGA. FPT Shuanglong Liu, Wayne Luk
2020	Misc	`conf`	Optimizing Reconfigurable Recurrent Neural Networks. FCCM Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Xinyu Niu, Wayne Luk
2020	A	`conf`	Performance Portable FPGA Design. FPGA Nils Voss, Tobias Becker, Simon Tilbury, Georgi Gaydadjiev, Oskar Mencer, Anna Maria Nestorov, Enrico Reggiani, Wayne Luk
2020	—	`conf`	Quantisation-aware Dimensionality Reduction. FPT Ce Guo, Wayne Luk
2020	A	`conf`	R2CNN: Recurrent Residual Convolutional Neural Network on FPGA. FPGA Hiroki Nakahara, Zhiqiang Que, Akira Jinguji, Wayne Luk
2020	A*	`conf`	Reducing Underflow in Mixed Precision Training by Gradient Scaling. IJCAI Ruizhe Zhao, Brian Vogel, Tanvir Ahmed, Wayne Luk
2020	—	`conf`	SLATE: Managing Heterogeneous Cloud Functions. ASAP Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Mishali Naik
2020	—	`conf`	Towards Overlay-based Rapid In-Circuit Tuning of Deep Learning Designs. FPT Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Xinyu Niu, Steven J. E. Wilton, Wayne Luk
2020	J	`jnl`	Towards Real Time Radiotherapy Simulation. J. Signal Process. Syst. Nils Voss, Peter Ziegenhein, Lukas Vermond, Joost Hoozemans, Oskar Mencer, Uwe Oelfke, Wayne Luk, Georgi Gaydadjiev
2019	J	`jnl`	A Real-Time Tree Crown Detection Approach for Large-Scale Remote Sensing Images on FPGAs. Remote. Sens. Weijia Li, Conghui He, Haohuan Fu, Juepeng Zheng, Runmin Dong, Maocai Xia, Le Yu, Wayne Luk
2019	B	`conf`	Accelerating the Merge Phase of Sort-Merge Join. FPL Philippos Papaphilippou, Holger Pirk, Wayne Luk
2019	—	`conf`	An Overlay for Rapid FPGA Debug of Machine Learning Applications. FPT Daniel Holanda Noronha, Ruizhe Zhao, Zhiqiang Que, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton
2019	C	`conf`	Convolution Based Spectral Partitioning Architecture for Hyperspectral Image Classification. IGARSS Ringo S. W. Chu, Ho-Cheung Ng, Xiwei Wang, Wayne Luk
2019	J	`jnl`	Convolution Based Spectral Partitioning Architecture for Hyperspectral Image Classification. CoRR Ringo S. W. Chu, Ho-Cheung Ng, Xiwei Wang, Wayne Luk
2019	—	`conf`	Customisable Control Policy Learning for Robotics. ASAP Ce Guo, Wayne Luk, Stanley Qing Shui Loh, Alexander Warren, Joshua M. Levine
2019	J	`jnl`	Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. CoRR Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides
2019	J	`jnl`	Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going. ACM Comput. Surv. Erwei Wang, James J. Davis, Ruizhe Zhao, Ho-Cheung Ng, Xinyu Niu, Wayne Luk, Peter Y. K. Cheung, George A. Constantinides
2019	—	`conf`	Efficient Structured Pruning and Architecture Searching for Group Convolution. ICCV Workshops Ruizhe Zhao, Wayne Luk
2019	—	`conf`	Efficient Weight Reuse for Large LSTMs. ASAP Zhiqiang Que, Thomas Nugent, Shuanglong Liu, Li Tian, Xinyu Niu, Yongxin Zhu, Wayne Luk
2019	—	`conf`	Enhanced Heterogeneous Cloud: Transparent Acceleration and Elasticity. FPT Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Mishali Naik
2019	—	`conf`	F-E3D: FPGA-based Acceleration of an Efficient 3D Convolutional Neural Network for Human Action Recognition. ASAP Hongxiang Fan, Cheng Luo, Chenglong Zeng, Martin Ferianc, Zhiqiang Que, Shuanglong Liu, Xinyu Niu, Wayne Luk
2019	—	`conf`	Investigating the Feasibility of FPGA-based Network Switches. ASAP Jiuxi Meng, Nadeen Gebara, Ho-Cheung Ng, Paolo Costa, Wayne Luk
2019	—	`conf`	Low Area Overhead Custom Buffering for FFT. ReConFig Nils Voss, Stephen Girdlestone, Tobias Becker, Oskar Mencer, Wayne Luk, Georgi Gaydadjiev
2019	Misc	`conf`	Memory Mapping for Multi-die FPGAs. FCCM Nils Voss, Pablo Quintana, Oskar Mencer, Wayne Luk, Georgi Gaydadjiev
2019	—	`conf`	Non-linear function evaluation reusing matrix-vector multipliers. ASICON Ce Guo, Wayne Luk, Wenguang Xu
2019	A	`conf`	On-chip FPGA Debug Instrumentation for Machine Learning Applications. FPGA Daniel Holanda Noronha, Ruizhe Zhao, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton
2019	—	`conf`	Optimizing CNN-Based Hyperspectral Image Classification on FPGAs. ARC Shuanglong Liu, Ringo S. W. Chu, Xiwei Wang, Wayne Luk
2019	J	`jnl`	Optimizing CNN-based Hyperspectral ImageClassification on FPGAs. CoRR Shuanglong Liu, Ringo S. W. Chu, Xiwei Wang, Wayne Luk
2019	J	`jnl`	Optimizing Finite Volume Method Solvers on Nvidia GPUs. IEEE Trans. Parallel Distributed Syst. Jingheng Xu, Guangwen Yang, Haohuan Fu, Wayne Luk, Lin Gan, Wen Shi, Wei Xue, Chao Yang, Yong Jiang, Conghui He
2019	J	`jnl`	Pangloss: a novel Markov chain prefetcher. CoRR Philippos Papaphilippou, Paul H. J. Kelly, Wayne Luk
2019	J	`jnl`	Performance Tuning and Analysis for Stencil-Based Applications on POWER8 Processor. ACM Trans. Archit. Code Optim. Jingheng Xu, Haohuan Fu, Wen Shi, Lin Gan, Yuxuan Li, Wayne Luk, Guangwen Yang
2019	—	`conf`	Real-Time Anomaly Detection for Flight Testing Using AutoEncoder and LSTM. FPT Zhiqiang Que, Yanyang Liu, Ce Guo, Xinyu Niu, Yongxin Zhu, Wayne Luk
2019	—	`conf`	Static Block Floating-Point Quantization for Convolutional Neural Networks on FPGA. FPT Hongxiang Fan, Gang Wang, Martin Ferianc, Xinyu Niu, Wayne Luk
2019	Misc	`conf`	Towards Efficient Deep Neural Network Training by FPGA-Based Batch-Level Parallelism. FCCM Cheng Luo, Man-Kit Sit, Hongxiang Fan, Shuanglong Liu, Wayne Luk, Ce Guo
2019	A	`conf`	Towards In-Circuit Tuning of Deep Learning Designs. ICCAD Zhiqiang Que, Daniel Holanda Noronha, Ruizhe Zhao, Steven J. E. Wilton, Wayne Luk
2019	—	`conf`	Towards Real Time Radiotherapy Simulation. ASAP Nils Voss, Peter Ziegenhein, Lukas Vermond, Joost Hoozemans, Oskar Mencer, Uwe Oelfke, Wayne Luk, Georgi Gaydadjiev
2019	B	`conf`	Towards an Efficient Accelerator for DNN-Based Remote Sensing Image Segmentation on FPGAs. FPL Shuanglong Liu, Wayne Luk
2019	—	`conf`	Transparent Heterogeneous Cloud Acceleration. ASAP Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Thomas Chau
2018	A	`conf`	A Low-Power Deconvolutional Accelerator for Convolutional Neural Network Based Segmentation on FPGA: Abstract Only. FPGA Shuanglong Liu, Xinyu Niu, Wayne Luk
2018	—	`conf`	A Real-Time Object Detection Accelerator with Compressed SSDLite on FPGA. FPT Hongxiang Fan, Shuanglong Liu, Martin Ferianc, Ho-Cheung Ng, Zhiqiang Que, Shen Liu, Xinyu Niu, Wayne Luk
2018	A	`conf`	ADAM: Automated Design Analysis and Merging for Speeding up FPGA Development. FPGA Ho-Cheung Ng, Shuanglong Liu, Wayne Luk
2018	B	`conf`	Accelerating Database Systems Using FPGAs: A Survey. FPL Philippos Papaphilippou, Wayne Luk
2018	A	`conf`	Automatic Optimising CNN with Depthwise Separable Convolution on FPGA: (Abstact Only). FPGA Ruizhe Zhao, Xinyu Niu, Wayne Luk
2018	—	`conf`	CJS: Custom Jacobi Solver. HEART Andreea-Ingrid Cross, Liucheng Guo, Wayne Luk, Mark Salmon
2018	B	`conf`	CRRS: Custom Regression and Regularisation Solver for Large-Scale Linear Systems. FPL Andreea-Ingrid Cross, Liucheng Guo, Wayne Luk, Mark Salmon
2018	—	`conf`	Correlation Coefficient Based Cluster Data Preprocessing and LSTM Prediction Model for Time Series Data in Large Aircraft Test Flights. SmartCom Hanlin Zhu, Yongxin Zhu, Di Wu, Hui Wang, Li Tian, Wei Mao, Can Feng, Xiaowen Zha, Guobao Deng, Jiayi Chen, Tao Liu, Xinyu Niu, Kuen Hung Tsoi, Wayne Luk
2018	—	`conf`	Custom machine learning architectures: towards realtime anomaly detection for flight testing. IPDPS Workshops Di Wu, Zhanrui Sun, Yongxin Zhu, Li Tian, Hanlin Zhu, Peng Xiong, Zihao Cao, Menglin Wang, Yu Zheng, Chao Xiong, Hao Jiang, Kuen Hung Tsoi, Xinyu Niu, Wei Mao, Can Feng, Xiaowen Zha, Guobao Deng, Wayne Luk
2018	—	`conf`	FLiMS: Fast Lightweight Merge Sorter. FPT Philippos Papaphilippou, Chris Brooks, Wayne Luk
2018	J	`jnl`	FP-BNN: Binarized neural network on FPGA. Neurocomputing Shuang Liang, Shouyi Yin, Leibo Liu, Wayne Luk, Shaojun Wei
2018	—	`conf`	From Tensor Algebra to Hardware Accelerators: Generating Streaming Architectures for Solving Partial Differential Equations. ASAP Francis P. Russell, James Stanley Targett, Wayne Luk
2018	—	`conf`	Hardware Compilation of Deep Neural Networks: An Overview. ASAP Ruizhe Zhao, Shuanglong Liu, Ho-Cheung Ng, Erwei Wang, James J. Davis, Xinyu Niu, Xiwei Wang, Huifeng Shi, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2018	J	`jnl`	Learning Grouped Convolution for Efficient Domain Adaptation. CoRR Ruizhe Zhao, Wayne Luk
2018	—	`conf`	Lossy Multiport Memory. FPT Bowen P. Y. Kwan, Gary C. T. Chow, Tim Todman, Wayne Luk, Wenguang Xu
2018	—	`conf`	Memory-Efficient Architecture for Accelerating Generative Networks on FPGA. FPT Shuanglong Liu, Chenglong Zeng, Hongxiang Fan, Ho-Cheung Ng, Jiuxi Meng, Zhiqiang Que, Xinyu Niu, Wayne Luk
2018	J	`jnl`	Optimizing CNN-based Segmentation with Deeply Customized Convolutional and Deconvolutional Architectures on FPGA. ACM Trans. Reconfigurable Technol. Syst. Shuanglong Liu, Hongxiang Fan, Xinyu Niu, Ho-Cheung Ng, Yang Chu, Wayne Luk
2018	—	`conf`	Performance Estimation for Exascale Reconfigurable Dataflow Platforms. FPT Ryota Yasudo, José Gabriel F. Coutinho, Ana Lucia Varbanescu, Wayne Luk, Hideharu Amano, Tobias Becker
2018	Misc	`conf`	Performance Prediction for Large-Scale Heterogeneous Platforms. FCCM Ryota Yasudo, Ana Lucia Varbanescu, José Gabriel F. Coutinho, Wayne Luk, Hideharu Amano
2018	—	`conf`	RAW 2018 Invited Talks. IPDPS Workshops Jürgen Becker, Viktor K. Prasanna, Markus Weimer, Wayne Luk, Kaveh Aasaraai, Derek Chiou
2018	B	`conf`	Reconfigurable Acceleration of 3D-CNNs for Human Action Recognition with Block Floating-Point Representation. FPL Hongxiang Fan, Ho-Cheung Ng, Shuanglong Liu, Zhiqiang Que, Xinyu Niu, Wayne Luk
2018	—	`conf`	Reconfigurable Hardware Generation for Tensor Flow Models of CNN Algorithms on a Heterogeneous Acceleration Platform. SmartCom Jiajun Gao, Yongxin Zhu, Meikang Qiu, Kuen Hung Tsoi, Xinyu Niu, Wayne Luk, Ruizhe Zhao, Zhiqiang Que, Wei Mao, Can Feng, Xiaowen Zha, Guobao Deng, Jiayi Chen, Tao Liu
2018	J	`jnl`	Run-time Reconfigurable Acceleration for Genetic Programming Fitness Evaluation in Trading Strategies. J. Signal Process. Syst. Andreea-Ingrid Funie, Paul Grigoras, Pavel Burovskiy, Wayne Luk, Mark Salmon
2018	—	`conf`	Scheduling Algorithms for High Performance Network Switching on FPGAs: A Survey. FPT Nadeen Gebara, Jiuxi Meng, Wayne Luk, Paolo Costa
2018	J	`jnl`	Stream Processing Dual-Track CGRA for Object Inference. IEEE Trans. Very Large Scale Integr. Syst. Xitian Fan, Di Wu, Wei Cao, Wayne Luk, Lingli Wang
2018	B	`conf`	Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA. FPL Ruizhe Zhao, Ho-Cheung Ng, Wayne Luk, Xinyu Niu
2018	J	`jnl`	Towards Efficient Convolutional Neural Network for Domain-Specific Applications on FPGA. CoRR Ruizhe Zhao, Ho-Cheung Ng, Wayne Luk, Xinyu Niu
2018	—	`conf`	Towards Hardware Accelerated Reinforcement Learning for Application-Specific Robotic Control. ASAP Shengjia Shao, Jason Tsai, Michal Mysior, Wayne Luk, Thomas Chau, Alexander Warren, Ben Jeppesen
2017	J	`jnl`	A Domain Specific Approach to High Performance Heterogeneous Computing. IEEE Trans. Parallel Distributed Syst. Gordon Inggs, David B. Thomas, Wayne Luk
2017	J	`jnl`	A Fully-Pipelined Hardware Design for Gaussian Mixture Models. IEEE Trans. Computers Conghui He, Haohuan Fu, Ce Guo, Wayne Luk, Guangwen Yang
2017	Misc	`conf`	A Nanosecond-Level Hybrid Table Design for Financial Market Data Generators. FCCM Haohuan Fu, Conghui He, Wayne Luk, Weijia Li, Guangwen Yang
2017	J	`jnl`	ADvaNCE - Efficient and Scalable Approximate Density-Based Clustering Based on Hashing. Informatica Tianrun Li, Thomas Heinis, Wayne Luk
2017	A	`conf`	Accelerating Financial Market Server through Hybrid List Design (Abstract Only). FPGA Haohuan Fu, Conghui He, Huabin Ruan, Itay Greenspon, Wayne Luk, Yongkang Zheng, Junfeng Liao, Qing Zhang, Guangwen Yang
2017	—	`conf`	An FPGA-based tree crown detection approach for remote sensing images. FPT Weijia Li, Conghui He, Haohuan Fu, Wayne Luk
2017	J	`jnl`	Chapter Four - Data Flow Computing in Geoscience Applications. Adv. Comput. Lin Gan, Haohuan Fu, Oskar Mencer, Wayne Luk, Guangwen Yang
2017	J	`jnl`	Chapter Two - Advances in Dataflow Systems. Adv. Comput. Thomas Chau, Pavel Burovskiy, Michael J. Flynn, Wayne Luk
2017	C	`conf`	Convolutional Neural Networks on Dataflow Engines. ICCD Nils Voss, Marco Bacis, Oskar Mencer, Georgi Gaydadjiev, Wayne Luk
2017	—	`conf`	Custom Framework for Run-Time Trading Strategies. ARC Andreea-Ingrid Funie, Liucheng Guo, Xinyu Niu, Wayne Luk, Mark Salmon
2017	B	`conf`	Customised pearlmutter propagation: A hardware architecture for trust region policy optimisation. FPL Shengjia Shao, Wayne Luk
2017	—	`conf`	DeepPump: Multi-pumping deep Neural Networks. ASAP Ruizhe Zhao, Tim Todman, Wayne Luk, Xinyu Niu
2017	J	`jnl`	Efficient Assembly for High-Order Unstructured FEM Meshes (FPL 2015). ACM Trans. Reconfigurable Technol. Syst. Pavel Burovskiy, Paul Grigoras, Spencer J. Sherwin, Wayne Luk
2017	J	`jnl`	Exploiting the chaotic behaviour of atmospheric models with reconfigurable architectures. Comput. Phys. Commun. Francis P. Russell, Peter D. Düben, Xinyu Niu, Wayne Luk, Tim N. Palmer
2017	B	`conf`	Exploring the potential of reconfigurable platforms for order book update. FPL Conghui He, Haohuan Fu, Wayne Luk, Weijia Li, Guangen Yang
2017	B	`conf`	F-C3D: FPGA-based 3-dimensional convolutional neural network. FPL Hongxiang Fan, Xinyu Niu, Qiang Liu, Wayne Luk
2017	—	`conf`	FEM-based soft robotic control framework for intracavitary navigation. RCAR Kit-Hang Lee, Martin C. W. Leong, Marco C. K. Chow, Hing-Choi Fu, Wayne Luk, Kam-Yim Sze, Chung-Kwong Yeung, Ka-Wai Kwok
2017	—	`conf`	Hardware Acceleration for Machine Learning. ISVLSI Ruizhe Zhao, Wayne Luk, Xinyu Niu, Huifeng Shi, Haitao Wang
2017	—	`ch.`	In-Circuit Assertions and Exceptions for Reconfigurable Hardware Design. Provably Correct Systems Tim Todman, Wayne Luk
2017	J	`jnl`	Leveraging FPGAs for Accelerating Short Read Alignment. IEEE ACM Trans. Comput. Biol. Bioinform. James Arram, Thomas Kaplan, Wayne Luk, Peiyong Jiang
2017	J	`jnl`	Lossless Compression Decoders for Bitstreams and Software Binaries Based on High-Level Synthesis. IEEE Trans. Very Large Scale Integr. Syst. Jian Yan, Junqi Yuan, Philip Heng Wai Leong, Wayne Luk, Lingli Wang
2017	—	`conf`	Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms. ARC Ruizhe Zhao, Xinyu Niu, Yajie Wu, Wayne Luk, Qiang Liu
2017	B	`conf`	Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts. FPL Ho-Cheung Ng, Shuanglong Liu, Wayne Luk
2017	J	`jnl`	Solving Mesoscale Atmospheric Dynamics Using a Reconfigurable Dataflow Architecture. IEEE Micro Lin Gan, Haohuan Fu, Wayne Luk, Chao Yang, Wei Xue, Guangwen Yang
2017	J	`jnl`	The First 25 Years of the FPL Conference: Significant Papers. ACM Trans. Reconfigurable Technol. Syst. Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang
2017	J	`jnl`	Transparent In-Circuit Assertions for FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Eddie Hung, Tim Todman, Wayne Luk
2017	B	`conf`	Validating optimisations for chaotic simulations. FPL James Stanley Targett, Peter D. Düben, Wayne Luk
2017	—	`conf`	dfesnippets: An Open-Source Library for Dataflow Acceleration on FPGAs. ARC Paul Grigoras, Pavel Burovskiy, James Arram, Xinyu Niu, Kit Cheung, Junyi Xie, Wayne Luk
2016	—	`conf`	A Domain Specific Language for accelerated Multilevel Monte Carlo simulations. ASAP Ben Lindsey, Matthew Leslie, Wayne Luk
2016	—	`conf`	A Scalable Dataflow Accelerator for Real Time Onboard Hyperspectral Image Classification. ARC Shaojun Wang, Xinyu Niu, Ning Ma, Wayne Luk, Philip H. W. Leong, Yu Peng
2016	J	`jnl`	An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating. IEEE Trans. Very Large Scale Integr. Syst. Assem A. M. Bsoul, Steven J. E. Wilton, Kuen Hung Tsoi, Wayne Luk
2016	A	`conf`	CASK: Open-Source Custom Architectures for Sparse Kernels. FPGA Paul Grigoras, Pavel Burovskiy, Wayne Luk
2016	B	`conf`	Connect on the fly: Enhancing and prototyping of cycle-reconfigurable modules. FPL Hao Zhou, Xinyu Niu, Junqi Yuan, Lingli Wang, Wayne Luk
2016	—	`conf`	Dataflow design for optimal incremental SVM training. FPT Shengjia Shao, Oskar Mencer, Wayne Luk
2016	B	`conf`	EURECA compilation: Automatic optimisation of cycle-reconfigurable circuits. FPL Xinyu Niu, Nicholas Ng, Tomofumi Yuki, Shaojun Wang, Nobuko Yoshida, Wayne Luk
2016	—	`conf`	EXTRA: Towards the exploitation of eXascale technology for reconfigurable architectures. ReCoSoC Dirk Stroobandt, Ana Lucia Varbanescu, Catalin Bogdan Ciobanu, Muhammed Al Kadi, Andreas Brokalakis, George Charitopoulos, Tim Todman, Xinyu Niu, Dionisios N. Pnevmatikatos, Amit Kulkarni, Elias Vansteenkiste, Wayne Luk, Marco D. Santambrogio, Donatella Sciuto, Michael Hübner, Tobias Becker, Georgi Gaydadjiev, Antonis Nikitakis, Alex J. W. Thom
2016	—	`conf`	F-CNN: An FPGA-based framework for training Convolutional Neural Networks. ASAP Wenlai Zhao, Haohuan Fu, Wayne Luk, Teng Yu, Shaojun Wang, Bo Feng, Yuchun Ma, Guangwen Yang
2016	C	`conf`	Hashing-Based Approximate DBSCAN. ADBIS Tianrun Li, Thomas Heinis, Wayne Luk
2016	Misc	`conf`	Knowledge Transfer in Automatic Optimisation of Reconfigurable Designs. FCCM Maciej Kurek, Marc Peter Deisenroth, Wayne Luk, Timothy John Todman
2016	B	`conf`	Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA. FPL Paul Grigoras, Pavel Burovskiy, Wayne Luk, Spencer J. Sherwin
2016	J	`jnl`	Performance-driven instrumentation and mapping strategies using the LARA aspect-oriented programming approach. Softw. Pract. Exp. João M. P. Cardoso, José Gabriel F. Coutinho, Tiago Carvalho, Pedro C. Diniz, Zlatko Petrov, Wayne Luk, Fernando M. Gonçalves
2016	—	`conf`	Relation-oriented resource allocation for multi-accelerator systems. ASAP Teng Yu, Bo Feng, Mark Stillwell, José Gabriel F. Coutinho, Wenlai Zhao, Shuang Liang, Wayne Luk, Alexander L. Wolf, Yuchun Ma
2016	—	`ch.`	Self-adaptive Hardware Acceleration on a Heterogeneous Cluster. Self-aware Computing Systems Xinyu Niu, Tim Todman, Wayne Luk
2016	—	`ch.`	Self-aware Hardware Acceleration of Financial Applications on a Heterogeneous Cluster. Self-aware Computing Systems Maciej Kurek, Tobias Becker, Ce Guo, Stewart Denholm, Andreea-Ingrid Funie, Mark Salmon, Tim Todman, Wayne Luk
2015	J	`jnl`	A Transfer-Aware Runtime System for Heterogeneous Asynchronous Parallel Execution. SIGARCH Comput. Archit. News Soukaina N. Hmid, José Gabriel F. Coutinho, Wayne Luk
2015	J	`jnl`	A general-purpose framework for FPGA-accelerated genetic algorithms. Int. J. Bio Inspired Comput. Liucheng Guo, Andreea-Ingrid Funie, Zhongliu Xie, David B. Thomas, Wayne Luk
2015	Misc	`conf`	Accelerating SpMV on FPGAs by Compressing Nonzero Values. FCCM Paul Grigoras, Pavel Burovskiy, Eddie Hung, Wayne Luk
2015	J	`jnl`	An Efficient, Automatic Approach to High Performance Heterogeneous Computing. CoRR Gordon Inggs, David B. Thomas, Wayne Luk
2015	Misc	`conf`	Architectures and Precision Analysis for Modelling Atmospheric Variables with Chaotic Behaviour. FCCM Francis P. Russell, Peter D. Düben, Xinyu Niu, Wayne Luk, Tim N. Palmer
2015	J	`jnl`	Automating Elimination of Idle Functions by Runtime Reconfiguration. ACM Trans. Reconfigurable Technol. Syst. Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu, Oliver Pell
2015	A	`conf`	Delay-Bounded Routing for Shadow Registers. FPGA Eddie Hung, Joshua M. Levine, Edward A. Stott, George A. Constantinides, Wayne Luk
2015	A	`conf`	EURECA: On-Chip Configuration Generation for Effective Dynamic Data Access. FPGA Xinyu Niu, Wayne Luk, Yu Wang
2015	—	`conf`	EXTRA: Towards an Efficient Open Platform for Reconfigurable High Performance Computing. CSE Catalin Bogdan Ciobanu, Ana Lucia Varbanescu, Dionisios N. Pnevmatikatos, George Charitopoulos, Xinyu Niu, Wayne Luk, Marco D. Santambrogio, Donatella Sciuto, Muhammed Al Kadi, Michael Hübner, Tobias Becker, Georgi Gaydadjiev, Andreas Brokalakis, Antonis Nikitakis, Alex J. W. Thom, Elias Vansteenkiste, Dirk Stroobandt
2015	B	`conf`	Efficient assembly for high order unstructured FEM meshes. FPL Pavel Burovskiy, Paul Grigoras, Spencer J. Sherwin, Wayne Luk
2015	J	`jnl`	FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration. Microprocess. Microsystems Dionisios N. Pnevmatikatos, Kyprianos Papadimitriou, Tobias Becker, Peter Böhm, Andreas Brokalakis, Karel Bruneel, Catalin Bogdan Ciobanu, Tom Davidson, Georgi Gaydadjiev, Karel Heyse, Wayne Luk, Xinyu Niu, Ioannis Papaefstathiou, Danilo Pau, Oliver Pell, Christian Pilato, Marco D. Santambrogio, Donatella Sciuto, Dirk Stroobandt, Tim Todman, Elias Vansteenkiste
2015	—	`conf`	FPGA acceleration of reference-based compression for genomic data. FPT James Arram, Moritz Pflanzer, Thomas Kaplan, Wayne Luk
2015	A*	`conf`	GPU-based proximity query processing on unstructured triangular mesh model. ICRA Kit-Hang Lee, Ziyan Guo, Gary C. T. Chow, Yue Chen, Wayne Luk, Ka-Wai Kwok
2015	—	`conf`	HW/SW Partitioning Algorithm Targeting MPSOC with Dynamic Partial Reconfigurable Fabric. CAD/Graphics Chao Zhang, Yuchun Ma, Wayne Luk
2015	A*	`conf`	In-circuit temporal monitors for runtime verification of reconfigurable designs. DAC Tim Todman, Stephan Stilkerich, Wayne Luk
2015	—	`conf`	Lower precision for higher accuracy: Precision and resolution exploration for shallow water equations. FPT James Stanley Targett, Xinyu Niu, Francis P. Russell, Wayne Luk, Stephen Jeffress, Peter D. Düben
2015	J	`jnl`	Mapping Adaptive Particle Filters to Heterogeneous Reconfigurable Systems. ACM Trans. Reconfigurable Technol. Syst. Thomas C. P. Chau, Xinyu Niu, Alison Eele, Jan M. Maciejowski, Peter Y. K. Cheung, Wayne Luk
2015	J	`jnl`	Network-Level FPGA Acceleration of Low Latency Market Data Feed Arbitration. IEICE Trans. Inf. Syst. Stewart Denholm, Hiroaki Inoue, Takashi Takenaka, Tobias Becker, Wayne Luk
2015	J	`jnl`	Parallel Genetic Algorithms on Multiple FPGAs. SIGARCH Comput. Archit. News Liucheng Guo, Andreea-Ingrid Funie, David B. Thomas, Haohuan Fu, Wayne Luk
2015	Misc	`conf`	Pipelined Genetic Propagation. FCCM Liucheng Guo, Ce Guo, David B. Thomas, Wayne Luk
2015	J	`jnl`	Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems. IEEE Trans. Very Large Scale Integr. Syst. Qiang Liu, Terrence S. T. Mak, Tao Zhang, Xinyu Niu, Wayne Luk, Alex Yakovlev
2015	B	`conf`	Preface. FPL Peter Y. K. Cheung, Wayne Luk, Cristina Silvano
2015	—	`conf`	RAW Introduction and Committees. IPDPS Workshops Jürgen Becker, Ken Eguro, Diana Göhringer, Wayne Luk, Marco D. Santambrogio, Ramachandran Vaidyanathan, Steven J. E. Wilton
2015	A	`conf`	Ramethy: Reconfigurable Acceleration of Bisulfite Sequence Alignment. FPGA James Arram, Wayne Luk, Peiyong Jiang
2015	—	`conf`	Reconfigurable acceleration of fitness evaluation in trading strategies. ASAP Andreea-Ingrid Funie, Paul Grigoras, Pavel Burovskiy, Wayne Luk, Mark Salmon
2015	B	`conf`	Recursive pipelined genetic propagation for bilevel optimisation. FPL Shengjia Shao, Liucheng Guo, Ce Guo, Thomas C. P. Chau, David B. Thomas, Wayne Luk, Stephen Weston
2015	—	`conf`	Relocation-Aware Floorplanning for Partially-Reconfigurable FPGA-Based Systems. IPDPS Workshops Marco Rabozzi, Riccardo Cattaneo, Tobias Becker, Wayne Luk, Marco D. Santambrogio
2015	J	`jnl`	Seeing Shapes in Clouds: On the Performance-Cost trade-off for Heterogeneous Infrastructure-as-a-Service. CoRR Gordon Inggs, David B. Thomas, George A. Constantinides, Wayne Luk
2015	B	`conf`	Significant papers from the first 25 years of the FPL conference. FPL Philip Heng Wai Leong, Hideharu Amano, Jason Helge Anderson, Koen Bertels, João M. P. Cardoso, Oliver Diessel, Guy Gogniat, Mike Hutton, JunKyu Lee, Wayne Luk, Patrick Lysaght, Marco Platzner, Viktor K. Prasanna, Tero Rissa, Cristina Silvano, Hayden Kwok-Hay So, Yu Wang
2015	J	`jnl`	Solving the Global Atmospheric Equations through Heterogeneous Reconfigurable Platforms. ACM Trans. Reconfigurable Technol. Syst. Lin Gan, Haohuan Fu, Wayne Luk, Chao Yang, Wei Xue, Xiaomeng Huang, Youhui Zhang, Guangwen Yang
2014	J	`jnl`	A Domain Specific Approach to Heterogeneous Computing: From Availability to Accessibility. CoRR Gordon Inggs, David B. Thomas, Wayne Luk
2014	C	`conf`	A Hybrid Genetic-Programming Swarm-Optimisation Approach for Examining the Nature and Stability of High Frequency Trading Strategies. ICMLA Andreea-Ingrid Funie, Mark Salmon, Wayne Luk
2014	J	`jnl`	A Self-Aware Tuning and Self-Aware Evaluation Method for Finite-Difference Applications in Reconfigurable Systems. ACM Trans. Reconfigurable Technol. Syst. Xinyu Niu, Qiwei Jin, Wayne Luk, Stephen Weston
2014	—	`conf`	A dataflow system for anomaly detection and analysis. FPT Andrei Bara, Xinyu Niu, Wayne Luk
2014	B	`conf`	A highly-efficient and green data flow engine for solving euler atmospheric equations. FPL Lin Gan, Haohuan Fu, Chao Yang, Wayne Luk, Wei Xue, Oskar Mencer, Xiaomeng Huang, Guangwen Yang
2014	A	`conf`	Accelerating parameter estimation for multivariate self-exciting point processes. FPGA Ce Guo, Wayne Luk
2014	—	`conf`	Accelerating transfer entropy computation. FPT Shengjia Shao, Ce Guo, Wayne Luk, Stephen Weston
2014	—	`conf`	An approach of processor core customization for stencil computation. ASAP Yanhua Li, Youhui Zhang, Jianfeng Yang, Wayne Luk, Guangwen Yang, Weimin Zheng
2014	B	`conf`	An efficient sparse conjugate gradient solver using a Beneš permutation network. FPL Gary C. T. Chow, Paul Grigoras, Pavel Burovskiy, Wayne Luk
2014	B	`conf`	Automated Framework for General-Purpose Genetic Algorithms in FPGAs. EvoApplications Liucheng Guo, David B. Thomas, Wayne Luk
2014	B	`conf`	Automated framework for FPGA-based parallel genetic algorithms. FPL Liucheng Guo, David B. Thomas, Ce Guo, Wayne Luk
2014	Misc	`conf`	Automating Optimization of Reconfigurable Designs. FCCM Maciej Kurek, Tobias Becker, Thomas C. P. Chau, Wayne Luk
2014	—	`conf`	Collaborative processing of Least-Square Monte Carlo for American options. FPT Jinzhe Yang, Ce Guo, Wayne Luk, Terence Nahar
2014	B	`conf`	Dataflow acceleration of Krylov subspace sparse banded problems. FPL Pavel Burovskiy, Stephen Girdlestone, Craig Davies, Spencer J. Sherwin, Wayne Luk
2014	—	`conf`	Effective Reconfigurable Design: The FASTER Approach. ARC Dionisios N. Pnevmatikatos, Tobias Becker, Andreas Brokalakis, Georgi Nedeltchev Gaydadjiev, Wayne Luk, Kyprianos Papadimitriou, Ioannis Papaefstathiou, Danilo Pau, Oliver Pell, Christian Pilato, Marco D. Santambrogio, Donatella Sciuto, Dirk Stroobandt
2014	C	`conf`	Elastic Management of Reconfigurable Accelerators. ISPA Paul Grigoras, Max Tottenham, Xinyu Niu, José Gabriel F. Coutinho, Wayne Luk
2014	C	`conf`	FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board. ISPA Fabrizio Spada, Alberto Scolari, Gianluca C. Durelli, Riccardo Cattaneo, Marco D. Santambrogio, Donatella Sciuto, Dionisios N. Pnevmatikatos, Georgi Gaydadjiev, Oliver Pell, Andreas Brokalakis, Wayne Luk, Dirk Stroobandt, Danilo Pau
2014	—	`conf`	HARNESS Project: Managing Heterogeneous Computing Resources for a Cloud Platform. ARC José Gabriel F. Coutinho, Oliver Pell, Eoghan O'Neill, Peter Sanders, John McGlone, Paul Grigoras, Wayne Luk, Carmelo Ragusa
2014	C	`conf`	HW/SW partitioning for region-based dynamic partial reconfigurable FPGAs. ICCD Yuchun Ma, Jinglan Liu, Chao Zhang, Wayne Luk
2014	J	`jnl`	Hardware Acceleration for an Accurate Stereo Vision System Using Mini-Census Adaptive Support Region. ACM Trans. Embed. Comput. Syst. Yi Shan, Yuchen Hao, Wenqiang Wang, Yu Wang, Xu Chen, Huazhong Yang, Wayne Luk
2014	—	`conf`	Is high level synthesis ready for business? A computational finance case study. FPT Gordon Inggs, Shane T. Fleming, David B. Thomas, Wayne Luk
2014	—	`conf`	Low latency FPGA acceleration of market data feed arbitration. ASAP Stewart Denholm, Hiroaki Inoue, Takashi Takenaka, Tobias Becker, Wayne Luk
2014	J	`jnl`	Mapping Loop Structures Onto Parametrized Hardware Pipelines. IEEE Trans. Very Large Scale Integr. Syst. Adrien Le Masle, Wayne Luk
2014	B	`conf`	Particle filtering-based Maximum Likelihood Estimation for financial parameter estimation. FPL Jinzhe Yang, Binghuan Lin, Wayne Luk, Terence Nahar
2014	B	`conf`	Patra: Parallel tree-reweighted message passing architecture. FPL Wenlai Zhao, Haohuan Fu, Guangwen Yang, Wayne Luk
2014	J	`jnl`	Pipelined HAC Estimation Engines for Multivariate Time Series. J. Signal Process. Syst. Ce Guo, Wayne Luk
2014	—	`conf`	Pipelined reconfigurable accelerator for ordinal pattern encoding. ASAP Ce Guo, Wayne Luk, Stephen Weston
2014	Misc	`conf`	SMCGen: Generating Reconfigurable Design for Sequential Monte Carlo Applications. FCCM Thomas C. P. Chau, Maciej Kurek, James Stanley Targett, Jake Humphrey, Georgios Skouroupathis, Alison Eele, Jan M. Maciejowski, Benjamin Cope, Kathryn Cobden, Philip Heng Wai Leong, Peter Y. K. Cheung, Wayne Luk
2014	B	`conf`	Transparent insertion of latency-oblivious logic onto FPGAs. FPL Eddie Hung, Tim Todman, Wayne Luk
2014	J	`jnl`	Using Statistical Assertions to Guide Self-Adaptive Systems. Int. J. Reconfigurable Comput. Tim Todman, Stephan Stilkerich, Wayne Luk
2013	B	`conf`	A Heterogeneous Computing Framework for Computational Finance. ICPP Gordon Inggs, David B. Thomas, Wayne Luk
2013	—	`conf`	A framework for effective exploitation of partial reconfiguration in dataflow computing. ReCoSoC Riccardo Cattaneo, Xinyu Niu, Christian Pilato, Tobias Becker, Wayne Luk, Marco D. Santambrogio
2013	B	`conf`	A scalable design approach for stencil computation on reconfigurable clusters. FPL Xinyu Niu, José Gabriel F. Coutinho, Wayne Luk
2013	—	`conf`	Accelerating HAC estimation for multivariate time series. ASAP Ce Guo, Wayne Luk
2013	B	`conf`	Accelerating maximum likelihood estimation for Hawkes point processes. FPL Ce Guo, Wayne Luk
2013	J	`jnl`	Accelerating sequential Monte Carlo method for real-time air traffic management. SIGARCH Comput. Archit. News Thomas C. P. Chau, James Stanley Targett, Marlon Wijeyasinghe, Wayne Luk, Peter Y. K. Cheung, Benjamin Cope, Alison Eele, Jan M. Maciejowski
2013	B	`conf`	Accelerating solvers for global atmospheric equations through mixed-precision data flow engine. FPL Lin Gan, Haohuan Fu, Wayne Luk, Chao Yang, Wei Xue, Xiaomeng Huang, Youhui Zhang, Guangwen Yang
2013	—	`conf`	Acceleration of real-time Proximity Query for dynamic active constraints. FPT Thomas C. P. Chau, Ka-Wai Kwok, Gary C. T. Chow, Kuen Hung Tsoi, Kit-Hang Lee, Zion Tse, Peter Y. K. Cheung, Wayne Luk
2013	Misc	`conf`	An FPGA-Based Data Flow Engine for Gaussian Copula Model. FCCM Huabin Ruan, Xiaomeng Huang, Haohuan Fu, Guangwen Yang, Wayne Luk, Sébastien Racanière, Oliver Pell, Wenjing Han
2013	—	`conf`	Application-specific customisation of market data feed arbitration. FPT Stewart Denholm, Hiroaki Inoue, Takashi Takenaka, Wayne Luk
2013	—	`conf`	Aspect driven compilation for dataflow designs. ASAP Paul Grigoras, Xinyu Niu, José Gabriel F. Coutinho, Wayne Luk, Jacob A. Bower, Oliver Pell
2013	Misc	`conf`	Automating Elimination of Idle Functions by Run-Time Reconfiguration. FCCM Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu
2013	A	`conf`	Automating resource optimisation in reconfigurable design (abstract only). FPGA Xinyu Niu, Thomas C. P. Chau, Qiwei Jin, Wayne Luk, Qiang Liu
2013	J	`jnl`	Controlling a complete hardware synthesis toolchain with LARA aspects. Microprocess. Microsystems João M. P. Cardoso, Tiago Carvalho, José Gabriel F. Coutinho, Ricardo Nobre, Razvan Nane, Pedro C. Diniz, Zlatko Petrov, Wayne Luk, Koen Bertels
2013	J	`jnl`	Customisable architectures for the set covering problem. SIGARCH Comput. Archit. News Liucheng Guo, David B. Thomas, Wayne Luk
2013	J	`jnl`	Customisable pipelined engine for intensity evaluation in multivariate hawkes point processes. SIGARCH Comput. Archit. News Ce Guo, Wayne Luk, Ekaterina Vinkovskaya, Rama Cont
2013	J	`jnl`	Dimensionality Reduction in Controlling Articulated Snake Robot for Endoscopy Under Dynamic Active Constraints. IEEE Trans. Robotics Ka-Wai Kwok, Kuen Hung Tsoi, Valentina Vitiello, James Clark, Gary C. T. Chow, Wayne Luk, Guang-Zhong Yang
2013	—	`conf`	Dynamic Stencil: Effective exploitation of run-time resources in reconfigurable clusters. FPT Xinyu Niu, José Gabriel F. Coutinho, Yu Wang, Wayne Luk
2013	Misc	`conf`	Global Atmospheric Simulation on a Reconfigurable Platform. FCCM Lin Gan, Haohuan Fu, Wayne Luk, Chao Yang, Wei Xue, Guangwen Yang
2013	—	`conf`	Hardware Acceleration of Genetic Sequence Alignment. ARC James Arram, Kuen Hung Tsoi, Wayne Luk, Peiyong Jiang
2013	—	`conf`	Heterogeneous Reconfigurable System for Adaptive Particle Filters in Real-Time Applications. ARC Thomas C. P. Chau, Xinyu Niu, Alison Eele, Wayne Luk, Peter Y. K. Cheung, Jan M. Maciejowski
2013	J	`jnl`	Multiplierless Algorithm for Multivariate Gaussian Random Number Generation in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. David B. Thomas, Wayne Luk
2013	J	`jnl`	Parallel neighbourhood search on many-core platforms. Int. J. Comput. Sci. Eng. Yuet Ming Lam, Kuen Hung Tsoi, Wayne Luk
2013	J	`jnl`	Parallel partitioning for distributed systems using sequential assignment. J. Parallel Distributed Comput. Simon A. Spacey, Wayne Luk, Daniel Kuhn, Paul H. J. Kelly
2013	—	`conf`	Parallelisation of Sequential Monte Carlo for real-time control in air traffic management. CDC Alison Eele, Jan M. Maciejowski, Thomas Chau, Wayne Luk
2013	—	`conf`	Parametric Optimization of Reconfigurable Designs Using Machine Learning. ARC Maciej Kurek, Tobias Becker, Wayne Luk
2013	—	`conf`	RALP: Reconvergence-aware layer partitioning for 3D FPGAs. ReConFig Qingyu Liu, Yuchun Ma, Yu Wang, Wayne Luk, Jinian Bian
2013	Misc	`conf`	Reconfigurable Acceleration of Short Read Mapping. FCCM James Arram, Kuen Hung Tsoi, Wayne Luk, Peiyong Jiang
2013	—	`conf`	Reconfigurable filtered acceleration of short read alignment. FPT James Arram, Wayne Luk, Peiyong Jiang
2013	B	`conf`	Runtime assertions and exceptions for streaming systems. FPL Tim Todman, Wayne Luk
2013	J	`jnl`	SPREAD: A Streaming-Based Partially Reconfigurable Architecture and Programming Model. IEEE Trans. Very Large Scale Integr. Syst. Ying Wang, Xuegong Zhou, Lingli Wang, Jian Yan, Wayne Luk, Chenglian Peng, Jiarong Tong
2013	—	`conf`	Scalable Session Programming for Heterogeneous High-Performance Systems. SEFM Workshops Nicholas Ng, Nobuko Yoshida, Wayne Luk
2013	J	`jnl`	The LUT-SR Family of Uniform Random Number Generators for FPGA Architectures. IEEE Trans. Very Large Scale Integr. Syst. David B. Thomas, Wayne Luk
2012	—	`conf`	A Large-Scale Spiking Neural Network Accelerator for FPGA Systems. ICANN (1) Kit Cheung, Simon R. Schultz, Wayne Luk
2012	Misc	`conf`	A Mixed Precision Methodology for Mathematical Optimisation. FCCM Gary C. T. Chow, Wayne Luk, Philip Heng Wai Leong
2012	—	`conf`	A Reconfigurable Computing Approach for Efficient and Scalable Parallel Graph Exploration. ASAP Brahim Betkaoui, Yu Wang, David B. Thomas, Wayne Luk
2012	—	`conf`	A fully-pipelined expectation-maximization engine for Gaussian Mixture Models. FPT Ce Guo, Haohuan Fu, Wayne Luk
2012	A	`conf`	A mixed precision Monte Carlo methodology for reconfigurable accelerator systems. FPGA Gary Chun Tak Chow, Anson Hong Tak Tse, Qiwei Jin, Wayne Luk, Philip Heng Wai Leong, David B. Thomas
2012	—	`conf`	A partially reconfigurable architecture supporting hardware threads. FPT Ying Wang, Jian Yan, Xuegong Zhou, Lingli Wang, Wayne Luk, Chenglian Peng, Jiarong Tong
2012	B	`conf`	Adaptive Sequential Monte Carlo approach for real-time applications. FPL Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung, Alison Eele, Jan M. Maciejowski
2012	J	`jnl`	Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms. J. Signal Process. Syst. Qiang Liu, Tim Todman, Wayne Luk, George A. Constantinides
2012	C	`conf`	Controlling Hardware Synthesis with Aspects. DSD João M. P. Cardoso, Tiago Carvalho, José Gabriel F. Coutinho, Pedro C. Diniz, Zlatko Petrov, Wayne Luk
2012	J	`jnl`	Design Exploration of Quadrature Methods in Option Pricing. IEEE Trans. Very Large Scale Integr. Syst. Anson H. T. Tse, David B. Thomas, Wayne Luk
2012	B	`conf`	Detecting power attacks on reconfigurable hardware. FPL Adrien Le Masle, Wayne Luk
2012	—	`conf`	Efficient Communication for FPGA Clusters. ARC Stewart Denholm, Kuen Hung Tsoi, Peter R. Pietzuch, Wayne Luk
2012	—	`conf`	Evaluating reconfigurable dataflow computing using the Himeno benchmark. ReConFig Yukinori Sato, Yasushi Inoguchi, Wayne Luk, Tadao Nakamura
2012	—	`conf`	Experiments with the LARA aspect-oriented approach. AOSD (Companion) José Gabriel F. Coutinho, Tiago Carvalho, Sérgio Durand, João M. P. Cardoso, Ricardo Nobre, Pedro C. Diniz, Wayne Luk
2012	B	`conf`	Exploiting run-time reconfiguration in stencil computation. FPL Xinyu Niu, Qiwei Jin, Wayne Luk, Qiang Liu, Oliver Pell
2012	C	`conf`	FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration. DSD Dionisios N. Pnevmatikatos, Tobias Becker, Andreas Brokalakis, Karel Bruneel, Georgi Gaydadjiev, Wayne Luk, Kyprianos Papadimitriou, Ioannis Papaefstathiou, Oliver Pell, Christian Pilato, M. Robart, Marco D. Santambrogio, Donatella Sciuto, Dirk Stroobandt, Tim Todman
2012	J	`jnl`	FISH: Fast Instruction SyntHesis for Custom Processors. IEEE Trans. Very Large Scale Integr. Syst. Kubilay Atasu, Wayne Luk, Oskar Mencer, Can C. Özturan, Günhan Dündar
2012	—	`conf`	FPGA based memory efficient high resolution stereo vision system for video tolling. FPT Yi Shan, Zilong Wang, Wenqiang Wang, Yuchen Hao, Yu Wang, Kuen Hung Tsoi, Wayne Luk, Huazhong Yang
2012	—	`conf`	Heterogeneous Systems for Energy Efficient Scientific Computing. ARC Qiang Liu, Wayne Luk
2012	J	`jnl`	Improving communication latency with the write-only architecture. J. Parallel Distributed Comput. Simon A. Spacey, Wayne Luk, Paul H. J. Kelly, Daniel Kuhn
2012	—	`conf`	LARA: an aspect-oriented programming language for embedded systems. AOSD João M. P. Cardoso, Tiago Carvalho, José Gabriel F. Coutinho, Wayne Luk, Ricardo Nobre, Pedro C. Diniz, Zlatko Petrov
2012	J	`jnl`	Modelling reconfigurable systems in event driven simulation. SIGARCH Comput. Archit. News Kuen Hung Tsoi, Tobias Becker, Wayne Luk
2012	—	`conf`	Multi-level Customisation Framework for Curve Based Monte Carlo Financial Simulations. ARC Qiwei Jin, Diwei Dong, Anson H. T. Tse, Gary Chun Tak Chow, David B. Thomas, Wayne Luk, Stephen Weston
2012	—	`conf`	Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration. CSE Kyprianos Papadimitriou, Christian Pilato, Dionisios N. Pnevmatikatos, Marco D. Santambrogio, Catalin Bogdan Ciobanu, Tim Todman, Tobias Becker, Tom Davidson, Xinyu Niu, Georgi Gaydadjiev, Wayne Luk, Dirk Stroobandt
2012	—	`conf`	Optimising Performance of Quadrature Methods with Reduced Precision. ARC Anson H. T. Tse, Gary C. T. Chow, Qiwei Jin, David B. Thomas, Wayne Luk
2012	B	`conf`	Optimising explicit finite difference option pricing for dynamic constant reconfiguration. FPL Qiwei Jin, Tobias Becker, Wayne Luk, David B. Thomas
2012	J	`jnl`	Optimizing Floating Point Units in Hybrid FPGAs. IEEE Trans. Very Large Scale Integr. Syst. Chi Wai Yu, Alastair M. Smith, Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton
2012	J	`jnl`	Optimizing Hardware Design by Composing Utility-Directed Transformations. IEEE Trans. Computers Qiang Liu, Tim Todman, Wayne Luk, George A. Constantinides
2012	B	`conf`	Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study. FPL Brahim Betkaoui, Yu Wang, David B. Thomas, Wayne Luk
2012	—	`conf`	Parametric reconfigurable designs with Machine Learning Optimizer. FPT Maciej Kurek, Wayne Luk
2012	—	`conf`	Reconfigurable Design Automation by High-Level Exploration. ASAP Tim Todman, Wayne Luk
2012	J	`jnl`	Reconfigurable FPGA-based switching path frequency-domain echo canceller with applications to voice control device. Digit. Signal Process. Ka Fai Cedric Yiu, Yao Lu, Chun Hok Ho, Wayne Luk, Jiaquan Huo, Sven Nordholm
2012	—	`conf`	Resource-Efficient Designs Using an Aspect-Oriented Approach. CSE José Gabriel F. Coutinho, Sujit Bhattacharya, Wayne Luk, George A. Constantinides, João M. P. Cardoso, Tiago Carvalho, Pedro C. Diniz, Zlatko Petrov
2012	J	`jnl`	Roberts: reconfigurable platform for benchmarking real-time systems. SIGARCH Comput. Archit. News Thomas C. P. Chau, Wayne Luk, Peter Y. K. Cheung
2012	J	`jnl`	Robust Software Partitioning with Multiple Instantiation. INFORMS J. Comput. Simon A. Spacey, Wolfram Wiesemann, Daniel Kuhn, Wayne Luk
2012	—	`conf`	Self-Adaptive Heterogeneous Cluster with Wireless Network. IPDPS Workshops Xinyu Niu, Kuen Hung Tsoi, Wayne Luk
2012	—	`conf`	Smart technologies for effective reconfiguration: The FASTER approach. ReCoSoC Marco D. Santambrogio, Dionisios N. Pnevmatikatos, Kyprianos Papadimitriou, Christian Pilato, Georgi Gaydadjiev, Dirk Stroobandt, Tom Davidson, Tobias Becker, Tim Todman, Wayne Luk, Alessandra Bonetto, Andrea Cazzaniga, Gianluca Durelli, Donatella Sciuto
2012	Misc	`conf`	Specifying Compiler Strategies for FPGA-based Systems. FCCM João M. P. Cardoso, João Teixeira, José C. Alves, Ricardo Nobre, Pedro C. Diniz, José Gabriel F. Coutinho, Wayne Luk
2012	B	`conf`	Verification of streaming designs by combining symbolic simulation and equivalence checking. FPL Tim Todman, Wayne Luk
2012	—	`conf`	Verification of streaming hardware and software codesigns. FPT Tim Todman, Peter Böhm, Wayne Luk
2011	J	`jnl`	A Systematic Design Space Exploration Approach to Customising Multi-Processor Architectures: Exemplified Using Graphics Processors. Trans. High Perform. Embed. Archit. Compil. Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes
2011	A	`conf`	A comparison of FPGAs, GPUS and CPUS for Smith-Waterman algorithm (abstract only). FPGA Yoshiki Yamaguchi, Kuen Hung Tsoi, Wayne Luk
2011	—	`conf`	A framework for FPGA acceleration of large graph problems: Graphlet counting case study. FPT Brahim Betkaoui, David B. Thomas, Wayne Luk, Natasa Przulj
2011	J	`jnl`	Adaptive Routing in Network-on-Chips Using a Dynamic-Programming Network. IEEE Trans. Ind. Electron. Terrence S. T. Mak, Peter Y. K. Cheung, Kai-Pui Lam, Wayne Luk
2011	J	`jnl`	An Analytical Model Relating FPGA Architecture to Logic Density and Depth. IEEE Trans. Very Large Scale Integr. Syst. Joydip Das, Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk
2011	—	`conf`	Automating formal verification of customized soft-processors. FPT Kong Woei Susanto, Wayne Luk
2011	—	`conf`	Constant power reconfigurable computing. FPT Adrien Le Masle, Gary Chun Tak Chow, Wayne Luk
2011	—	`conf`	CusComNet: A customisable network for reconfigurable heterogeneous clusters. ASAP Stewart Denholm, Kuen Hung Tsoi, Peter R. Pietzuch, Wayne Luk
2011	—	`conf`	Customisable Multi-Processor Acceleration of Inductive Logic Programming. ILP (Late Breaking Papers) Andreas Kirkeby Fidjeland, Wayne Luk, Stephen H. Muggleton
2011	J	`jnl`	Design Optimizations for Tiled Partially Reconfigurable Systems. IEEE Trans. Very Large Scale Integr. Syst. Markus Koester, Wayne Luk, Jens Hagemeyer, Mario Porrmann, Ulrich Rückert
2011	—	`conf`	Dynamic Constant Reconfiguration for Explicit Finite Difference Option Pricing. ReConFig Tobias Becker, Qiwei Jin, Wayne Luk, Stephen Weston
2011	J	`jnl`	Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation. Trans. High Perform. Embed. Archit. Compil. William George Osborne, Wayne Luk, José Gabriel F. Coutinho, Oskar Mencer
2011	—	`conf`	FPGA-Based Smith-Waterman Algorithm: Analysis and Novel Design. ARC Yoshiki Yamaguchi, Kuen Hung Tsoi, Wayne Luk
2011	—	`conf`	Hydrate: Hybrid Reconfigurable Architecture Expressions. FPT Chi Wai Yu, Fred Cox, Wayne Luk, Ray C. C. Cheung
2011	Misc	`conf`	Mixed Precision Processing in Reconfigurable Systems. FCCM Gary Chun Tak Chow, K. W. Kwok, Wayne Luk, Philip Heng Wai Leong
2011	—	`conf`	Objective-driven workload allocation in heterogeneous computing systems. FPT Qiang Liu, Wayne Luk
2011	Misc	`conf`	On Comparing Financial Option Price Solvers on FPGA. FCCM Qiwei Jin, Wayne Luk, David B. Thomas
2011	—	`conf`	Parametrized hardware architectures for the Lucas primality test. ICSAMOS Adrien Le Masle, Wayne Luk, Csaba Andras Moritz
2011	—	`conf`	Power adaptive computing system design in energy harvesting environment. ICSAMOS Qiang Liu, Terrence S. T. Mak, Junwen Luo, Wayne Luk, Alexandre Yakovlev
2011	J	`jnl`	Power profiling and optimization for heterogeneous multi-core systems. SIGARCH Comput. Archit. News Kuen Hung Tsoi, Wayne Luk
2011	B	`conf`	Reconfiguring Distributed Applications in FPGA Accelerated Cluster with Wireless Networking. FPL Xinyu Niu, Kuen Hung Tsoi, Wayne Luk
2011	B	`conf`	Unifying Finite Difference Option-Pricing for Hardware Acceleration. FPL Qiwei Jin, Wayne Luk, David B. Thomas
2010	B	`conf`	A Karatsuba-Based Montgomery Multiplier. FPL Gary Chun Tak Chow, Ken Eguro, Wayne Luk, Philip Heng Wai Leong
2010	Misc	`conf`	A Scripting Engine for Combining Design Transformations. FCCM Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides
2010	—	`conf`	An FPGA-specific algorithm for direct generation of multi-variate Gaussian random numbers. ASAP David B. Thomas, Wayne Luk
2010	C	`conf`	Automated placement of reconfigurable regions for relocatable modules. ISCAS Tobias Becker, Markus Koester, Wayne Luk
2010	A	`conf`	Axel: a heterogeneous cluster with FPGAs and GPUs. FPGA Kuen Hung Tsoi, Wayne Luk
2010	J	`jnl`	Benchmarking and evaluating reconfigurable architectures targeting the mobile domain. ACM Trans. Design Autom. Electr. Syst. Peter Jamieson, Tobias Becker, Peter Y. K. Cheung, Wayne Luk, Tero Rissa, Teemu Pitkänen
2010	A	`conf`	Combining optimizations in automated low power design. DATE Qiang Liu, Tim Todman, Wayne Luk
2010	—	`conf`	Comparing performance and energy efficiency of FPGAs and GPUs for high productivity computing. FPT Brahim Betkaoui, David B. Thomas, Wayne Luk
2010	—	`conf`	Convex models for accelerating applications on FPGA-based clusters. FPT Qiang Liu, Tim Todman, Kuen Hung Tsoi, Wayne Luk
2010	C	`conf`	Customizable Composition and Parameterization of Hardware Design Transformations. DSD Tim Todman, Qiang Liu, Wayne Luk, George A. Constantinides
2010	—	`conf`	Design space exploration of parametric pipelined designs. ASAP Adrien Le Masle, Wayne Luk
2010	—	`conf`	Dynamic scheduling Monte-Carlo framework for multi-accelerator heterogeneous clusters. FPT Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk
2010	J	`jnl`	Efficient reconfigurable design for pricing asian options. SIGARCH Comput. Archit. News Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk
2010	Misc	`conf`	Energy-Aware Optimisation for Run-Time Reconfiguration. FCCM Tobias Becker, Wayne Luk, Peter Y. K. Cheung
2010	A	`conf`	Exploration of hardware sharing for image encoders. DATE Sebastián López, Roberto Sarmiento, Philip G. Potter, Wayne Luk, Peter Y. K. Cheung
2010	—	`conf`	Exploring algorithmic trading in reconfigurable hardware. ASAP Stephen Wray, Wayne Luk, Peter R. Pietzuch
2010	J	`jnl`	FPGA Designs with Optimized Logarithmic Arithmetic. IEEE Trans. Computers Haohuan Fu, Oskar Mencer, Wayne Luk
2010	B	`conf`	FPGA-Optimised Uniform Random Number Generators Using LUTs and Shift Registers. FPL David B. Thomas, Wayne Luk
2010	J	`jnl`	HArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms. IEEE Micro Koen Bertels, Vlad Mihai Sima, Yana Yankova, Georgi Kuzmanov, Wayne Luk, José Gabriel F. Coutinho, Fabrizio Ferrandi, Christian Pilato, Marco Lattuada, Donatella Sciuto, Andrea Michelotti
2010	J	`jnl`	Multiloop Parallelisation Using Unrolling and Fission. Int. J. Reconfigurable Comput. Yuet Ming Lam, José Gabriel F. Coutinho, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk
2010	—	`conf`	Parametric Encryption Hardware Design. ARC Adrien Le Masle, Wayne Luk, Jared Eldredge, Kristopher Carver
2010	J	`jnl`	Performance Comparison of Graphics Processors to Reconfigurable Logic: A Case Study. IEEE Trans. Computers Ben Cope, Peter Y. K. Cheung, Wayne Luk, Lee W. Howes
2010	J	`jnl`	Power Characterisation for Fine-Grain Reconfigurable Fabrics. Int. J. Reconfigurable Comput. Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa
2010	J	`jnl`	Programming framework for clusters with heterogeneous accelerators. SIGARCH Comput. Archit. News Kuen Hung Tsoi, Anson H. T. Tse, Peter R. Pietzuch, Wayne Luk
2010	B	`conf`	Reconfigurable Control Variate Monte-Carlo Designs for Pricing Exotic Options. FPL Anson H. T. Tse, David B. Thomas, Kuen Hung Tsoi, Wayne Luk
2010	B	`conf`	Run-Time Reconfiguration for a Reconfigurable Algorithmic Trading Engine. FPL Stephen Wray, Wayne Luk, Peter R. Pietzuch
2010	—	`conf`	Towards an embedded biologically-inspired machine vision processor. FPT Vinay Sriram, David D. Cox, Kuen Hung Tsoi, Wayne Luk
2010	J	`jnl`	Wave-pipelined intra-chip signaling for on-FPGA communications. Integr. Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2009	Misc	`conf`	A DP-network for optimal dynamic routing in network-on-chip. CODES+ISSS Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam
2009	A	`conf`	A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation. FPGA David B. Thomas, Lee W. Howes, Wayne Luk
2009	—	`conf`	A high-level compilation toolchain for heterogeneous systems. SoCC Wayne Luk, José Gabriel de Figueiredo Coutinho, Timothy John Todman, Yuet Ming Lam, William George Osborne, Kong Woei Susanto, Qiang Liu, W. S. Wong
2009	Misc	`conf`	Accelerating Quadrature Methods for Option Valuation. FCCM Anson H. T. Tse, David B. Thomas, Wayne Luk
2009	J	`jnl`	Accelerating Seismic Computations Using Customized Number Representations on FPGAs. EURASIP J. Embed. Syst. Haohuan Fu, William George Osborne, Robert G. Clapp, Oskar Mencer, Wayne Luk
2009	—	`conf`	Accelerating a Virtual Ecology Model with FPGAs. ASAP Julien Lamoureux, Tony Field, Wayne Luk
2009	Misc	`conf`	Benchmarking Reconfigurable Architectures in the Mobile Domain. FCCM Peter Jamieson, Tobias Becker, Wayne Luk, Peter Y. K. Cheung, Tero Rissa, Teemu Pitkänen
2009	B	`conf`	Design Validation by Symbolic Simulation and Equivalence Checking: A Case Study in Memory Optimization for Image Manipulation. SOFSEM Kong Woei Susanto, Tim Todman, José Gabriel F. Coutinho, Wayne Luk
2009	A	`conf`	Design optimizations to improve placeability of partial reconfiguration modules. DATE Markus Koester, Wayne Luk, Jens Hagemeyer, Mario Porrmann
2009	J	`jnl`	Exploring Reconfigurable Architectures for Tree-Based Option Pricing Models. ACM Trans. Reconfigurable Technol. Syst. Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope
2009	B	`conf`	Exploring reconfigurable architectures for explicit finite difference option pricing models. FPL Qiwei Jin, David B. Thomas, Wayne Luk
2009	—	`conf`	FPGA Accelerated Low-Latency Market Data Feed Processing. Hot Interconnects Gareth W. Morris, David B. Thomas, Wayne Luk
2009	Misc	`conf`	FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks. FCCM David B. Thomas, Wayne Luk
2009	J	`jnl`	Floating-Point FPGA: Architecture and Modeling. IEEE Trans. Very Large Scale Integr. Syst. Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton
2009	—	`conf`	Harnessing Human Computation Cycles for the FPGA Placement Problem. ERSA Luke Terry, Vladimir Roitch, Shoeb Tufail, Kirit Singh, Omair Taraq, Wayne Luk, Peter Jamieson
2009	J	`jnl`	Hierarchical Segmentation for Hardware Function Evaluation. IEEE Trans. Very Large Scale Integr. Syst. Dong-U Lee, Ray C. C. Cheung, Wayne Luk, John D. Villasenor
2009	J	`jnl`	High-throughput one-dimensional median and weighted median filters on FPGA. IET Comput. Digit. Tech. Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk
2009	B	`conf`	Modeling post-techmapping and post-clustering FPGA circuit depth. FPL Joydip Das, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk
2009	—	`conf`	NeMo: A Platform for Neural Modelling of Spiking Neurons Using GPUs. ASAP Andreas Fidjeland, Etienne B. Roesch, Murray Shanahan, Wayne Luk
2009	B	`conf`	Optimising designs by combining model-based and pattern-based transformations. FPL Qiang Liu, Tim Todman, José Gabriel de Figueiredo Coutinho, Wayne Luk, George A. Constantinides
2009	—	`conf`	Parametric Design for Reconfigurable Software-Defined Radio. ARC Tobias Becker, Wayne Luk, Peter Y. K. Cheung
2009	A	`conf`	Partition-based exploration for reconfigurable JPEG designs. DATE Philip G. Potter, Wayne Luk, Peter Y. K. Cheung
2009	—	`conf`	Tuning instruction customisation for reconfigurable system-on-chip. SoCC Chun Hok Ho, Wayne Luk, Jakub Szefer, Ruby B. Lee
2008	—	`conf`	A Customisable Multiprocessor for Application-Optimised Inductive Logic Programming. BCS Int. Acad. Conf. Andreas Fidjeland, Wayne Luk, Stephen H. Muggleton
2008	J	`jnl`	A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications. ACM Trans. Reconfigurable Technol. Syst. Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk
2008	B	`conf`	A hardware compilation flow for instance-specific VLIW cores. FPL Markus Koester, Wayne Luk, Geoffrey Brown
2008	—	`conf`	An FPGA run-time parameterisable Log-Normal Random Number Generator. ARC Pedro Echeverría, David B. Thomas, Marisa López-Vallejo, Wayne Luk
2008	—	`conf`	An Overview of Low-Power Techniques for Field-Programmable Gate Arrays. AHS Julien Lamoureux, Wayne Luk
2008	B	`conf`	An analytical model describing the relationships between logic architecture and FPGA density. FPL Andrew Lam, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk
2008	J	`jnl`	CHIPS: Custom Hardware Instruction Processor Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kubilay Atasu, Can C. Özturan, Günhan Dündar, Oskar Mencer, Wayne Luk
2008	Misc	`conf`	Credit Risk Modelling using Hardware Accelerated Monte-Carlo Simulation. FCCM David B. Thomas, Wayne Luk
2008	J	`jnl`	Custom parallel caching schemes for hardware-accelerated image compression. J. Real Time Image Process. Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung
2008	—	`conf`	Estimation of sample mean and variance for Monte-Carlo simulations. FPT David B. Thomas, Wayne Luk
2008	—	`conf`	Exploring Reconfigurable Architectures for Binomial-Tree Pricing Models. ARC Qiwei Jin, David B. Thomas, Wayne Luk, Benjamin Cope
2008	A	`conf`	FPGA-optimised high-quality uniform random number generators. FPGA David B. Thomas, Wayne Luk
2008	—	`conf`	Fast custom instruction identification by convex subgraph enumeration. ASAP Kubilay Atasu, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar
2008	—	`conf`	Global interconnections in FPGAs: modeling and performance analysis. SLIP Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk
2008	J	`jnl`	Guest Editorial: 20 Years of ASAP. J. Signal Process. Syst. Wayne Luk, Yvon Savaria, Oskar Mencer
2008	J	`jnl`	Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations. IEEE Trans. Computers Dong-U Lee, Ray C. C. Cheung, Wayne Luk, John D. Villasenor
2008	A	`conf`	High-throughput interconnect wave-pipelining for global communication in FPGAs. FPGA Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2008	—	`conf`	Implementation of Wave-Pipelined Interconnects in FPGAs. NOCS Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk
2008	—	`conf`	Interconnection lengths and delays estimation for communication links in FPGAs. SLIP Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2008	J	`jnl`	Introduction. ACM Trans. Reconfigurable Technol. Syst. Duncan A. Buell, Wayne Luk
2008	B	`conf`	Mapping and scheduling with task clustering for heterogeneous computing systems. FPL Yuet Ming Lam, José Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai Leong
2008	J	`jnl`	Multivariate Gaussian Random Number Generation Targeting Reconfigurable Hardware. ACM Trans. Reconfigurable Technol. Syst. David B. Thomas, Wayne Luk
2008	—	`conf`	Optimizing coarse-grained units in floating point hybrid FPGA. FPT Chi Wai Yu, Alastair M. Smith, Wayne Luk, Philip Heng Wai Leong, Steven J. E. Wilton
2008	—	`conf`	Optimizing residue arithmetic on FPGAs. FPT Haohuan Fu, Oskar Mencer, Wayne Luk
2008	Misc	`conf`	Power-Aware and Branch-Aware Word-Length Optimization. FCCM William George Osborne, José Gabriel F. Coutinho, Wayne Luk, Oskar Mencer
2008	B	`conf`	Rapid estimation of power consumption for hybrid FPGAs. FPL Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton
2008	J	`jnl`	Reconfigurable Architecture for Network Flow Analysis. IEEE Trans. Very Large Scale Integr. Syst. Sherif Yusuf, Wayne Luk, Morris Sloman, Naranker Dulay, Emil C. Lupu, Geoffrey Brown
2008	—	`conf`	Reconfigurable acceleration of microphone array algorithms for speech enhancement. ASAP Ka Fai Cedric Yiu, Chun Hok Ho, Nedelko Grbic, Yao Lu, Xiaoxiang Shi, Wayne Luk
2008	—	`conf`	Reconfigurable design with clock gating. ICSAMOS William George Osborne, Wayne Luk, José Gabriel F. Coutinho, Oskar Mencer
2008	—	`conf`	Resource efficient generators for the floating-point uniform and exponential distributions. ASAP David B. Thomas, Wayne Luk
2008	B	`conf`	Sampling from the exponential distribution using independent Bernoulli variates. FPL David B. Thomas, Wayne Luk
2008	—	`conf`	Smart Enumeration: A Systematic Approach to Exhaustive Search. PATMOS Tim Todman, Haohuan Fu, Brittle Tsoi, Oskar Mencer, Wayne Luk
2008	—	`conf`	Systematic design space exploration for customisable multi-processor architectures. ICSAMOS Ben Cope, Peter Y. K. Cheung, Wayne Luk
2008	J	`jnl`	The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units. Int. J. Reconfigurable Comput. Chi Wai Yu, Julien Lamoureux, Steven J. E. Wilton, Philip Heng Wai Leong, Wayne Luk
2008	B	`conf`	Towards benchmarking energy efficiency of reconfigurable architectures. FPL Tobias Becker, Peter Jamieson, Wayne Luk, Peter Y. K. Cheung, Tero Rissa
2008	—	`conf`	Unrolling-based loop mapping and scheduling. FPT Yuet Ming Lam, José Gabriel F. Coutinho, Wayne Luk, Philip Heng Wai Leong
2008	A	`conf`	Using Reconfigurable Logic to Optimise GPU Memory Accesses. DATE Ben Cope, Peter Y. K. Cheung, Wayne Luk
2008	—	`conf`	Wave-pipelined signaling for on-FPGA communication. FPT Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2007	—	`conf`	A Domain Specific Language for Reconfigurable Path-based Monte Carlo Simulations. FPT David B. Thomas, Wayne Luk
2007	—	`conf`	A Hybrid Analog-Digital Routing Network for NoC Dynamic Routing. NOCS Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam
2007	Misc	`conf`	A Hybrid Memory Sub-system for Video Coding Applications. FCCM Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung
2007	A	`conf`	A synthesizable datapath-oriented embedded FPGA fabric. FPGA Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton
2007	B	`conf`	Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems. FPL William George Osborne, Ray C. C. Cheung, José Gabriel F. Coutinho, Wayne Luk, Oskar Mencer
2007	—	`conf`	Automatic Generation and Optimisation of Reconfigurable Financial Monte-Carlo Simulations. ASAP David B. Thomas, Jacob A. Bower, Wayne Luk
2007	—	`conf`	Bridging the Gap between FPGAs and Multi-Processor Architectures: A Video Processing Perspective. ASAP Ben Cope, Peter Y. K. Cheung, Wayne Luk
2007	J	`jnl`	Designing a Posture Analysis System with Hardware Implementation. J. VLSI Signal Process. José Gabriel F. Coutinho, M. P. T. Juvonen, J. L. Wang, Benny Lo, Wayne Luk, Oskar Mencer, Guang-Zhong Yang
2007	—	`conf`	Domain Specific Transformations for Hardware Ray Tracing. CPA Tim Todman, Wayne Luk
2007	B	`conf`	Domain-Specific Hybrid FPGA: Architecture and Floating Point Applications. FPL Chun Hok Ho, Chi Wai Yu, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton
2007	Misc	`conf`	Enhancing Relocatability of Partial Bitstreams for Run-Time Reconfiguration. FCCM Tobias Becker, Wayne Luk, Peter Y. K. Cheung
2007	J	`jnl`	Evaluation of SystemC Modelling of Reconfigurable Embedded Systems CoRR Tero Rissa, Adam Donlin, Wayne Luk
2007	—	`conf`	FPGA-based Streaming Computation for Lattice Boltzmann Method. FPT Kentaro Sano, Oliver Pell, Wayne Luk, Satoru Yamamoto
2007	J	`jnl`	Gaussian random number generators. ACM Comput. Surv. David B. Thomas, Wayne Luk, Philip Heng Wai Leong, John D. Villasenor
2007	J	`jnl`	Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method. IEEE Trans. Very Large Scale Integr. Syst. Ray C. C. Cheung, Dong-U Lee, Wayne Luk, John D. Villasenor
2007	J	`jnl`	High Quality Uniform Random Number Generation Using LUT Optimised State-transition Matrices. J. VLSI Signal Process. David B. Thomas, Wayne Luk
2007	J	`jnl`	High-Performance Embedded Architecture and Compilation Roadmap. Trans. High Perform. Embed. Archit. Compil. Koen De Bosschere, Wayne Luk, Xavier Martorell, Nacho Navarro, Michael F. P. O'Boyle, Dionisios N. Pnevmatikatos, Alex Ramírez, Pascal Sainrat, André Seznec, Per Stenström, Olivier Temam
2007	—	`conf`	Improving Bounds for FPGA Logic Minimization. FPT Tim Todman, Haofan Fu, Oskar Mencer, Wayne Luk
2007	—	`conf`	Instrumented Multi-Stage Word-Length Optimization. FPT William George Osborne, José Gabriel F. Coutinho, Ray C. C. Cheung, Wayne Luk, Oskar Mencer
2007	J	`jnl`	Non-uniform random number generation through piecewise linear approximations. IET Comput. Digit. Tech. David B. Thomas, Wayne Luk
2007	Misc	`conf`	Optimizing Logarithmic Arithmetic on FPGAs. FCCM Haohuan Fu, Oskar Mencer, Wayne Luk
2007	A	`conf`	Optimizing instruction-set extensible processors under data bandwidth constraints. DATE Kubilay Atasu, Robert G. Dimond, Oskar Mencer, Wayne Luk, Can C. Özturan, Günhan Dündar
2007	J	`jnl`	Real-time hardware acceleration of the trace transform. J. Real Time Image Process. Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk
2007	—	`conf`	Reconfigurable Hardware Acceleration of Canonical Graph Labelling. ARC David B. Thomas, Wayne Luk, Michael Stumpf
2007	J	`jnl`	Run-Time Integration of Reconfigurable Video Processing Systems. IEEE Trans. Very Large Scale Integr. Syst. N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2007	Misc	`conf`	Sampling from the Multivariate Gaussian Distribution using Reconfigurable Hardware. FCCM David B. Thomas, Wayne Luk
2007	—	`conf`	Unifying FPGA Hardware Development. FPT Jacob A. Bower, Wei Ning Cho, Wayne Luk
2006	—	`conf`	A Flexible Multi-port Caching Scheme for Reconfigurable Platforms. ARC Su-Shin Ang, George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2006	J	`jnl`	A Hardware Gaussian Noise Generator Using the Box-Muller Method and Its Error Analysis. IEEE Trans. Computers Dong-U Lee, John D. Villasenor, Wayne Luk, Philip Heng Wai Leong
2006	—	`conf`	A Reconfigurable Simulation Framework for Financial Computation. ReConFig Jacob A. Bower, David B. Thomas, Wayne Luk, Oskar Mencer
2006	J	`jnl`	Accuracy-Guaranteed Bit-Width Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dong-U Lee, Altaf Abdul Gaffar, Ray C. C. Cheung, Oskar Mencer, Wayne Luk, George A. Constantinides
2006	—	`conf`	An FPGA implementation of the simplex algorithm. FPT Samuel Bayliss, Christos-Savvas Bouganis, George A. Constantinides, Wayne Luk
2006	B	`conf`	Archlog: High-Level Synthesis of Reconfigurable Multiprocessors for Logic Programming. FPL Andreas Fidjeland, Wayne Luk
2006	A	`conf`	Automating processor customisation: optimised memory access and resource sharing. DATE Robert G. Dimond, Oskar Mencer, Wayne Luk
2006	Misc	`conf`	Combining Instruction Coding and Scheduling to Optimize Energy in System-on-FPGA. FCCM Robert G. Dimond, Oskar Mencer, Wayne Luk
2006	—	`conf`	Comparing floating-point and logarithmic number representations for reconfigurable acceleration. FPT Haohuan Fu, Oskar Mencer, Wayne Luk
2006	B	`conf`	Compiling Higher-Order Polymorphic Hardware Descriptions Into Parametrised VHDL Libraries with Flexible Placement Information. FPL Oliver Pell, Wayne Luk
2006	J	`jnl`	Dynamic clock-frequencies for FPGAs. Microprocess. Microsystems Jacob A. Bower, Wayne Luk, Oskar Mencer, Michael J. Flynn, Martin Morf
2006	Misc	`conf`	Efficient Hardware Generation of Random Variates with Arbitrary Distributions. FCCM David B. Thomas, Wayne Luk
2006	B	`conf`	Efficient Realtime FPGA Implementation of the Trace Transform. FPL Suhaib A. Fahmy, Christos-Savvas Bouganis, Peter Y. K. Cheung, Wayne Luk
2006	Misc	`conf`	Generating Parametrised Hardware Libraries from Higher-Order Descriptions. FCCM Oliver Pell, Wayne Luk
2006	—	`conf`	Hardware architectures for Monte-Carlo based financial simulations. FPT David B. Thomas, Jacob A. Bower, Wayne Luk
2006	Misc	`conf`	Incremental elaboration for run-time reconfigurable hardware designs. CASES Arran Derbyshire, Tobias Becker, Wayne Luk
2006	—	`conf`	Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation. FPT Dong-U Lee, Ray C. C. Cheung, John D. Villasenor, Wayne Luk
2006	B	`conf`	Non-Uniform Random Number Generation Through Piecewise Linear Approximations. FPL David B. Thomas, Wayne Luk
2006	—	`conf`	On-Chip Communication in Run-Time Assembled Reconfigurable Systems. ICSAMOS N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2006	B	`conf`	On-FPGA Communication Architectures and Design Factors. FPL Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk
2006	J	`jnl`	Provably-correct hardware compilation tools based on pass separation techniques. Formal Aspects Comput. Steve McKeever, Wayne Luk
2006	—	`conf`	Reconfigurable Acceleration of Robust Frequency-Domain Echo Cancellation. ERSA Chun Hok Ho, Ka Fai Cedric Yiu, Jiaquan Huo, Sven Nordholm, Wayne Luk
2006	—	`conf`	The cost of data dependence in motion vector estimation for reconfigurable platforms. FPT Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung
2006	—	`conf`	Towards optimal custom instruction processors. Hot Chips Symposium Wayne Luk, Kubilay Atasu, Robert G. Dimond, Oskar Mencer
2006	—	`conf`	UNITE: Uniform Hardware-Based Network Intrusion deTection Engine. ARC Sherif Yusuf, Wayne Luk, M. K. N. Szeto, William George Osborne
2006	Misc	`conf`	Virtual Embedded Blocks: A Methodology for Evaluating Embedded Elements in FPGAs. FCCM Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton, Sergio López-Buedo
2005	—	`conf`	A Combined Hardware-Software Architecture for Network Flow. ERSA Wayne Luk, Sherif Yusuf, Morris Sloman, Geoffrey Brown, Emil C. Lupu, Naranker Dulay
2005	J	`jnl`	A hardware Gaussian noise generator using the Wallace method. IEEE Trans. Very Large Scale Integr. Syst. Dong-U Lee, Wayne Luk, John D. Villasenor, Guanglie Zhang, Philip Heng Wai Leong
2005	—	`conf`	An Overview of High-Level Synthesis of Multiprocessors for Logic Programming. FPT Andreas Fidjeland, Wayne Luk
2005	Misc	`conf`	Automating custom-precision function evaluation for embedded processors. CASES Ray C. C. Cheung, Dong-U Lee, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung
2005	B	`conf`	Bitwise Optimised CAM for Network Intrusion Detection Systems. FPL Sherif Yusuf, Wayne Luk
2005	B	`conf`	CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools. FPL Robert G. Dimond, Oskar Mencer, Wayne Luk
2005	—	`conf`	Cell Based Motion Estimators for Reconfigurable Platforms. ERSA Wim J. C. Melis, Kieron Turkington, Alexander Whitton, Wayne Luk, Peter Y. K. Cheung, Paul Metzgen
2005	B	`conf`	Compilation and Management of Phase-Optimized Reconfigurable Systems. FPL Henry Styles, Wayne Luk
2005	—	`conf`	Custom Hardware Architectures for Posture Analysis. FPT M. P. T. Juvonen, José Gabriel F. Coutinho, J. L. Wang, Benny Lo, Wayne Luk, Oskar Mencer, Guang-Zhong Yang
2005	J	`jnl`	Customisable Hardware Compilation. J. Supercomput. Tim Todman, José Gabriel F. Coutinho, Wayne Luk
2005	—	`conf`	Customising Application-Speci.c Multiprocessor Systems: a Case Study. ASAP Andreas Fidjeland, Wayne Luk
2005	J	`jnl`	Customizable elliptic curve cryptosystems. IEEE Trans. Very Large Scale Integr. Syst. Ray C. C. Cheung, N. J. Telle, Wayne Luk, Peter Y. K. Cheung
2005	—	`conf`	Dynamic Voltage Scaling for Commercial FPGAs. FPT Gary Chun Tak Chow, L. S. M. Tsui, Philip Heng Wai Leong, Wayne Luk, Steven J. E. Wilton
2005	A	`conf`	Hardware Acceleration of Hidden Markov Model Decoding for Person Detection. DATE Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk
2005	J	`jnl`	Hardware/software codesign: a systematic approach targeting data-intensive applications. IEEE Signal Process. Mag. Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
2005	—	`conf`	Have GPUs Made FPGAs Redundant in the Field of Video Processing? FPT Ben Cope, Peter Y. K. Cheung, Wayne Luk, Sarah Witt
2005	—	`conf`	High Quality Uniform Random Number Generation Through LUT Optimised Linear Recurrences. FPT David B. Thomas, Wayne Luk
2005	—	`conf`	High quality uniform random number generation for massively parallel simulations in FPGA. ReConFig David B. Thomas, Wayne Luk
2005	Misc	`conf`	Interleaving Behavioral and Cycle-Accurate Descriptions for Reconfigurable Hardware Compilation. FCCM José Gabriel F. Coutinho, Jun Jiang, Wayne Luk
2005	A*	`conf`	MiniBit: bit-width optimization via affine arithmetic. DAC Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk
2005	B	`conf`	Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing. FPL Suhaib A. Fahmy, Peter Y. K. Cheung, Wayne Luk
2005	J	`jnl`	Optimizing Hardware Function Evaluation. IEEE Trans. Computers Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk
2005	J	`jnl`	Optimum and heuristic synthesis of multiple word-length architectures. IEEE Trans. Very Large Scale Integr. Syst. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2005	—	`conf`	Quartz: a framework for correct and efficient reconfigurable design. ReConFig Oliver Pell, Wayne Luk
2005	—	`conf`	Reconfigurable Acceleration for Monte Carlo Based Financial Simulation. FPT Guanglie Zhang, Philip Heng Wai Leong, Chun Hok Ho, Kuen Hung Tsoi, Chris C. C. Cheung, Dong-U Lee, Ray C. C. Cheung, Wayne Luk
2005	Misc	`conf`	Reconfigurable Designs for Radiosity. FCCM Paul Baker, Tim Todman, Henry Styles, Wayne Luk
2005	A	`conf`	Reconfigurable Elliptic Curve Cryptosystems on a Chip. DATE Ray C. C. Cheung, Wayne Luk, Peter Y. K. Cheung
2005	—	`conf`	Resolving Quartz Overloading. CHARME Oliver Pell, Wayne Luk
2005	B	`conf`	Ziggurat-based Hardware Gaussian Random Number Generator. FPL Guanglie Zhang, Philip Heng Wai Leong, Dong-U Lee, John D. Villasenor, Ray C. C. Cheung, Wayne Luk
2004	Misc	`conf`	A Flexible Hardware Encoder for Low-Density Parity-Check Codes. FCCM Dong-U Lee, Wayne Luk, Connie Wang, Christopher R. Jones, Michael Smith, John D. Villasenor
2004	J	`jnl`	A Gaussian Noise Generator for Hardware-Based Simulations. IEEE Trans. Computers Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
2004	B	`conf`	A Structured Methodology for System-on-an-FPGA Design. FPL N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2004	Misc	`conf`	A Structured System Methodology for FPGA Based System-on-A-Chip Design. FCCM N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2004	—	`conf`	A scalable hardware architecture for prime number validation. FPT Ray C. C. Cheung, Ashley Brown, Wayne Luk, Peter Y. K. Cheung
2004	—	`conf`	Adaptive range reduction for hardware function evaluation. FPT Dong-U Lee, Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk
2004	B	`conf`	Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs. FPL Dong-U Lee, Oskar Mencer, David J. Pearce, Wayne Luk
2004	—	`conf`	Autonomous Memory Block for reconfigurable computing. ISCAS (2) Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk
2004	A	`conf`	Customisable EPIC Processor: Architecture and Tools. DATE W. W. S. Chu, Robert G. Dimond, S. Perrott, S. P. Seng, Wayne Luk
2004	—	`conf`	Customisable Hardware Compilation. ERSA Tim Todman, José Gabriel F. Coutinho, Wayne Luk
2004	—	`conf`	Customising Hardware Designs for Elliptic Curve Cryptography. SAMOS Nicolas Telle, Wayne Luk, Ray C. C. Cheung
2004	—	`conf`	Customising Processors: Design-Time and Run-Time Opportunities. SAMOS Wayne Luk
2004	—	`conf`	Distinguished Paper: Automated Combination of Simulation and Hardware Prototyping. ERSA Tero Rissa, Wayne Luk, Peter Y. K. Cheung
2004	A	`conf`	Evaluation of SystemC Modelling of Reconfigurable Embedded Systems. DATE Tero Rissa, Adam Donlin, Wayne Luk
2004	J	`jnl`	Exploiting Program Branch Probabilities in Hardware Compilation. IEEE Trans. Computers Henry Styles, Wayne Luk
2004	B	`conf`	Implementing Graphics Shaders Using FPGAs. FPL David B. Thomas, Wayne Luk
2004	—	`conf`	Memory optimisations for high-resolution imaging. FPT Tim Todman, Wayne Luk
2004	B	`conf`	Methods and Tools for High-Resolution Imaging. FPL Tim Todman, Wayne Luk
2004	J	`jnl`	Parameterized High Throughput Function Evaluation for FPGAs. J. VLSI Signal Process. Oskar Mencer, Wayne Luk
2004	—	`conf`	Pipelining designs with loop-carried dependencies. FPT Henry Styles, David B. Thomas, Wayne Luk
2004	—	`conf`	Reduction of design complexity using virtual hardware platforms. SoC Tero Rissa, Wayne Luk
2004	—	`conf`	Scalable structured data access by combining autonomous memory blocks. FPT Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk
2004	B	`conf`	SoftSONIC: A Customisable Modular Platform for Video Applications. FPL Tero Rissa, Peter Y. K. Cheung, Wayne Luk
2004	—	`book`	Synthesis and optimization of DSP algorithms. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2004	B	`conf`	The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays. FPL Steven J. E. Wilton, Su-Shin Ang, Wayne Luk
2004	Misc	`conf`	Unifying Bit-Width Optimisation for Fixed-Point and Floating-Point Designs. FCCM Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung
2003	Misc	`conf`	A Hardware Gaussian Noise Generator for Channel Code Evaluation. FCCM Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
2003	B	`conf`	A Reconfigurable Platform for Real-Time Embedded Video Image Processing. FPL N. Pete Sedcole, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk
2003	B	`conf`	A Unified Codesign Run-Time Environment for the UltraSONIC Reconfigurable Computer. FPL Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
2003	B	`conf`	Branch Optimisation Techniques for Hardware Compilation. FPL Henry Styles, Wayne Luk
2003	B	`conf`	Cluster-Driven Hardware/Software Partitioning and Scheduling Approach for a Reconfigurable Computer System. FPL Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
2003	—	`conf`	Combining Imperative and Declarative Hardware Descriptions. HICSS Tim Todman, Wayne Luk
2003	Misc	`conf`	Compiling Policy Descriptions into Reconfigurable Firewall Processors. FCCM T. K. Lee, Sherif Yusuf, Wayne Luk, Morris Sloman, Emil Lupu, Naranker Dulay
2003	—	`conf`	Customising parallelism and caching for machine learning. FPT Andreas Fidjeland, Wayne Luk
2003	—	`conf`	Design space exploration with A Stream Compiler. FPT Oskar Mencer, David J. Pearce, Lee W. Howes, Wayne Luk
2003	B	`conf`	FPGA-Based Computation of Free-Form Deformations. FPL Jun Jiang, Wayne Luk, Daniel Rueckert
2003	—	`conf`	FPGA-based computation of free-form deformations in medical image registration. FPT Jun Jiang, Wayne Luk, Daniel Rueckert
2003	B	`conf`	Hardware Design with a Scripting Language. FPL Per Haglund, Oskar Mencer, Wayne Luk, Benjamin Tai
2003	—	`conf`	Hierarchical segmentation schemes for function evaluation. FPT Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
2003	—	`conf`	High-level language extensions for run-time reconfigurable systems. FPT T. K. Lee, Arran Derbyshire, Wayne Luk, Peter Y. K. Cheung
2003	B	`conf`	Irregular Reconfigurable CAM Structures for Firewall Applications. FPL T. K. Lee, Sherif Yusuf, Wayne Luk, Morris Sloman, Emil Lupu, Naranker Dulay
2003	—	`conf`	Multitasking in hardware-software codesign for reconfigurable computer. ISCAS (5) Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
2003	B	`conf`	Non-uniform Segmentation for Hardware Function Evaluation. FPL Dong-U Lee, Wayne Luk, John D. Villasenor, Peter Y. K. Cheung
2003	—	`conf`	PyHDL: Hardware Scripting with Python. Engineering of Reconfigurable Systems and Algorithms Per Haglund, Oskar Mencer, Wayne Luk, Benjamin Tai
2003	Misc	`conf`	Real-time Extensions to a C-like Hardware Description Language. FCCM Tim Todman, Wayne Luk
2003	—	`conf`	Source-directed transformations for hardware compilation. FPT José Gabriel F. Coutinho, Wayne Luk
2003	J	`jnl`	Synthesis of saturation arithmetic architectures. ACM Trans. Design Autom. Electr. Syst. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2003	—	`conf`	Towards Verifying Parametrised Hardware Libraries with Relative Placement Information. HICSS Steve McKeever, Wayne Luk, Arran Derbyshire
2003	J	`jnl`	Wordlength optimization for linear digital signal processing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2002	Misc	`conf`	Accelerating Radiosity Calculations Using Reconfigurable Platforms. FCCM Henry Styles, Wayne Luk
2002	B	`conf`	Automating Customisation of Floating-Point Designs. FPL Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi, James Hwang
2002	J	`jnl`	Comparing Three Heuristic Search Methods for Functional Partitioning in Hardware-Software Codesign. Des. Autom. Embed. Syst. Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
2002	B	`conf`	Compiling Hardware Descriptions with Relative Placement Information for Parametrised Libraries. FMCAD Steve McKeever, Wayne Luk, Arran Derbyshire
2002	—	`conf`	Compiling run-time parametrisable designs. FPT Arran Derbyshire, Wayne Luk
2002	Misc	`conf`	Customising Floating-Point Designs. FCCM Altaf Abdul Gaffar, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi
2002	—	`conf`	Development framework for firewall processors. FPT T. K. Lee, Sherif Yusuf, Wayne Luk, Morris Sloman, Emil Lupu, Naranker Dulay
2002	—	`conf`	FPGA-based computation of free-form deformations. FPT Jun Jiang, Wayne Luk, Daniel Rueckert
2002	—	`conf`	Floating-point bitwidth analysis via automatic differentiation. FPT Altaf Abdul Gaffar, Oskar Mencer, Wayne Luk, Peter Y. K. Cheung, Nabeel Shirazi
2002	B	`conf`	Image Registration of Real-Time Broadcast Video Using the UltraSONIC Reconfigurable Computer. FPL Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk
2002	Misc	`conf`	Image Registration of Real-Time Video Data Using the SONIC Reconfigurable Computer Platform. FCCM Wim J. C. Melis, Peter Y. K. Cheung, Wayne Luk
2002	—	`conf`	Incremental programming for reconfigurable engines. FPT Dong-U Lee, T. K. Lee, Wayne Luk, Peter Y. K. Cheung
2002	—	`conf`	Optimising and adapting high-level hardware designs. FPT José Gabriel F. Coutinho, Wayne Luk
2002	Misc	`conf`	Optimum Wordlength Allocation. FCCM George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2002	—	`conf`	PD-XML: extensible markup language for processor description. FPT Shay Ping Seng, Krishna V. Palem, Rodric M. Rabbah, Weng-Fai Wong, Wayne Luk, Peter Y. K. Cheung
2002	Misc	`conf`	Reconfigurable Shape-Adaptive Template Matching Architectures. FCCM Jörn Gause, Peter Y. K. Cheung, Wayne Luk
2002	B	`conf`	Run-Time Adaptive Flexible Instruction Processors. FPL Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung
2002	—	`conf`	Scalable acceleration of inductive logic programs. FPT Andreas Fidjeland, Wayne Luk, Stephen H. Muggleton
2002	—	`conf`	Strassen's matrix multiplication for customisable processors. FPT Henry M. D. Ip, James D. Low, Peter Y. K. Cheung, George A. Constantinides, Wayne Luk, Shay Ping Seng, Paul Metzgen
2002	Misc	`conf`	Tabu Search with Intensification Strategy for Functional Partitioning in Hardware-Software Codesign. FCCM Theerayod Wiangtong, Peter Y. K. Cheung, Wayne Luk
2001	B	`conf`	A Digit-Serial Structure for Reconfigurable Multipliers. FPL Chakkapas Visavakul, Peter Y. K. Cheung, Wayne Luk
2001	—	`conf`	A declarative framework for developing parametrised hardware libraries. ICECS Steve McKeever, Wayne Luk
2001	J	`jnl`	An integrated system for developing regular array designs. J. Syst. Archit. Shaori Guo, Wayne Luk
2001	A	`conf`	Heuristic datapath allocation for multiple wordlength systems. DATE George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2001	Misc	`conf`	Parameterised floating-point arithmetic on FPGAs. ICASSP Allan Jaenicke, Wayne Luk
2001	B	`conf`	Parameterized Function Evaluation for FPGAs. FPL Oskar Mencer, Nicolas Boullis, Wayne Luk, Henry Styles
2001	J	`jnl`	Pipeline vectorization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Markus Weinhardt, Wayne Luk
2001	Misc	`conf`	Pipelined Function Evaluation on FPGAs. FCCM Nicolas Boullis, Oskar Mencer, Wayne Luk, Henry Styles
2001	J	`jnl`	Quantitative Analysis of FPGA-based Database Searching. J. VLSI Signal Process. Nabeel Shirazi, Dan Benyamin, Wayne Luk, Peter Y. K. Cheung, Shaori Guo
2001	Misc	`conf`	Reconfigurable Designs for Ray Tracing. FCCM Tim Todman, Wayne Luk
2001	B	`conf`	Task-Parallel Programming of Reconfigurable Systems. FPL Markus Weinhardt, Wayne Luk
2001	Misc	`conf`	The Effect of FPGA Granularity on Video Codec Implementations. FCCM Jörn Gause, Carsten Reuter, Holger Kropp, Peter Y. K. Cheung, Wayne Luk
2001	Misc	`conf`	The Multiple Wordlength Paradigm. FCCM George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2001	—	`conf`	Towards Provably-Correct Hardware Compilation Tools Based on Pass Separation Techniques. CHARME Steve McKeever, Wayne Luk
2000	B	`conf`	A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems. FPL Xue-Jie Zhang, Kam-Wing Ng, Wayne Luk
2000	B	`conf`	Combining Serialisation and Reconfiguration for FPGA Designs. FPL Arran Derbyshire, Wayne Luk
2000	Misc	`conf`	Combining Serialization and Reconfiguration for Convolver Designs. FCCM Arran Derbyshire, Wayne Luk
2000	Misc	`conf`	Customizing Graphics Applications: Techniques and Programming Interface. FCCM Henry Styles, Wayne Luk
2000	Misc	`conf`	Evaluating Hardware Compilation Techniques. FCCM Markus Weinhardt, Wayne Luk
2000	Misc	`conf`	Flexible instruction processors. CASES Shay Ping Seng, Wayne Luk, Peter Y. K. Cheung
2000	J	`jnl`	Guest Editors' Introduction. J. VLSI Signal Process. Jeffrey Arnold, Wayne Luk, Ken Pocek
2000	Misc	`conf`	Multiple Precision for Resource Minimization. FCCM George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2000	B	`conf`	Multiple-Wordlength Resource Binding. FPL George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2000	C	`conf`	Roundoff-noise shaping in filter design. ISCAS George A. Constantinides, Peter Y. K. Cheung, Wayne Luk
2000	B	`conf`	Static and Dynamic Reconfigurable Designs for a 2D Shape-Adaptive DCT. FPL Jörn Gause, Peter Y. K. Cheung, Wayne Luk
2000	J	`jnl`	Video Image Processing with the Sonic Architecture. Computer Simon D. Haynes, John Stone, Peter Y. K. Cheung, Wayne Luk
1999	B	`conf`	Memory Access Optimization and RAM Inference for Pipeline Vectorization. FPL Markus Weinhardt, Wayne Luk
1999	Misc	`conf`	Optimizing FPGA-Based Vector Product Designs. FCCM Dan Benyamin, John D. Villasenor, Wayne Luk
1999	Misc	`conf`	Pipeline Vectorization for Reconfigurable Systems. FCCM Markus Weinhardt, Wayne Luk
1999	B	`conf`	Quantitative Analysis of Run-Time Reconfigurable Database Search. FPL Nabeel Shirazi, Wayne Luk, Dan Benyamin, Peter Y. K. Cheung
1999	Misc	`conf`	Reconfigurable Computing for Augmented Reality. FCCM Wayne Luk, T. K. Lee, J. Rice, Nabeel Shirazi, Peter Y. K. Cheung
1999	Misc	`conf`	SONIC - A Plug-In Architecture for Video Processing. FCCM Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone
1999	B	`conf`	SONIC - A Plug-In Architecture for Video Processing. FPL Simon D. Haynes, Peter Y. K. Cheung, Wayne Luk, John Stone
1999	B	`conf`	Serial Hardware Libraries for Reconfigurable Designs. FPL Wayne Luk, Arran Derbyshire, Shaori Guo, D. Siganos
1999	A	`conf`	Towards Adaptable Hierarchical Placement for FPGAs. FPGA Florent de Dinechin, Wayne Luk, Steve McKeever
1998	B	`conf`	A Reconfigurable Engine for Real-Time Video Processing. FPL Wayne Luk, P. Andreou, Arran Derbyshire, Florent Dupont de Dinechin, J. Rice, Nabeel Shirazi, D. Siganos
1998	Misc	`conf`	Automating Production of Run-Time Reconfigurable Designs. FCCM Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung
1998	B	`conf`	Pebble: A Language for Parametrised and Reconfigurable Hardware Design. FPL Wayne Luk, Steve McKeever
1998	B	`conf`	Run-Time Management of Dynamically Recongigurable Designs. FPL Nabeel Shirazi, Wayne Luk, Peter Y. K. Cheung
1997	B	`conf`	A reconfigurable data-localised array for morphological algorithms. FPL Anjit Sekhar Chaudhuri, Peter Y. K. Cheung, Wayne Luk
1997	Misc	`conf`	Compilation tools for run-time reconfigurable designs. FCCM Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung
1997	B	`ed.`	Field-Programmable Logic and Applications, 7th International Workshop, FPL '97, London, UK, September 1-3, 1997, Proceedings FPL Wayne Luk, Peter Y. K. Cheung, Manfred Glesner
1997	B	`conf`	Pipeline morphing and virtual pipelines. FPL Wayne Luk, Nabeel Shirazi, Shaori Guo, Peter Y. K. Cheung
1997	B	`conf`	Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research. FPL Patrick I. Mackinlay, Peter Y. K. Cheung, Wayne Luk, Richard Sandiford
1997	J	`jnl`	Verified Compilation of Communicating Processes into Clocked Circuits. Formal Aspects Comput. John O'Leary, Geoffrey Brown, Wayne Luk
1996	B	`conf`	A Framework for Developing Parameterised FPGA Libraries. FPL Wayne Luk, Shaori Guo, Nabeel Shirazi, N. Zhuang
1996	J	`jnl`	Binomial filters. J. VLSI Signal Process. Matthew Aubury, Wayne Luk
1996	J	`jnl`	Guest editors' introduction. J. VLSI Signal Process. Wayne Luk, Duncan A. Buell
1996	Misc	`conf`	Modelling and optimising run-time reconfigurable systems. FCCM Wayne Luk, Nabeel Shirazi, Peter Y. K. Cheung
1996	J	`jnl`	Retargeting a Hardware Compiler Using Protokol Converters. Formal Aspects Comput. Geoffrey Brown, Wayne Luk, John O'Leary
1995	Misc	`conf`	A declarative approach to incremental custom computing. FCCM Wayne Luk
1995	B	`conf`	Compiling Ruby into FPGAs. FPL Shaori Guo, Wayne Luk
1995	B	`ed.`	Field-Programmable Logic and Applications, 5th International Workshop, FPL '95, Oxford, UK, August 29 - September 1, 1995, Proceedings FPL Will Moore, Wayne Luk
1995	B	`conf`	Using Reconfigurable Hardware to Speed up Product Development and Performance. FPL Adrian Lawrence, Andrew Kay, Wayne Luk, Toshio Nomura, Ian Page
1994	B	`conf`	Constraint-based Hierarchical Placement of Parallel Programs. FPL Mat Newman, Wayne Luk, Ian Page
1994	A*	`conf`	Developing Parallel Architectures for Range and Image Sensors. ICRA Shaori Guo, Wayne Luk, Penelope Probert
1994	—	`conf`	Retargeting a hardware compiler proof using protocol converters. ASYNC Geoffrey Brown, Wayne Luk, John O'Leary
1994	—	`conf`	Towards a declarative framework for hardware-software codesign. CODES Wayne Luk, Teddy Wu
1993	J	`jnl`	Introduction. J. VLSI Signal Process. Will Moore, Wayne Luk
1990	J	`jnl`	A Systolic LRU Processor and Its Top-Down Development. Sci. Comput. Program. Wayne Luk, Geoffrey Brown
1990	—	`conf`	Analysing parametrised designs by non-standard interpretation. ASAP Wayne Luk