Wantong Li

26 papers A* 1A 2C 1Journal 9Unranked 13
YearRankTypeTitle / Venue / Authors
2025 A* conf
Folded Banks: 3D-Stacked HBM Design for Fine-Grained Random-Access Bandwidth.
ISCA
Vignesh Adhinarayanan, Bradford M. Beckmann, Wantong Li, Mohammad Seyedzadeh, Sergey Blagodurov, Derrick Aguren, Hayden Hyungdong Lee
2025 — conf
RandEye: On-Sensor Stochastic Image Transformation for Backdoor-Resistant Edge Inference.
ACM Great Lakes Symposium on VLSI
Wantong Li, Liuwan Zhu
2024 J jnl
NeuroSim V1.4: Extending Technology Support for Digital Compute-in-Memory Toward 1nm Node.
IEEE Trans. Circuits Syst. I Regul. Pap.
Junmo Lee, Anni Lu, Wantong Li, Shimeng Yu
2023 — conf
A Reconfigurable Monolithic 3D Switched-Capacitor DC-DC Converter with Back-End-of-Line Oxide Channel Transistor.
MWSCAS
Jungyoun Kwak, Wantong Li, Shimeng Yu
2023 J jnl
ENNA: An Efficient Neural Network Accelerator Design Based on ADC-Free Compute-In-Memory Subarrays.
IEEE Trans. Circuits Syst. I Regul. Pap.
Hongwu Jiang, Shanshi Huang, Wantong Li, Shimeng Yu
2023 C conf
Enabling Long-Term Robustness in RRAM-based Compute-In-Memory Edge Devices.
ISCAS
James Read, Wantong Li, Shimeng Yu
2023 — conf
Enabling Ultra-Low Power Ultrasound Imaging with Compute-in-Memory Sparse Reconstruction Accelerator.
BioCAS
Wantong Li, Xitie Zhang, Junmo Lee, F. Levent Degertekin, Shaolan Li, Shimeng Yu
2023 J jnl
H3DAtten: Heterogeneous 3-D Integrated Hybrid Analog and Digital Compute-in-Memory Accelerator for Vision Transformer Self-Attention.
IEEE Trans. Very Large Scale Integr. Syst.
Wantong Li, Madison Manley, James Read, Ankit Kaul, Muhannad S. Bakir, Shimeng Yu
2023 — conf
Optimization Strategies for Digital Compute-in-Memory from Comparative Analysis with Systolic Array.
AICAS
Wantong Li, Junmo Lee, Shimeng Yu
2023 A conf
RAWAtten: Reconfigurable Accelerator for Window Attention in Hierarchical Vision Transformers.
DATE
Wantong Li, Yandong Luo, Shimeng Yu
2023 J jnl
Temporal Frame Filtering for Autonomous Driving Using 3D-Stacked Global Shutter CIS With IWO Buffer Memory and Near-Pixel Compute.
IEEE Trans. Circuits Syst. I Regul. Pap.
Janak Sharda, Wantong Li, Qiucheng Wu, Shiyu Chang, Shimeng Yu
2022 J jnl
A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References.
IEEE J. Solid State Circuits
Wantong Li, Xiaoyu Sun, Shanshi Huang, Hongwu Jiang, Shimeng Yu
2022 — conf
A 40nm Analog-Input ADC-Free Compute-in-Memory RRAM Macro with Pulse-Width Modulation between Sub-arrays.
VLSI Technology and Circuits
Hongwu Jiang, Wantong Li, Shanshi Huang, Shimeng Yu
2022 — conf
A 40nm RRAM Compute-in-Memory Macro with Parallelism-Preserving ECC for Iso-Accuracy Voltage Scaling.
ESSCIRC
Wantong Li, James Read, Hongwu Jiang, Shimeng Yu
2022 — conf
A Method for Reverse Engineering Neural Network Parameters from Compute-in-Memory Accelerators.
ISVLSI
James Read, Wantong Li, Shimeng Yu
2022 J jnl
Analog-to-Digital Converter Design Exploration for Compute-in-Memory Accelerators.
IEEE Des. Test
Hongwu Jiang, Wantong Li, Shanshi Huang, Stefan Cosemans, Francky Catthoor, Shimeng Yu
2022 J jnl
MAC-ECC: In-Situ Error Correction and Its Design Methodology for Reliable NVM-Based Compute-in-Memory Inference Engine.
IEEE J. Emerg. Sel. Topics Circuits Syst.
Wantong Li, James Read, Hongwu Jiang, Shimeng Yu
2022 — conf
Temporal Frame Filtering with Near-Pixel Compute for Autonomous Driving.
AICAS
Wantong Li, Qiucheng Wu, Janak Sharda, Shiyu Chang, Shimeng Yu
2021 — conf
A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References.
ESSCIRC
Wantong Li, Xiaoyu Sun, Hongwu Jiang, Shanshi Huang, Shimeng Yu
2021 — conf
A 40nm RRAM Compute-in-Memory Macro Featuring On-Chip Write-Verify and Offset-Cancelling ADC References.
ESSDERC
Wantong Li, Xiaoyu Sun, Hongwu Jiang, Shanshi Huang, Shimeng Yu
2021 — conf
Compute-in-Memory: From Device Innovation to 3D System Integration.
ESSDERC
Shimeng Yu, Wonbo Shim, Jae Hur, Yuan-Chun Luo, Gihun Choe, Wantong Li, Anni Lu, Xiaochen Peng
2021 J jnl
NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and Benchmark.
Frontiers Artif. Intell.
Anni Lu, Xiaochen Peng, Wantong Li, Hongwu Jiang, Shimeng Yu
2021 — conf
NeuroSim Validation with 40nm RRAM Compute-in-Memory Macro.
AICAS
Anni Lu, Xiaochen Peng, Wantong Li, Hongwu Jiang, Shimeng Yu
2021 J jnl
Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption.
IEEE Trans. Very Large Scale Integr. Syst.
Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu
2021 — conf
Secure-RRAM: A 40nm 16kb Compute-in-Memory Macro with Reconfigurability, Sparsity Control, and Embedded Security.
CICC
Wantong Li, Shanshi Huang, Xiaoyu Sun, Hongwu Jiang, Shimeng Yu
2020 A conf
XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR Encryption.
ICCAD
Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu