Wangqi Qiu - RankMe

17 papers A* 1A 4Misc 3Journal 3Unranked 5

Year	Rank	Type	Title / Venue / Authors
2016	J	`jnl`	Macro Model of Advanced Devices for Parasitic Extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuhan Zhou, Yong Zhang, Vivek Sarin, Wangqi Qiu, Weiping Shi
2007	—	`—`	Fault simulation and test generation for small delay faults. Wangqi Qiu
2006	A	`conf`	Comparison of Delay Tests on Silicon. ITC Wangqi Qiu, D. M. H. Walker, Neil Simpson, Divya Reddy, Anthony Moore
2005	A	`conf`	A vector-based approach for power supply noise analysis in test compaction. ITC Jing Wang, Ziding Yue, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
2005	J	`jnl`	Longest-path selection for delay test under process variation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
2005	Misc	`conf`	Static Compaction of Delay Tests Considering Power Supply Noise. VTS Jing Wang, Xiang Lu, Wangqi Qiu, Ziding Yue, Steve Fancler, Weiping Shi, D. M. H. Walker
2004	—	`conf`	A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. MTV Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
2004	Misc	`conf`	A Statistical Fault Coverage Metric for Realistic Path Delay Faults. VTS Wangqi Qiu, Xiang Lu, Jing Wang, Zhuo Li, D. M. H. Walker, Weiping Shi
2004	A	`conf`	K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. ITC Wangqi Qiu, Jing Wang, D. M. H. Walker, Divya Reddy, Zhuo Li, Weiping Shi, Hari Balachandran
2004	—	`conf`	Longest path selection for delay test under process variation. ASP-DAC Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
2004	A*	`conf`	Minimum moment Steiner trees. SODA Wangqi Qiu, Weiping Shi
2004	—	`conf`	PARADE: PARAmetric Delay Evaluation under Process Variation. ISQED Xiang Lu, Zhuo Li, Wangqi Qiu, D. M. H. Walker, Weiping Shi
2003	Misc	`conf`	A Circuit Level Fault Model for Resistive Opens and Bridges. VTS Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
2003	J	`jnl`	A circuit level fault model for resistive bridges. ACM Trans. Design Autom. Electr. Syst. Zhuo Li, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker
2003	A	`conf`	An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit. ITC Wangqi Qiu, D. M. H. Walker
2003	—	`conf`	CodSim -- A Combined Delay Fault Simulator. DFT Wangqi Qiu, Xiang Lu, Zhuo Li, D. M. H. Walker, Weiping Shi
2003	—	`conf`	Testing the Path Delay Faults of ISCAS85 Circuit c6288. MTV Wangqi Qiu, D. M. H. Walker