Wanghua Wu - RankMe

20 papers Journal 9Unranked 11

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	34.2 Compact, Low-Power 60-and-77GHz 4T/4R Multi-Mode FMCW Radar RFICs in 28nm CMOS. ISSCC Byeong-Taek Moon, Mingyuan Li, Jun-Seuk Suh, Minseob Lee, Doyoon Kim, Kyunghwan Kim, Geonho Park, Goeun Baek, Byungho Yook, Dooseok Choi, Kyungwoo Yoo, Junseong Kim, Taewoo Yu, Seonghyeon Kang, Hyeonsu Jo, Juhee Son, Sangsung Lee, Pak-Kim Lau, Ivan Siu-Chuang Lu, Gregory Eric Rogers, Ajaypat Jain, Jian Wang, Viduneth Ariyarathna, Wan Jong Kim, Oren E. Eliezer, Gennady Feygin, Wen Zhou, Kyoung-Jun Moon, Jaehyun Chung, Woncheol Lee, Seongjung Kim, Jonghyun Kim, Joonggeun Lee, Taeyeon Kim, Sungjoo Kim, Youngki Lee, Yonghwan Harold Jang, Sai Krishna Rayudu, Shihchieh Chien, Ying Chen, Hyungsun Lim, Kidong Kang, Sungjun Lee, Joonhee Lee, Jeongyeol Bae, Hyun-Gi Seok, Pranav Dayal, Wanghua Wu, Hyun-Chul Park, Joonhoi Hur, Sangmin Yoo, Chan-Hong Park, Joonsuk Kim
2025	J	`jnl`	Guest Editorial: Introduction to the Special Section on the 2024 RFIC Symposium. IEEE J. Solid State Circuits Wanghua Wu
2022	—	`conf`	A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW. ISSCC Ashutosh Verma, Venumadhav Bhagavatula, Amitoj Singh, Wanghua Wu, Hariharan Nagarajan, Pak-Kim Lau, Xiaohua Yu, Omar Elsayed, Ajaypat Jain, Anirban Sarkar, Fan Zhang, Che-Chun Kuo, Patrick McElwee, Pei-Yuan Chiang, Chengkai Guo, Zhanjun Bai, Tienyu Chang, Abishek Mann, Andreas Rydin, Xingliang Zhao, Jeiyoung Lee, Daeyoung Yoon, Chih-Wei Yao, Siuchuang-Ivan Lu, Sang Won Son, Thomas Byunghak Cho
2022	J	`jnl`	Guest Editorial Introduction to the Special Issue on the 2022 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits Wanghua Wu, Hiroyuki Ito, Jens Anders, Ahmed M. A. Ali, Gaël Pillonnet
2021	—	`conf`	32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels. ISSCC Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Pak-Kim Lau, Lei Chen, Sang Won Son, Thomas Byunghak Cho
2021	J	`jnl`	A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO. IEEE J. Solid State Circuits Wanghua Wu, Chih-Wei Yao, Chengkai Guo, Pei-Yuan Chiang, Lei Chen, Pak-Kim Lau, Zhanjun Bai, Sang Won Son, Thomas Byunghak Cho
2021	—	`conf`	Session 32 Overview: Frequency Synthesizers Rf Subcommittee. ISSCC Wei Deng, Jaehyouk Choi, Wanghua Wu
2019	J	`jnl`	A 28-nm 75-fs IEEE J. Solid State Circuits Wanghua Wu, Chih-Wei Yao, Kunal Godbole, Ronghua Ni, Pei-Yuan Chiang, Yongping Han, Yongrong Zuo, Ashutosh Verma, Ivan Siu-Chuang Lu, Sang Won Son, Thomas Byunghak Cho
2017	J	`jnl`	A 14-nm 0.14-ps IEEE J. Solid State Circuits Chih-Wei Yao, Ronghua Ni, Chung Lau, Wanghua Wu, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang Won Son, Thomas Byunghak Cho
2016	—	`conf`	9.4 A 2×2 WLAN and Bluetooth combo SoC in 28nm CMOS with on-chip WLAN digital power amplifier, integrated 2G/BT SP3T switch and BT pulling cancelation. ISSCC Renaldi Winoto, Ashkan Olyaei, Mohammad Hajirostam, Wai Lau, Xiang Gao, Arnab Mitra, Ovidiu Carnu, Philip Godoy, Luns Tee, Hao Li, Erdem Erdogan, Alden Wong, Qiang Zhu, Timothy Loo, Fan Zhang, Liwei Sheng, Donghong Cui, Anuranjan Jha, Xiang Li, Wanghua Wu, Kun-Seok Lee, Derek Cheung, Ka Wo Pang, Haisong Wang, Jiexi Liu, Xingliang Zhao, Daibashish Gangopadhyay, David Cousinard, Arvind Anumula Paramanandam, Xiaoang Li, Norman Liu, Weiwei Xu, Yuan Fang, Xiaoyue Wang, Randy Tsang, Li Lin
2016	—	`conf`	9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, -246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS. ISSCC Xiang Gao, Olivier Burg, Haisong Wang, Wanghua Wu, Cao-Thong Tu, Konstantinos Manetakis, Fan Zhang, Luns Tee, Mustafa Yayla, Sining Xiang, Randy Tsang, Li Lin
2015	—	`conf`	9.4 A 28nm CMOS digital fractional-N PLL with -245.5dB FOM and a frequency tripler for 802.11abgn/ac radio. ISSCC Xiang Gao, Luns Tee, Wanghua Wu, Kun-Seok Lee, Arvind Anumula Paramanandam, Anuranjan Jha, Norman Liu, Edwin Chan, Li Lin
2014	J	`jnl`	A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS. IEEE J. Solid State Circuits Wanghua Wu, Robert Bogdan Staszewski, John R. Long
2014	—	`conf`	Design for test of a mm-Wave ADPLL-based transmitter. CICC Wanghua Wu, Robert Bogdan Staszewski, John R. Long
2013	—	`conf`	A 56.4-to-63.4GHz spurious-free all-digital fractional-N PLL in 65nm CMOS. ISSCC Wanghua Wu, Xuefei Bai, Robert Bogdan Staszewski, John R. Long
2013	J	`jnl`	High-Resolution Millimeter-Wave Digitally Controlled Oscillators With Reconfigurable Passive Resonators. IEEE J. Solid State Circuits Wanghua Wu, John R. Long, Robert Bogdan Staszewski
2012	J	`jnl`	Passive Circuit Technologies for mm-Wave Wireless Systems on Silicon. IEEE Trans. Circuits Syst. I Regul. Pap. John R. Long, Yi Zhao, Wanghua Wu, Marco Spirito, Leonardo Vera, Edward Gordon
2011	—	`conf`	Circuit technologies for mm-wave wireless systems on silicon. CICC John R. Long, Yi Zhao, Y. Jin, Wanghua Wu, Marco Spirito
2008	J	`jnl`	17 GHz RF Front-Ends for Low-Power Wireless Sensor Networks. IEEE J. Solid State Circuits Wanghua Wu, Mihai A. T. Sanduleanu, Xia Li, John R. Long
2008	—	`conf`	Energy-efficient wireless front-end concepts for ultra lower power radio. CICC John R. Long, Wanghua Wu, Yunzhi Dong, Yi Zhao, Mihai A. T. Sanduleanu, John F. M. Gerrits, Gerrit van Veenendaal