Wang Kang - RankMe

108 papers A* 9A 11B 1C 9Journal 44Unranked 34

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A 40 nm Buffer-Free 7T-SRAM Analog Charge-Domain CIM Macro With Merging Timing Based On Time-Row Division Strategy. IEEE Trans. Very Large Scale Integr. Syst. Linjun Jiang, Jianxin Wu, Sifan Sun, Changyu Li, Wang Kang, He Zhang
2026	J	`jnl`	Self-Calibrating Analog Circuitry for Softmax-Scaled Function With Analog Computing-In-Memory. IEEE Trans. Very Large Scale Integr. Syst. Linjun Jiang, Yitong Zhou, He Zhang, Wang Kang
2025	J	`jnl`	A 0.88 e‾ IEEE Trans. Circuits Syst. I Regul. Pap. Jianxin Wu, Wenjie Li, Wang Kang, Jing Kou, Liang Zhang, Liangchen Li, He Zhang, Weisheng Zhao
2025	—	`conf`	A 24.65 TOPS/W@INT8 Hybrid Analog-Digital Multi-core SRAM CIM Macro with Optimal Weight Dividing and Resource Allocation Strategies. ASP-DAC Yitong Zhou, Wente Yi, Sifan Sun, Wenjia Wang, Jinyu Bai, He Zhang, Wang Kang
2025	C	`conf`	ACSNN: A 61.25 TOPS/W, 1.65 ns delay SNN Processor that combines CIM-inspired Synapse and Asynchronous Architecture. ISCAS Tingran Chen, Yi Zhao, Yuxuan Ran, Yueting Li, Wang Kang, Biao Pan
2025	A*	`conf`	Accuracy Is Not Always We Need: Precision-Aware Bayesian Yield Optimization. DAC Jing Kou, Zidong Chen, Liang Zhang, Haiyan Qin, Wang Kang, Wei W. Xing
2025	A	`conf`	An Adaptive Sparse Matrix Compression CIM Accelerator based on 256Kb SOT-MRAM for Downlink Massive MIMO Communications. ICCAD Liangchen Li, Jianxin Wu, Changyu Li, Liang Zhang, Anyang Yu, Junda Zhao, Zhaohao Wang, Chengyuan Sun, Kaihua Cao, Hongxi Liu, Wang Kang, He Zhang, Weisheng Zhao
2025	A*	`conf`	Efficient Weight Mapping and Resource Scheduling on Crossbar-based Multi-core CIM Systems. DAC Hanjie Liu, Sifan Sun, Aifei Zhang, Haiyan Qin, Yutong Wu, Minhao Gu, Shihang Fu, Shuaikai Liu, Baosen Liu, Wang Kang
2025	J	`jnl`	Extending Straight-Through Estimation for Robust Neural Networks on Analog CIM Hardware. CoRR Yuannuo Feng, Wenyong Zhou, Yuexi Lyu, Yixiang Zhang, Zhengwu Liu, Ngai Wong, Wang Kang
2025	J	`jnl`	HPD: Hybrid Projection Decomposition for Robust State Space Models on Analog CIM Hardware. CoRR Yuannuo Feng, Wenyong Zhou, Yuexi Lyu, Hanjie Liu, Zhengwu Liu, Ngai Wong, Wang Kang
2025	J	`jnl`	HiT-CIM: A High-Throughput Compute-in-Memory SRAM Architecture With Simultaneous Weight Loading/Computing and Balance Capabilities. IEEE Trans. Emerg. Top. Comput. Junzhan Liu, Sifan Sun, Liang Zhang, Lichuan Luo, Liang Ran, He Zhang, Wang Kang, Weisheng Zhao
2025	A	`conf`	HyIMC: Analog-Digital Hybrid In-Memory Computing SoC for High-Quality Low-Latency Speech Enhancement. DATE Wanru Mao, Hanjie Liu, Guangyao Wang, Tianshuo Bai, Jingcheng Gu, Han Zhang, Xitong Yang, Aifei Zhang, Xiaohang Wei, Meng Wang, Wang Kang
2025	J	`jnl`	Model quantization for computing-in-memory: a survey. Sci. China Inf. Sci. Sifan Sun, Jinyu Bai, Hanting Chen, Kaiwen Deng, Zhiwei Xie, Jingjing Li, Bin Cao, He Zhang, Wang Kang, Weisheng Zhao
2025	A*	`conf`	Multi-Agent Yield Analysis For Circuit Design. DAC Haiyan Qin, Jing Kou, Liang Zhang, Wang Kang, Wei W. Xing
2025	A	`conf`	PAR-CIM: A Precise/Approximate Reconfigurable Digital CIM Macro with 0.35-4b Fractional Mixed-Bitwidth Quantization. ICCAD Han Zhang, Zhenyu Xue, Wente Yi, Tianshuo Bai, Lehao Tan, Jingcheng Gu, Weijie Ding, Wang Kang, Biao Pan
2025	J	`jnl`	ReasoningV: Efficient Verilog Code Generation with Adaptive Hybrid Reasoning Model. CoRR Haiyan Qin, Zhiwei Xie, Jingjing Li, Liangchen Li, Xiaotong Feng, Junzhan Liu, Wang Kang
2025	A	`conf`	Towards Accurate Characterization of In-Memory Computing Non-Idealities: A Physics & Data Co-Driven Generative Framework. ICCAD Jing Kou, Guangyao Wang, Saiya Wang, Yuexi Lv, Liang Zhang, Chenglin Yu, Xinghao Cui, Yulong Liu, Wei. W. Xing, Wang Kang
2025	J	`jnl`	Towards Optimal Circuit Generation: Multi-Agent Collaboration Meets Collective Intelligence. CoRR Haiyan Qin, Jiahao Feng, Xiaotong Feng, Wei W. Xing, Wang Kang
2024	J	`jnl`	An End-to-End In-Memory Computing System Based on a 40-nm eFlash-Based IMC SoC: Circuits, Toolchains, and Systems Co-Design Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tianshuo Bai, Wanru Mao, Guangyao Wang, Hanjie Liu, Aifei Zhang, Shihang Fu, Shuaikai Liu, Jianchao Hu, Xitong Yang, Biao Pan, Wei W. Xing, Wang Kang
2024	J	`jnl`	CIMQ: A Hardware-Efficient Quantization Framework for Computing-In-Memory-Based Neural Network Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jinyu Bai, Sifan Sun, Weisheng Zhao, Wang Kang
2024	J	`jnl`	CIM²PQ: An Arraywise and Hardware-Friendly Mixed Precision Quantization Method for Analog Computing-In-Memory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Sifan Sun, Jinyu Bai, Zhaoyu Shi, Weisheng Zhao, Wang Kang
2024	J	`jnl`	CiTST-AdderNets: Computing in Toggle Spin Torques MRAM for Energy-Efficient AdderNets. IEEE Trans. Circuits Syst. I Regul. Pap. Lichuan Luo, Erya Deng, Dijun Liu, Zhen Wang, Weiliang Huang, He Zhang, Xiao Liu, Jinyu Bai, Junzhan Liu, Youguang Zhang, Wang Kang
2024	—	`conf`	Device Characteristic-Aware Quantization for eFlash-Based In-Memory Computing SoC. ICTA Yizhe Chen, Guangyao Wang, Hanjie Liu, Yuexi Lv, Yuannuo Feng, Minghua Tang, Yong Pei, Wang Kang
2024	J	`jnl`	Erratum to "A Reconfigurable Spatial Architecture for Energy-Efficient Inception Neural Networks". IEEE J. Emerg. Sel. Topics Circuits Syst. Lichuan Luo, Wang Kang, Junzhan Liu, He Zhang, Youguang Zhang, Dijun Liu, Peng Ouyang
2024	—	`conf`	MixMixQ: Quantization with Mixed Bit-Sparsity and Mixed Bit-Width for CIM Accelerators. ACM Great Lakes Symposium on VLSI Jinyu Bai, He Zhang, Wang Kang
2024	A*	`conf`	Series-Parallel Hybrid SOT-MRAM Computing-in-Memory Macro with Multi-Method Modulation for High Area and Energy Efficiency. DAC Weiliang Huang, Jinyu Bai, Wang Kang, Zhaohao Wang, Kaihua Cao, Hongxi Liu, He Zhang, Weisheng Zhao
2024	J	`jnl`	Toward Energy-efficient STT-MRAM-based Near Memory Computing Architecture for Embedded Systems. ACM Trans. Embed. Comput. Syst. Yueting Li, Xueyan Wang, He Zhang, Biao Pan, Keni Qiu, Wang Kang, Jun Wang, Weisheng Zhao
2024	J	`jnl`	Toward Write Optimization for Skyrmion Racetrack Memory by Skyrmion Repermutation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tsun-Yu Yang, Xiangjun Peng, Wang Kang, Ming-Chang Yang
2023	—	`conf`	A 40nm 5-16Tops/W@INT8 eFlash In-Memory Computing SoC Chip with Noise Suppression and Compensation Techniques to Improve the Accuracy. ICTA Guanavao Wang, Yuexi Lv, Yu Tian, Jian Zhang, Carol Guo, Tianshuo Bai, Biao Pan, Derek Wang, Wang Kang
2023	J	`jnl`	A Reconfigurable Spatial Architecture for Energy-Efficient Inception Neural Networks. IEEE J. Emerg. Sel. Topics Circuits Syst. Lichuan Luo, Wang Kang, Junzhan Liu, He Zhang, Youguang Zhang, Dijun Liu, Peng Ouyang
2023	—	`conf`	An In-Memory-Computing STT-MRAM Macro with Analog ReLU and Pooling Layers for Ultra-High Efficient Neural Network. NVMSA Linjun Jiang, Sifan Sun, Jinming Ge, He Zhang, Wang Kang
2023	J	`jnl`	Differentiable Multi-Fidelity Fusion: Efficient Learning of Physics Simulations with Neural Architecture Search and Transfer Learning. CoRR Yuwen Deng, Wang Kang, Wei W. Xing
2023	—	`conf`	ES-MPQ: Evolutionary Search Enabled Mixed Precision Quantization Framework for Computing-in-Memory. NVMSA Sifan Sun, Jinming Ge, Jinyu Bai, Wang Kang
2023	J	`jnl`	Experimental Demonstration of STT-MRAM-based Nonvolatile Instantly On/Off System for IoT Applications: Case Studies. ACM Trans. Embed. Comput. Syst. Yueting Li, Wang Kang, Kunyu Zhou, Keni Qiu, Weisheng Zhao
2023	—	`conf`	Exploring Bit-Level Sparsity for Partial Sum Quantization in Computing-In-Memory Accelerator. NVMSA Jinyu Bai, Sifan Sun, Wang Kang
2023	J	`jnl`	Granularity-Driven Management for Reliable and Efficient Skyrmion Racetrack Memories. IEEE Trans. Emerg. Top. Comput. Yun-Shan Hsieh, Po-Chun Huang, Yuan-Hao Chang, Bo-Jun Chen, Wang Kang, Wei-Kuan Shih
2023	A	`conf`	Hierarchical Non-Structured Pruning for Computing-In-Memory Accelerators with Reduced ADC Resolution Requirement. DATE Wenlu Xue, Jinyu Bai, Sifan Sun, Wang Kang
2023	A	`conf`	OPT: Optimal Proposal Transfer for Efficient Yield Optimization for Analog and SRAM Circuits. ICCAD Yanfang Liu, Guohao Dai, Yuanqing Cheng, Wang Kang, Wei W. Xing
2023	J	`jnl`	Partial Sum Quantization for Computing-In-Memory-Based Neural Network Accelerator. IEEE Trans. Circuits Syst. II Express Briefs Jinyu Bai, Wenlu Xue, Yunqian Fan, Sifan Sun, Wang Kang
2023	J	`jnl`	Roadmap for Unconventional Computing with Nanotechnology. CoRR Giovanni Finocchio, Supriyo Bandyopadhyay, Peng Lin, Gang Pan, J. Joshua Yang, Riccardo Tomasello, Christos Panagopoulos, Mario Carpentieri, Vito Puliafito, Johan Åkerman, Hiroki Takesue, Amit Ranjan Trivedi, Saibal Mukhopadhyay, Kaushik Roy, Vinod K. Sangwan, Mark C. Hersam, Anna Giordano, Huynsoo Yang, Julie Grollier, Kerem Yunus Çamsari, Peter L. McMahon, Supriyo Datta, Jean Anne C. Incorvia, Joseph S. Friedman, Sorin Cotofana, Florin Ciubotaru, Andrii V. Chumak, Azad J. Naeemi, Brajesh Kumar Kaushik, Yao Zhu, Wang Kang, Belita Koiller, Gabriel Aguilar, Guilherme P. Temporão, Kremena Makasheva, Aida Todri-Sanial, Jennifer Hasler, William Levy, Vwani Roychowdhury, Samiran Ganguly, Avik W. Ghosh, Davi Rodriquez, Satoshi Sunada, Karin Everschor-Sitte, Amit Lal, Shubham Jadhav, Massimiliano Di Ventra, Yuriy V. Pershin, Kosuke Tatsumura, Hayato Goto
2023	—	`conf`	Searching Tiny Neural Networks for Deployment on Embedded FPGA. AICAS Haiyan Qin, Yejun Zeng, Jinyu Bai, Wang Kang
2022	J	`jnl`	A Mini Tutorial of Processing in Memory: From Principles, Devices to Prototypes. IEEE Trans. Circuits Syst. II Express Briefs Biao Pan, Guangyao Wang, He Zhang, Wang Kang, Weisheng Zhao
2022	J	`jnl`	A Spintronic In-Memory Computing Network for Efficient Hamming Codec Implementation. IEEE Trans. Circuits Syst. II Express Briefs Linjun Jiang, Erya Deng, He Zhang, Zhaohao Wang, Wang Kang, Weisheng Zhao
2022	A*	`conf`	CP-SRAM: charge-pulsation SRAM marco for ultra-high energy-efficiency computing-in-memory. DAC He Zhang, Linjun Jiang, Jianxin Wu, Tingran Chen, Junzhan Liu, Wang Kang, Weisheng Zhao
2022	J	`jnl`	HD-CIM: Hybrid-Device Computing-In-Memory Structure Based on MRAM and SRAM to Reduce Weight Loading Energy of Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. He Zhang, Junzhan Liu, Jinyu Bai, Sai Li, Lichuan Luo, Shaoqian Wei, Jianxin Wu, Wang Kang
2022	A*	`conf`	SMART: on simultaneously marching racetracks to improve the performance of racetrack-based main memory. DAC Xiangjun Peng, Ming-Chang Yang, Ho Ming Tsui, Chi Ngai Leung, Wang Kang
2022	J	`jnl`	SpinCIM: spin orbit torque memory for ternary neural networks based on the computing-in-memory architecture. CCF Trans. High Perform. Comput. Lichuan Luo, Dijun Liu, He Zhang, Youguang Zhang, Jinyu Bai, Wang Kang
2021	—	`conf`	A 40nm 33.6Tops/W 8T-SRAM Computing-in-Memory Macro with DAC-less Spike-Pulse-Truncation Input and ADC-less Charge-Reservoir-Integrate-Counter Output. ICTA He Zhang, Junzhan Liu, Wang Kang, Yunqian Fan, Shufeng Fu, Jinyu Bai, Biao Pan, Yongpan Liu, Weisheng Zhao
2021	J	`jnl`	Forecasting the outcome of spintronic experiments with Neural Ordinary Differential Equations. CoRR Xing Chen, Flavio Abreu Araujo, Mathieu Riou, Jacob Torrejon, Dafine Ravelosona, Wang Kang, Weisheng Zhao, Julie Grollier, Damien Querlioz
2021	C	`conf`	HSC: A Hybrid Spin/CMOS Logic Based In-Memory Engine with Area-Efficient Mapping Strategy. ISCAS Yan Huang, Erya Deng, Jinyu Bai, Qing Yang, Wang Kang, Biao Pan
2021	C	`conf`	Spin-Orbit Torque Nonvolatile Flip-Flop Designs. ISCAS Erya Deng, Wang Kang, Weisheng Zhao, Shaoqian Wei, You Wang, Deming Zhang
2021	A	`conf`	SpinLiM: Spin Orbit Torque Memory for Ternary Neural Networks Based on the Logic-in-Memory Architecture. DATE Lichuan Luo, He Zhang, Jinyu Bai, Youguang Zhang, Wang Kang, Weisheng Zhao
2021	—	`conf`	Tiny neural network search and implementation for embedded FPGA: a software-hardware co-design approach. A-SSCC Jinyu Bai, Yunqian Fan, Sifan Sun, Wang Kang, Weisheng Zhao
2020	J	`jnl`	A Comparative Cross-layer Study on Racetrack Memories: Domain Wall vs Skyrmion. ACM J. Emerg. Technol. Comput. Syst. Wang Kang, Bi Wu, Xing Chen, Daoqian Zhu, Zhaohao Wang, Xichao Zhang, Yan Zhou, Youguang Zhang, Weisheng Zhao
2020	—	`conf`	Deep Neural Network accelerator with Spintronic Memory. ACM Great Lakes Symposium on VLSI He Zhang, Wang Kang, Youguang Zhang, Weisheng Zhao
2020	A	`conf`	High-Density, Low-Power Voltage-Control Spin Orbit Torque Memory with Synchronous Two-Step Write and Symmetric Read Techniques. DATE Haotian Wang, Wang Kang, Liuyang Zhang, He Zhang, Brajesh Kumar Kaushik, Weisheng Zhao
2020	A*	`conf`	Permutation-Write: Optimizing Write Performance and Energy for Skyrmion Racetrack Memory. DAC Tsun-Yu Yang, Ming-Chang Yang, Jiawei Li, Wang Kang
2020	J	`jnl`	Shift-Limited Sort: Optimizing Sorting Performance on Skyrmion Memory-Based Systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yun-Shan Hsieh, Po-Chun Huang, Ping-Xiang Chen, Yuan-Hao Chang, Wang Kang, Ming-Chang Yang, Wei-Kuan Shih
2019	J	`jnl`	An STT-MRAM Based in Memory Architecture for Low Power Integral Computing. IEEE Trans. Computers Yinglin Zhao, Peng Ouyang, Wang Kang, Shouyi Yin, Youguang Zhang, Shaojun Wei, Weisheng Zhao
2019	—	`conf`	Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration. ISVLSI Yinglin Zhao, Jianlei Yang, Xiaotao Jia, Xueyan Wang, Zhaohao Wang, Wang Kang, Youguang Zhang, Weisheng Zhao
2019	J	`jnl`	Low-Power (1T1N) Skyrmionic Synapses for Spiking Neuromorphic Systems. IEEE Access Tinish Bhattacharya, Sai Li, Yangqi Huang, Wang Kang, Weisheng Zhao, Manan Suri
2019	—	`conf`	Spintronic Memories: From Memory to Computing-in-Memory. NANOARCH Wang Kang, He Zhang, Weisheng Zhao
2019	—	`conf`	Voltage-Controlled Magnetoelectric Memory Bit-cell Design With Assisted Body-bias in FD-SOI. ACM Great Lakes Symposium on VLSI Hao Cai, Menglin Han, Weiwei Shan, Jun Yang, You Wang, Wang Kang, Weisheng Zhao
2019	A*	`conf`	ZUMA: Enabling Direct Insertion/Deletion Operations with Emerging Skyrmion Racetrack Memory. DAC Zheng Liang, Guangyu Sun, Wang Kang, Xing Chen, Weisheng Zhao
2018	—	`conf`	A Comparative Study on Racetrack Memories: Domain Wall vs. Skyrmion. NVMSA Wang Kang, Xing Chen, Daoqian Zhu, Xichao Zhang, Yan Zhou, Keni Qiu, Youguang Zhang, Weisheng Zhao
2018	J	`jnl`	A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM. IEEE Access He Zhang, Wang Kang, Youguang Zhang, Meng-Fan Chang, Weisheng Zhao
2018	—	`conf`	A Novel Cross-point MRAM with Diode Selector Capable of High-Density, High-Speed, and Low-Power In-Memory Computation. NANOARCH Chaoxin Ding, Wang Kang, He Zhang, Youguang Zhang, Weisheng Zhao
2018	—	`conf`	A Robust Dual Reference Computing-in-Memory Implementation and Design Space Exploration Within STT-MRAM. ISVLSI Liuyang Zhang, Wang Kang, Hao Cai, Peng Ouyang, Lionel Torres, Youguang Zhang, Aida Todri-Sanial, Weisheng Zhao
2018	C	`conf`	Design and Data Management for Magnetic Racetrack Memory. ISCAS Bing Li, Fan Chen, Wang Kang, Weisheng Zhao, Yiran Chen, Hai Li
2018	—	`conf`	Emerging Neuromorphic Computing Paradigms Exploring Magnetic Skyrmions. ISVLSI Sai Li, Wang Kang, Xing Chen, Jinyu Bai, Biao Pan, Youguang Zhang, Weisheng Zhao
2018	C	`conf`	Enabling Resilient Voltage-Controlled MeRAM Using Write Assist Techniques. ISCAS Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner, Weiwei Shan, Jun Yang, Weisheng Zhao
2018	—	`conf`	High-Density and Fast-Configuration Non-Volatile Look-Up Table Based on NAND-Like Spintronic Memory. APCCAS He Zhang, Wang Kang, Zhaohao Wang, Erya Deng, Youguang Zhang, Weisheng Zhao
2018	—	`conf`	MRAM-on-FDSOI Integration: A Bit-Cell Perspective. ISVLSI Hao Cai, You Wang, Wang Kang, Lirida A. B. Naviner, Xinning Liu, Jun Yang, Weisheng Zhao
2018	A	`conf`	Magnetic skyrmions for future potential memory and logic applications: Alternative information carriers. DATE Wang Kang, Xing Chen, Daoqian Zhu, Sai Li, Yangqi Huang, Youguang Zhang, Weisheng Zhao
2018	C	`conf`	Multi-bit nonvolatile flip-flop based on NAND-like spin transfer torque MRAM. VLSI-SoC Erya Deng, Zhaohao Wang, Wang Kang, Shaoqian Wei, Weisheng Zhao
2018	—	`conf`	Process variation aware data management for magnetic skyrmions racetrack memory. ASP-DAC Fan Chen, Zheng Li, Wang Kang, Weisheng Zhao, Hai Li, Yiran Chen
2018	C	`conf`	Progresses and challenges of spin orbit torque driven magnetization switching and application (Invited). ISCAS Zhaohao Wang, Zuwei Li, Yang Liu, Simin Li, Liang Chang, Wang Kang, Youguang Zhang, Weisheng Zhao
2017	—	`conf`	Advanced Low Power Spintronic Memories beyond STT-MRAM. ACM Great Lakes Symposium on VLSI Wang Kang, Zhaohao Wang, He Zhang, Sai Li, Youguang Zhang, Weisheng Zhao
2017	—	`conf`	An Efficient Racetrack Memory-Based Processing-in-Memory Architecture for Convolutional Neural Networks. ISPA/IUCC Bicheng Liu, Shouzhen Gu, Mingsong Chen, Wang Kang, Jingtong Hu, Qingfeng Zhuge, Edwin Hsing-Mean Sha
2017	J	`jnl`	Dynamic Dual-Reference Sensing Scheme for Deep Submicrometer STT-MRAM. IEEE Trans. Circuits Syst. I Regul. Pap. Wang Kang, Tingting Pang, Weifeng Lv, Weisheng Zhao
2017	—	`conf`	Energy Efficient Magnetic Tunnel Junction Based Hybrid LSI Using Multi-Threshold UTBB-FD-SOI Device. ACM Great Lakes Symposium on VLSI Hao Cai, You Wang, Lirida A. B. Naviner, Wang Kang, Weisheng Zhao
2017	C	`conf`	Programmable Stateful In-Memory Computing Paradigm via a Single Resistive Device. ICCD Wang Kang, He Zhang, Peng Ouyang, Youguang Zhang, Weisheng Zhao
2017	J	`jnl`	Pseudo-Differential Sensing Framework for STT-MRAM: A Cross-Layer Perspective. IEEE Trans. Computers Wang Kang, Liang Chang, Zhaohao Wang, Weifeng Lv, Guangyu Sun, Weisheng Zhao
2017	—	`conf`	Ultrafast spintronic integrated circuits. ASICON Jiaqi Wei, Liang Chang, Zhaohao Wang, Xiaoyang Lin, Kaihua Cao, Hushan Cui, Wang Kang, Haoxuan Chen, Lang Zeng, Youguang Zhang, Chao Zhao, Weisheng Zhao
2017	A	`conf`	Voltage-controlled MRAM for working memory: Perspectives and challenges. DATE Wang Kang, Liang Chang, Youguang Zhang, Weisheng Zhao
2016	—	`conf`	A spin Hall effect-based multi-level cell for MRAM. NANOARCH Qian Shi, Zhaohao Wang, Yuqian Gao, Liang Chang, Wang Kang, Youguang Zhang, Weisheng Zhao
2016	J	`jnl`	Complementary Skyrmion Racetrack Memory with Voltage Manipulation. CoRR Wang Kang, Chentian Zheng, Yangqi Huang, Xichao Zhang, Yan Zhou, Weifeng Lv, Weisheng Zhao
2016	—	`conf`	Dual reference sensing scheme with triple steady states for deeply scaled STT-MRAM. NANOARCH He Zhang, Wang Kang, Tingting Pang, Weifeng Lv, Youguang Zhang, Weisheng Zhao
2016	—	`conf`	Evaluation of spin-Hall-assisted STT-MRAM for cache replacement. NANOARCH Liang Chang, Zhaohao Wang, Yuqian Gao, Wang Kang, Youguang Zhang, Weisheng Zhao
2016	J	`jnl`	Magnetic skyrmion-based synaptic devices. CoRR Yangqi Huang, Wang Kang, Xichao Zhang, Yan Zhou, Weisheng Zhao
2016	A*	`conf`	PDS: pseudo-differential sensing scheme for STT-MRAM. DAC Wang Kang, Tingting Pang, Bi Wu, Weifeng Lv, Youguang Zhang, Guangyu Sun, Weisheng Zhao
2016	C	`conf`	Quantitative evaluation of reliability and performance for STT-MRAM. ISCAS Liuyang Zhang, Aida Todri-Sanial, Wang Kang, Youguang Zhang, Lionel Torres, Yuanqing Cheng, Weisheng Zhao
2016	J	`jnl`	Read disturbance issue and design techniques for nanoscale STT-MRAM. J. Syst. Archit. Yi Ran, Wang Kang, Youguang Zhang, Jacques-Olivier Klein, Weisheng Zhao
2016	J	`jnl`	Skyrmion-Electronics: An Overview and Outlook. Proc. IEEE Wang Kang, Yangqi Huang, Xichao Zhang, Yan Zhou, Weisheng Zhao
2016	J	`jnl`	Skyrmions as Compact, Robust and Energy-Efficient Interconnects for Domain Wall (DW)-based Systems. CoRR Wang Kang, Yangqi Huang, Xichao Zhang, Yan Zhou, Weifeng Lv, Weisheng Zhao
2015	—	`conf`	Channel Modeling and Reliability Enhancement Design Techniques for STT-MRAM. ISVLSI Liuyang Zhang, Wang Kang, Youguang Zhang, Yuanqing Cheng, Lang Zeng, Jacques-Olivier Klein, Weisheng Zhao
2015	—	`conf`	Nonvolatile radiation hardened DICE latch. NVMTS Tingting Pang, Wang Kang, Yi Ran, Youguang Zhang, Weifeng Lv, Weisheng Zhao
2015	—	`conf`	Read disturbance issue for nanoscale STT-MRAM. NVMSA Yi Ran, Wang Kang, Youguang Zhang, Jacques-Olivier Klein, Weisheng Zhao
2015	J	`jnl`	Spintronics: Emerging Ultra-Low-Power Circuits and Systems beyond MOS Technology. ACM J. Emerg. Technol. Comput. Syst. Wang Kang, Yue Zhang, Zhaohao Wang, Jacques-Olivier Klein, Claude Chappert, Dafine Ravelosona, Gefei Wang, Youguang Zhang, Weisheng Zhao
2015	J	`jnl`	Synchronous 8-bit Non-Volatile Full-Adder based on Spin Transfer Torque Magnetic Tunnel Junction. IEEE Trans. Circuits Syst. I Regul. Pap. Erya Deng, Yue Zhang, Wang Kang, Bernard Dieny, Jacques-Olivier Klein, Guillaume Prenat, Weisheng Zhao
2015	J	`jnl`	Yield and Reliability Improvement Techniques for Emerging Nonvolatile STT-MRAM. IEEE J. Emerg. Sel. Topics Circuits Syst. Wang Kang, Liuyang Zhang, Weisheng Zhao, Jacques-Olivier Klein, Youguang Zhang, Dafine Ravelosona, Claude Chappert
2014	—	`conf`	An overview of spin-based integrated circuits. ASP-DAC Wang Kang, Weisheng Zhao, Zhaohao Wang, Jacques-Olivier Klein, Yue Zhang, Djaafar Chabi, Youguang Zhang, Dafine Ravelosona, Claude Chappert
2014	J	`jnl`	Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells. J. Parallel Distributed Comput. Weisheng Zhao, Jean-Michel Portal, Wang Kang, Mathieu Moreau, Yue Zhang, Hassen Aziza, Jacques-Olivier Klein, Zhaohao Wang, Damien Querlioz, Damien Deleruyelle, Marc Bocquet, Dafine Ravelosona, Christophe Muller, Claude Chappert
2014	B	`conf`	Ferroelectric tunnel memristor-based neuromorphic network with 1T1R crossbar architecture. IJCNN Zhaohao Wang, Weisheng Zhao, Wang Kang, Youguang Zhang, Jacques-Olivier Klein, Claude Chappert
2014	—	`conf`	One-step majority-logic-decodable codes enable STT-MRAM for high speed working memories. NVMSA Wang Kang, Weisheng Zhao, Lun Yang, Jacques-Olivier Klein, Youguang Zhang, Dafine Ravelosona
2014	A	`conf`	Spintronics for low-power computing. DATE Yue Zhang, Weisheng Zhao, Jacques-Olivier Klein, Wang Kang, Damien Querlioz, Youguang Zhang, Dafine Ravelosona, Claude Chappert
2013	J	`jnl`	A low-cost built-in error correction circuit design for STT-MRAM reliability improvement. Microelectron. Reliab. Wang Kang, Weisheng Zhao, Zhaohao Wang, Yue Zhang, Jacques-Olivier Klein, Youguang Zhang, Claude Chappert, Dafine Ravelosona
2012	—	`conf`	Improving flash memory reliability with dynamic thresholds: Signal processing and coding schemes. CHINACOM Wang Kang, Youguang Zhang, Mingbang Wang, Guoyan Li