Wang-Dauh Tseng

21 papers Journal 11Unranked 10
YearRankTypeTitle / Venue / Authors
2021 J jnl
A Cascaded Multicasting Architecture for Test Data Compression.
J. Electron. Test.
Wang-Dauh Tseng
2019 J jnl
Multi-Scan Architecture with Scan Chain Disabling Technique for Capture Power Reduction.
J. Inf. Sci. Eng.
Jen-Cheng Ying, Wang-Dauh Tseng, Wen-Jiin Tsai
2018 J jnl
Asymmetry dual-LFSR reseeding for low power BIST.
Integr.
Jen-Cheng Ying, Wang-Dauh Tseng, Wen-Jiin Tsai
2018 — conf
Bipolar Dual-LFSR Reseeding for Low-Power Testing.
DSC
Jen-Cheng Ying, Wang-Dauh Tseng, Wen-Jiin Tsai
2012 J jnl
$2^{n}$ Pattern Run-Length for Test Data Compression.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Cheng-Ho Chang
2012 — conf
Deterministic ATPG for Low Capture Power Testing.
MTV
Lung-Jen Lee, Chia-Cheng He, Wang-Dauh Tseng
2012 — conf
Dual-LFSR Reseeding for Low Power Testing.
MTV
Lung-Jen Lee, Wang-Dauh Tseng, Wen-Ting Yang
2012 — conf
Two-Way Multicasting for Test Data Compression.
MTV
Lung-Jen Lee, Wang-Dauh Tseng, Wei-Shun Chen
2010 J jnl
Deterministic built-in self-test using multiple linear feedback shift registers for test power and test volume reduction.
IET Comput. Digit. Tech.
Wang-Dauh Tseng, Lung-Jen Lee, Rung-Bin Lin
2010 J jnl
Test Data Compression Using Multi-dimensional Pattern Run-length Codes.
J. Electron. Test.
Wang-Dauh Tseng, Lung-Jen Lee
2009 — conf
A Multi-dimensional Pattern Run-Length Method for Test Data Compression.
Asian Test Symposium
Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chen-Lun Lee
2009 — conf
Deterministic Built-In Self-Test Using Multiple Linear Feedback Shift Registers for Low-Power Scan Testing.
Asian Test Symposium
Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin, Chi-Wei Yu
2008 J jnl
Power Reduction during Scan Testing Based on Multiple Capture Technique.
IEICE Trans. Electron.
Lung-Jen Lee, Wang-Dauh Tseng, Rung-Bin Lin
2007 J jnl
A novel dynamic Multiple Ring-based Local Restoration for point-to-multipoint multicast traffic in WDM mesh networks.
Photonic Netw. Commun.
I-Shyan Hwang, Ren-Yuan Cheng, Wang-Dauh Tseng
2007 J jnl
Generation of Primary Input Blocking Pattern for Power Minimization during Scan Testing.
J. Electron. Test.
Wang-Dauh Tseng
2007 — conf
Reduction of Power Dissipation during Scan Testing by Test Vector Ordering.
MTV
Wang-Dauh Tseng, Lung-Jen Lee
2006 J jnl
A novel dynamic fault restoration mechanism using cluster allocation approach in WDM mesh networks.
Comput. Commun.
I-Shyan Hwang, Meng-Yuan Tu, Wang-Dauh Tseng, Zen-Der Shyu
2002 — conf
Printed circuit board routing and package layout codesign.
APCCAS (1)
Shuenn-Shi Chen, Wang-Dauh Tseng, Jin-Tai Yan, Sao-Jie Chen
1999 J jnl
Fuzzy-based CMOS circuit partitioning in built-in current testing.
IEEE Trans. Very Large Scale Integr. Syst.
Wang-Dauh Tseng, Kuochen Wang
1997 — conf
Fuzzy-based circuit partitioning in built-in current testing.
ASP-DAC
Wang-Dauh Tseng, Kuochen Wang
1996 — conf
Testable Design and Testing of MCMs Based on Multifrequency Scan.
Asian Test Symposium
Wang-Dauh Tseng, Kuochen Wang