Walter Stechele

176 papers A* 7A 20B 11C 18Misc 1Journal 30Unranked 84

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	HiFi-LLP: High-Fidelity, Low-Cost Latency Predictors with Confidence for Robust HW-NAS. SOCC Shambhavi Balamuthu Sampath, Behzad Shomali, Nael Fasfous, Moritz Thoma, Judeson Anthony Fernando, Lukas Frickenstein, Pierpaolo Morì, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele
2025	A	`conf`	HiFi-SAGE: High Fidelity GraphSAGE-Based Latency Estimators for DNN Optimization. DATE Shambhavi Balamuthu Sampath, Leon Hecht, Moritz Thoma, Lukas Frickenstein, Pierpaolo Morì, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone
2025	A*	`conf`	LA-MTL: Latency-Aware Automated Multi-Task Learning. DAC Shambhavi Balamuthu Sampath, Sami Sawani, Moritz Thoma, Lukas Frickenstein, Pierpaolo Morì, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Ulf Schlichtmann, Claudio Passerone, Walter Stechele
2025	—	`conf`	RepFC: Universal Structural Reparametrization Block for High Performance, Lightweight Deep Neural Networks. CVPR Workshops Shambhavi Balamuthu Sampath, Judeson Anthony Fernando, Moritz Thoma, Nael Fasfous, Lukas Frickenstein, Pierpaolo Morì, Manoj Rohit Vemparala, Alexander Frickenstein, Ulf Schlichtmann, Walter Stechele
2024	A	`conf`	MATAR: Multi-Quantization-Aware Training for Accurate and Fast Hardware Retargeting. DATE Pierpaolo Morì, Moritz Thoma, Lukas Frickenstein, Shambhavi Balamuthu Sampath, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone
2024	—	`conf`	Pruning as a Binarization Technique. CVPR Workshops Lukas Frickenstein, Pierpaolo Morì, Shambhavi Balamuthu Sampath, Moritz Thoma, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Christian Unger, Claudio Passerone, Walter Stechele
2024	J	`jnl`	ReLiCADA: Reservoir Computing Using Linear Cellular Automata design algorithm. Complex Intell. Syst. Jonas Kantic, Fabian C. Legl, Walter Stechele, Jakob Hermann
2024	A	`conf`	Wino Vidi Vici: Conquering Numerical Instability of 8-bit Winograd Convolution for Accurate Inference Acceleration on Edge. WACV Pierpaolo Morì, Lukas Frickenstein, Shambhavi Balamuthu Sampath, Moritz Thoma, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Christian Unger, Walter Stechele, Daniel Mueller-Gritschneder, Claudio Passerone
2023	—	`conf`	Adversarial Robustness of Multi-bit Convolutional Neural Networks. IntelliSys (3) Lukas Frickenstein, Shambhavi Balamuthu Sampath, Pierpaolo Morì, Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Christian Unger, Claudio Passerone, Walter Stechele
2023	—	`conf`	Lightweight Instruction Set for Flexible Dilated Convolutions and Mixed-Precision Operands. ISQED Simon Friedrich, Shambhavi Balamuthu Sampath, Robert Wittig, Manoj Rohit Vemparala, Nael Fasfous, Emil Matús, Walter Stechele, Gerhard P. Fettweis
2023	J	`jnl`	ReLiCADA - Reservoir Computing using Linear Cellular Automata Design Algorithm. CoRR Jonas Kantic, Fabian C. Legl, Walter Stechele, Jakob Hermann
2023	J	`jnl`	Skeleton Graph-Based Ultrasound-CT Non-Rigid Registration. IEEE Robotics Autom. Lett. Zhongliang Jiang, Xuesong Li, Chenyu Zhang, Yuan Bi, Walter Stechele, Nassir Navab
2023	J	`jnl`	Skeleton Graph-based Ultrasound-CT Non-rigid Registration. CoRR Zhongliang Jiang, Xuesong Li, Chenyu Zhang, Yuan Bi, Walter Stechele, Nassir Navab
2023	A*	`conf`	WinoTrain: Winograd-Aware Training for Accurate Full 8-bit Convolution Acceleration. DAC Pierpaolo Morì, Shambhavi Balamuthu Sampath, Lukas Frickenstein, Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Walter Stechele, Claudio Passerone
2022	A*	`conf`	Accelerating and pruning CNNs for semantic segmentation on FPGA. DAC Pierpaolo Morì, Manoj Rohit Vemparala, Nael Fasfous, Saptarshi Mitra, Sreetama Sarkar, Alexander Frickenstein, Lukas Frickenstein, Domenik Helms, Naveen Shankar Nagaraja, Walter Stechele, Claudio Passerone
2022	A	`conf`	AnaCoNGA: Analytical HW-CNN Co-Design Using Nested Genetic Algorithms. DATE Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Emanuele Valpreda, Driton Salihu, Julian Höfer, Anmol Singh, Naveen Shankar Nagaraja, Hans-Jörg Vögel, Nguyen Anh Vu Doan, Maurizio Martina, Jürgen Becker, Walter Stechele
2022	J	`jnl`	Autonomous Robotic Screening of Tubular Structures Based Only on Real-Time Ultrasound Imaging Feedback. IEEE Trans. Ind. Electron. Zhongliang Jiang, Zhenyu Li, Matthias Grimm, Mingchuan Zhou, Marco Esposito, Wolfgang Wein, Walter Stechele, Thomas Wendler, Nassir Navab
2022	J	`jnl`	HW-Flow: A Multi-Abstraction Level HW-CNN Codesign Pruning Methodology. Leibniz Trans. Embed. Syst. Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Emanuele Valpreda, Manfredi Camalleri, Qi Zhao, Christian Unger, Naveen Shankar Nagaraja, Maurizio Martina, Walter Stechele
2022	A	`conf`	Mind the Scaling Factors: Resilience Analysis of Quantized Adversarially Robust CNNs. DATE Nael Fasfous, Lukas Frickenstein, Michael Neumeier, Manoj Rohit Vemparala, Alexander Frickenstein, Emanuele Valpreda, Maurizio Martina, Walter Stechele
2022	—	`conf`	Non-iterative Blind Deblurring of Digital Microscope Images with Spatially Varying Blur. MIUA Furkan Kaynar, Peter Geißler, Laurent Demaret, Tamara Seybold, Walter Stechele
2022	—	`conf`	Potentials of combined visible light and near infrared imaging for driving automation. Autonomous Vehicles and Machines Korbinian Weikl, Damien Schroeder, Walter Stechele
2022	A	`conf`	Region of interest based non-dominated sorting genetic algorithm-II: an invite and conquer approach. GECCO Manu Manuel, Benjamin Hien, Simon Conrady, Arne Kreddig, Nguyen Anh Vu Doan, Walter Stechele
2021	C	`conf`	A Framework for Hardware-Accelerated Design Space Exploration for Approximate Computing on FPGA. DSD Arne Kreddig, Simon Conrady, Manu Manuel, Walter Stechele
2021	—	`conf`	Adversarial Robust Model Compression Using In-Train Pruning. CVPR Workshops Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Sreetama Sarkar, Qi Zhao, Sabine Kuhn, Lukas Frickenstein, Anmol Singh, Christian Unger, Naveen Shankar Nagaraja, Christian Wressnegger, Walter Stechele
2021	A*	`conf`	Binary-LoRAX: Low-Latency Runtime Adaptable XNOR Classifier for Semi-Autonomous Grasping with Prosthetic Hands. ICRA Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Mohamed Badawy, Felix Hundhausen, Julian Höfer, Naveen Shankar Nagaraja, Christian Unger, Hans-Jörg Vögel, Jürgen Becker, Tamim Asfour, Walter Stechele
2021	—	`conf`	BinaryCoP: Binary Neural Network-based COVID-19 Face-Mask Wear and Positioning Predictor on Edge Devices. IPDPS Workshops Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Lukas Frickenstein, Mohamed Badawy, Walter Stechele
2021	J	`jnl`	BinaryCoP: Binary Neural Network-based COVID-19 Face-Mask Wear and Positioning Predictor on Edge Devices. CoRR Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Lukas Frickenstein, Walter Stechele
2021	J	`jnl`	BreakingBED - Breaking Binary and Efficient Deep Neural Networks by Adversarial Attacks. CoRR Manoj Rohit Vemparala, Alexander Frickenstein, Nael Fasfous, Lukas Frickenstein, Qi Zhao, Sabine Kuhn, Daniel Ehrhardt, Yuankai Wu, Christian Unger, Naveen Shankar Nagaraja, Walter Stechele
2021	—	`conf`	BreakingBED: Breaking Binary and Efficient Deep Neural Networks by Adversarial Attacks. IntelliSys (1) Manoj Rohit Vemparala, Alexander Frickenstein, Nael Fasfous, Lukas Frickenstein, Qi Zhao, Sabine Kuhn, Daniel Ehrhardt, Yuankai Wu, Christian Unger, Naveen Shankar Nagaraja, Walter Stechele
2021	—	`conf`	End-to-End Imaging System Optimization for Computer Vision in Driving Automation. Autonomous Vehicles and Machines Korbinian Weikl, Damien Schroeder, Daniel Blau, Zhenyi Liu, Walter Stechele
2021	J	`jnl`	HW-FlowQ: A Multi-Abstraction Level HW-CNN Co-design Quantization Methodology. ACM Trans. Embed. Comput. Syst. Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Emanuele Valpreda, Driton Salihu, Nguyen Anh Vu Doan, Christian Unger, Naveen Shankar Nagaraja, Maurizio Martina, Walter Stechele
2021	A	`conf`	Hardware-Aware Mixed-Precision Neural Networks using In-Train Quantization. BMVC Manoj Rohit Vemparala, Nael Fasfous, Lukas Frickenstein, Alexander Frickenstein, Anmol Singh, Driton Salihu, Christian Unger, Naveen Shankar Nagaraja, Walter Stechele
2021	C	`conf`	Investigating Binary Neural Networks for Traffic Sign Detection and Recognition. IV Ee Heng Chen, Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Ahmed Mzid, Naveen Shankar Nagaraja, Jöran Zeisler, Walter Stechele
2021	J	`jnl`	L2PF - Learning to Prune Faster. CoRR Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Mhd Ali Moraly, Aquib Jamal, Lukas Frickenstein, Christian Unger, Naveen Shankar Nagaraja, Walter Stechele
2021	J	`jnl`	Model-Based Design Space Exploration for FPGA-based Image Processing Applications Employing Parameterizable Approximations. Microprocess. Microsystems Simon Conrady, Arne Kreddig, Manu Manuel, Nguyen Anh Vu Doan, Walter Stechele
2021	—	`conf`	Pruning CNNs for LiDAR-based Perception in Resource Constrained Environments. IV Workshops Manoj Rohit Vemparala, Anmol Singh, Ahmed Mzid, Nael Fasfous, Alexander Frickenstein, Florian Mirus, Hans-Jörg Vögel, Naveen Shankar Nagaraja, Walter Stechele
2021	J	`jnl`	Region of Interest-Based Parameter Optimization for Approximate Image Processing on FPGAs. Int. J. Netw. Comput. Manu Manuel, Arne Kreddig, Simon Conrady, Nguyen Anh Vu Doan, Walter Stechele
2021	—	`conf`	Sensor Fusion Neural Networks for Gesture Recognition on Low-power Edge Devices. ICAART (2) Gábor Balázs, Mateusz Chmurski, Walter Stechele, Mariusz Zubert
2020	A*	`conf`	ALF: Autoencoder-based Low-rank Filter-sharing for Efficient Convolutional Neural Networks. DAC Alexander Frickenstein, Manoj Rohit Vemparala, Nael Fasfous, Laura Hauenschild, Naveen Shankar Nagaraja, Christian Unger, Walter Stechele
2020	J	`jnl`	ALF: Autoencoder-based Low-rank Filter-sharing for Efficient Convolutional Neural Networks. CoRR Alexander Frickenstein, Manoj Rohit Vemparala, Nael Fasfous, Laura Hauenschild, Naveen Shankar Nagaraja, Christian Unger, Walter Stechele
2020	J	`jnl`	Autonomous Robotic Screening of Tubular Structures based only on Real-Time Ultrasound Imaging Feedback. CoRR Zhongliang Jiang, Zhenyu Li, Matthias Grimm, Mingchuan Zhou, Marco Esposito, Wolfgang Wein, Walter Stechele, Thomas Wendler, Nassir Navab
2020	A*	`conf`	Binary DAD-Net: Binarized Driveable Area Detection Network for Autonomous Driving. ICRA Alexander Frickenstein, Manoj Rohit Vemparala, Jakob Mayr, Naveen Shankar Nagaraja, Christian Unger, Federico Tombari, Walter Stechele
2020	J	`jnl`	Binary DAD-Net: Binarized Driveable Area Detection Network for Autonomous Driving. CoRR Alexander Frickenstein, Manoj Rohit Vemparala, Jakob Mayr, Naveen Shankar Nagaraja, Christian Unger, Federico Tombari, Walter Stechele
2020	—	`conf`	L2PF - Learning to Prune Faster. CVIP (3) Manoj Rohit Vemparala, Nael Fasfous, Alexander Frickenstein, Mhd Ali Moraly, Aquib Jamal, Lukas Frickenstein, Christian Unger, Naveen Shankar Nagaraja, Walter Stechele
2020	—	`conf`	Model-Based Design Space Exploration for Approximate Image Processing on FPGA. NorCAS Manu Manuel, Arne Kreddig, Simon Conrady, Nguyen Anh Vu Doan, Walter Stechele
2020	C	`conf`	Neural Architecture Search for Automotive Grid Fusion Networks Under Embedded Hardware Constraints. ICMLA Gábor Balázs, Walter Stechele
2020	—	`conf`	Optimization of automotive color filter arrays for traffic light color separation. CIC Korbinian Weikl, Damien Schroeder, Walter Stechele
2020	A	`conf`	OrthrusPE: Runtime Reconfigurable Processing Elements for Binary Neural Networks. DATE Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele
2020	—	`conf`	Parameter Optimization of Approximate Image Processing Algorithms in FPGAs. CANDAR (Workshops) Nguyen Anh Vu Doan, Manu Manuel, Simon Conrady, Arne Kreddig, Walter Stechele
2019	—	`conf`	An Efficient FPGA Accelerator Design for Optimized CNNs Using OpenCL. ARCS Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele
2019	—	`conf`	DSC: Dense-Sparse Convolution for Vectorized Inference of Convolutional Neural Networks. CVPR Workshops Alexander Frickenstein, Manoj Rohit Vemparala, Christian Unger, Fatih Ayar, Walter Stechele
2019	—	`conf`	Deep Grid Fusion of Feature-Level Sensor Data with Convolutional Neural Networks. ICCVE Gábor Balázs, Walter Stechele
2019	—	`conf`	LCS-based automatic configuration of approximate computing parameters for FPGA system designs. GECCO (Companion) Simon Conrady, Manu Manuel, Arne Kreddig, Walter Stechele
2019	A*	`conf`	Mixed Frame-/Event-Driven Fast Pedestrian Detection. ICRA Zhuangyi Jiang, Pengfei Xia, Kai Huang, Walter Stechele, Guang Chen, Zhenshan Bing, Alois C. Knoll
2019	—	`conf`	Resource-Aware Optimization of DNNs for Embedded Applications. CRV Alexander Frickenstein, Christian Unger, Walter Stechele
2019	—	`conf`	Resource-Aware Parameter Tuning for Real-Time Applications. ARCS Dirk Gabriel, Walter Stechele, Stefan Wildermann
2018	A	`conf`	Efficient hardware acceleration of CNNs using logarithmic data representation with arbitrary log-base. ICCAD Sebastian Vogel, Mengyu Liang, Andre Guntoro, Walter Stechele, Gerd Ascheid
2017	—	`conf`	Hardware-accelerated CCD readout smear correction for Fast Solar Polarimeter. ASAP Stefan Tabel, Korbinian Weikl, Walter Stechele
2017	Misc	`conf`	Online Multi-object Tracking-by-Clustering for Intelligent Transportation System with Neuromorphic Vision Sensor. KI Gereon Hinz, Guang Chen, Muhammad Aafaque, Florian Röhrbein, Jörg Conradt, Zhenshan Bing, Zhongnan Qu, Walter Stechele, Alois C. Knoll
2017	J	`jnl`	Random Finite Set Based Bayesian Filtering with OpenCL in a Heterogeneous Platform. Sensors Biao Hu, Uzair Sharif, Rajat Koner, Guang Chen, Kai Huang, Feihu Zhang, Walter Stechele, Alois C. Knoll
2016	B	`ed.`	26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016 FPL Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele
2016	—	`conf`	A Chip-level Redundant Threading (CRT) scheme for shared-memory protection. HPCS Erol Koser, Korbinian Berthold, Ravi Kumar Pujari, Walter Stechele
2016	J	`jnl`	Adaptive tracking of people and vehicles using mobile platforms. EURASIP J. Adv. Signal Process. Haifa Ben Salem, Thyagaraju Damarla, Kishan Sudusinghe, Walter Stechele, Shuvra S. Bhattacharyya
2016	C	`conf`	Integrated Soft Error Resilience and Self-Test. VLSI-SoC Erol Koser, Sebastian Krosche, Walter Stechele
2016	J	`jnl`	Invasive computing for timing-predictable stream processing on MPSoCs. it Inf. Technol. Stefan Wildermann, Michael Bader, Lars Bauer, Marvin Damschen, Dirk Gabriel, Michael Gerndt, Michael Glaß, Jörg Henkel, Johny Paul, Alexander Pöppl, Sascha Roloff, Tobias Schwarzer, Gregor Snelting, Walter Stechele, Jürgen Teich, Andreas Weichslgartner, Andreas Zwinkau
2016	B	`conf`	Preface. FPL Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele
2016	—	`ed.`	Proceedings of the 1st International Workshop on RESource Awareness and Application Auto-tuning in Adaptive and heterogeNeous compuTing co-located with 19th International Conference on Design, Automation And Test In Europe (DATE 2016), Dresden, Germany, March 18th, 2016. RES4ANT@DATE Cristina Silvano, Walter Stechele, Stephan Wong, Jerónimo Castrillón, Michael Hübner, Amir Hossein Ashouri
2016	—	`conf`	Prototyping real-time tracking systems on mobile devices. Conf. Computing Frontiers Kyunghun Lee, Haifa Ben Salem, Thyagaraju Damarla, Walter Stechele, Shuvra S. Bhattacharyya
2016	—	`conf`	Special session 1 automotive parallel computing challenges - architectures, applications and tricks. DASIP Walter Stechele, Tomasz Kryjak, Lionel Lacassagne, Dominique Houzet, Martin Danek
2016	C	`conf`	Tackling long duration transients in sequential logic. IOLTS Erol Koser, Walter Stechele
2016	—	`conf`	Voltage over-scaling in sequential circuits for approximate computing. DTIS David May, Walter Stechele
2015	—	`conf`	A soft-core processor array for relational operators. ASAP Raphael Polig, Heiner Giefers, Walter Stechele
2015	A	`conf`	Design of fine-grained sequential approximate circuits using probability-aware fault emulation. ISLPED David May, Walter Stechele
2015	—	`conf`	Improving wavelet denoising based on an in-depth analysis of the camera color processing. Real-Time Image and Video Processing Tamara Seybold, Mathias Plichta, Walter Stechele
2015	C	`conf`	Matching Detection and Correction Schemes for Soft Error Handling in Sequential Logic. DSD Erol Koser, Felix Miller, Walter Stechele
2015	—	`conf`	Predictability of image processing algorithms on heterogeneous MPSoC. ESTIMedia Johny Paul, Walter Stechele
2015	—	`conf`	Protecting FPGA-based automotive systems against soft errors through reduced precision redundancy. SIES Walter Stechele
2015	J	`jnl`	Resource-awareness on heterogeneous MPSoCs for image processing. J. Syst. Archit. Johny Paul, Walter Stechele, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat, Manfred Kröhnert, Tamim Asfour, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Artjom Grudnitsky, Lars Bauer, Jörg Henkel
2015	J	`jnl`	Self-adaptive corner detection on MPSoC through resource-aware programming. J. Syst. Archit. Johny Paul, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Manfred Kröhnert, Daniel Lohmann, Walter Stechele, Tamim Asfour, Wolfgang Schröder-Preikschat
2015	J	`jnl`	Self-reconfigurable control architecture for complex mobile robots. it Inf. Technol. Jan Frost, Walter Stechele, Erik Maehle
2014	—	`ed.`	ARCS 2014 - 27th International Conference on Architecture of Computing Systems, Workshop Proceedings, February 25-28, 2014, Luebeck, Germany, University of Luebeck, Institute of Computer Engineering ARCS Workshops Walter Stechele, Thomas Wild
2014	C	`conf`	Automatic denoising parameter estimation using gradient histograms. VCIP Tamara Seybold, Florian Kuhn, Julian Habigt, Mark Hartenstein, Walter Stechele
2014	J	`jnl`	Beyond Standard Noise Models: Evaluating Denoising Algorithms with Respect to Realistic Camera Noise. Int. J. Semantic Comput. Tamara Seybold, Marion Knopp, Christian Keimel, Walter Stechele
2014	—	`conf`	Improving Efficiency of Embedded Multi-core Platforms with Scratchpad Memories. ARCS Workshops Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour
2014	C	`conf`	Improving the significance of probabilistic circuit fault emulations. IOLTS David May, Walter Stechele
2014	—	`conf`	Noise characteristics of a single sensor camera in digital color image processing. CIC Tamara Seybold, Özlem Cakmak, Christian Keimel, Walter Stechele
2014	J	`jnl`	Resource Prediction for Humanoid Robots. CoRR Manfred Kröhnert, Nikolaus Vahrenkamp, Johny Paul, Walter Stechele, Tamim Asfour
2014	—	`conf`	Resource-Aware Harris Corner Detection Based on Adaptive Pruning. ARCS Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat
2014	J	`jnl`	Resource-Aware Programming for Robotic Vision. CoRR Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour
2014	—	`conf`	Self-adaptive harris corner detector on heterogeneous many-core processor. DASIP Johny Paul, Walter Stechele, Éricles Sousa, Vahid Lari, Frank Hannig, Jürgen Teich, Manfred Kröhnert, Tamim Asfour
2014	C	`conf`	Towards low-cost fault detection strategy of FPGA configuration memory in real-time systems. IOLTS Michael Frischke, Andreas J. Rohatschek, Walter Stechele
2013	C	`conf`	A Design Space Exploration Framework For Automotive Embedded Systems And Their Power Management. ECMS Gregor Walla, Zaur Molotnikov, Hans-Ulrich Michel, Walter Stechele, Andreas Barthels, Andreas Herkersdorf
2013	—	`conf`	A resource-aware nearest-neighbor search algorithm for k-dimensional trees. DASIP Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour, Benjamin Oechslein, Christoph Erhardt, Jens Schedel, Daniel Lohmann, Wolfgang Schröder-Preikschat
2013	B	`conf`	A resource-efficient probabilistic fault simulator. FPL David May, Walter Stechele
2013	C	`conf`	Dynamic Noise Estimation Approach for X-Ray Detectors on FPGAs. DSD Florian Aschauer, Walter Stechele, Johannes Treis
2013	—	`conf`	Evaluation of hop count advantages of network-coded 2D-mesh NoCs. PATMOS Michael Vonbun, Stefan Wallentowitz, Michael Feilen, Walter Stechele, Andreas Herkersdorf
2013	C	`conf`	FPGA Based Real-Time Data Processing DAQ System for the Mercury Imaging X-Ray Spectrometer. DSD Florian Aschauer, Walter Stechele, Johannes Treis
2013	—	`conf`	Potentials and Challenges for Multi-Core Processors in Robotic Applications. GI-Jahrestagung Andreas Herkersdorf, Johny Paul, Ravi Kumar Pujari, Walter Stechele, Stefan Wallentowitz, Thomas Wild, Aurang Zaib
2013	—	`conf`	RTL Simulation of High Performance Dynamic Reconfiguration: A Video Processing Case Study. IPDPS Workshops Lingkan Gong, Oliver Diessel, Johny Paul, Walter Stechele
2013	J	`jnl`	Real-time motion detection based on SW/HW-codesign for walking rescue robots. J. Real Time Image Process. Johny Paul, Andreas Laika, Christopher Claus, Walter Stechele, Adam El Sayed Auf, Erik Maehle
2013	—	`conf`	Self-adaptation for Mobile Robot Algorithms Using Organic Computing Principles. ARCS Jan Hartmann, Walter Stechele, Erik Maehle
2013	—	`conf`	Self-reconfigurable Control Architecture for Complex Robots. GI-Jahrestagung Jan Hartmann, Walter Stechele, Erik Maehle
2013	C	`conf`	Towards an Evaluation of Denoising Algorithms with Respect to Realistic Camera Noise. ISM Tamara Seybold, Christian Keimel, Marion Knopp, Walter Stechele
2013	B	`conf`	Weighted partitioning of sequential processing chains for dynamically reconfigurable FPGAS. FPL Michael Feilen, Andreas Iliopoulos, Michael Vonbun, Walter Stechele
2012	—	`conf`	A Real-Time Capable Virtualized Information and Communication Technology Infrastructure for Automotive Systems. Advances in Real-Time Systems Sebastian Drössler, Michael Eichhorn, S. Holzknecht, Bernd Müller-Rathgeber, Holm Rauchfuss, Michael Zwick, Erwin M. Biebl, Klaus Diepold, Jörg Eberspächer, Andreas Herkersdorf, Walter Stechele, Eckehard G. Steinbach, R. Freymann, Karl-Ernst Steinberg, Hans-Ulrich Michel
2012	C	`conf`	A low-overhead monitoring ring interconnect for MPSoC parameter optimization. DDECS Abdelmajid Bouajila, Abdallah Lakhtel, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf
2012	—	`conf`	An FPGA-based probability-aware fault simulator. ICSAMOS David May, Walter Stechele
2012	—	`conf`	An evaluation on using GPU coprocessing for software radios on a low-cost platform. DASIP Lothar Stolz, Matthias Ihmig, Walter Stechele
2012	B	`conf`	Efficient DVB-T2 decoding accelerator design by time-multiplexing FPGA resources. FPL Michael Feilen, Matthias Ihmig, Christian Schwarzbauer, Walter Stechele
2012	—	`conf`	Invasive Computing for robotic vision. ASP-DAC Johny Paul, Walter Stechele, Manfred Kröhnert, Tamim Asfour, Rüdiger Dillmann
2012	—	`conf`	Partial Reconfiguration on FPGAs in Practice - Tools and Applications. ARCS Workshops Dirk Koch, Jim Tørresen, Christian Beckhoff, Daniel Ziener, Christopher Dennl, Volker Breuer, Jürgen Teich, Michael Feilen, Walter Stechele
2012	—	`conf`	Partitioning and context switching for a reconfigurable FPGA-based DAB receiver. DASIP Michael Feilen, Andreas Iliopoulos, Matthias Ihmig, Walter Stechele
2011	—	`conf`	A Model-Based Software Generation Approach Qualified for Heterogeneous GPGPU-Enabled Platforms. PARCO Holger Endt, Lothar Stolz, Martin Wechs, Walter Stechele
2011	A	`conf`	A reasoning approach to enable abductive semantic explanation upon collected observations for forensic visual surveillance. ICME Seunghan Han, Andreas Hutter, Walter Stechele
2011	—	`conf`	An approach to self-learning multicore reconfiguration management applied on Robotic Vision. DASIP Walter Stechele, Jan Hartmann, Erik Maehle
2011	C	`conf`	An architecture and an FPGA prototype of a reliable processor pipeline towards multiple soft- and timing errors. DDECS Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf
2011	—	`ch.`	Applying ASoC to Multi-core Applications for Workload Management. Organic Computing Johannes Zeppenfeld, Abdelmajid Bouajila, Walter Stechele, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Andreas Herkersdorf
2011	—	`ch.`	Autonomic System on Chip Platform. Organic Computing Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Andreas Herkersdorf
2011	J	`jnl`	Default Reasoning for Forensic Visual Surveillance based on Subjective Logic and Its Comparison with L-Fuzzy Set Based Approaches. Int. J. Multim. Data Eng. Manag. Seunghan Han, Walter Stechele
2011	—	`conf`	Egomotion compensation and moving objects detection algorithm on GPU. PARCO Juan Gómez-Luna, Holger Endt, Walter Stechele, José María González-Linares, José Ignacio Benavides, Nicolás Guil
2010	A	`conf`	A rapid prototyping system for error-resilient multi-processor systems-on-chip. DATE Matthias May, Norbert Wehn, Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Daniel Ziener, Jürgen Teich
2010	C	`conf`	Architectural Vulnerability Factor Estimation with Backwards Analysis. DSD Robert Hartl, Andreas J. Rohatschek, Walter Stechele, Andreas Herkersdorf
2010	—	`ch.`	AutoVision - Reconfigurable Hardware Acceleration for Video-Based Driver Assistance. Dynamically Reconfigurable Systems Christopher Claus, Walter Stechele
2010	—	`conf`	Forensic reasoning upon pre-obtained surveillance metadata using uncertain spatio-temporal rules and subjective logic. WIAMIS Seunghan Han, Bonjung Koo, Andreas Hutter, Walter Stechele
2010	—	`conf`	Lessons Learned from last 4 Years of Reconfigurable Computing. Dynamically Reconfigurable Architectures Walter Stechele, Christopher Claus, Andreas Laika
2010	—	`conf`	Stereo Vision based Vehicle Detection. VISAPP (2) Benjamin Kormann, Antje Neve, Gudrun Klinker, Walter Stechele
2010	—	`conf`	Subjective Logic Based Approach to Modeling Default Reasoning for Visual Surveillance. ICSC Seunghan Han, Bonjung Koo, Walter Stechele
2010	B	`conf`	Subjective Logic Based Hybrid Approach to Conditional Evidence Fusion for Forensic Visual Surveillance. AVSS Seunghan Han, Bonjung Koo, Andreas Hutter, Vinay D. Shet, Walter Stechele
2010	—	`conf`	Towards Rapid Dynamic Partial Reconfiguration in Video-Based Driver Assistance Systems. ARC Christopher Claus, Rehan Ahmed, Florian Altenried, Walter Stechele
2010	—	`conf`	Towards Scalability and Reliability of Autonomic Systems on Chip. ISORC Workshops Johannes Zeppenfeld, Abdelmajid Bouajila, Andreas Herkersdorf, Walter Stechele
2009	B	`conf`	Optimizing the SUSAN corner detection algorithm for a high speed FPGA implementation. FPL Christopher Claus, Robert Huitl, Joachim Rausch, Walter Stechele
2009	—	`conf`	Segmentation Through Edge-linking - Segmentation for Video-based Driver Assistance Systems. IMAGAPP Andreas Laika, Adrian Taruttis, Walter Stechele
2009	—	`conf`	Toward contextual forensic retrieval for visual surveillance: Challenges and an architectural approach. WIAMIS Seunghan Han, Andreas Hutter, Walter Stechele
2009	J	`jnl`	Wire Topology Optimization for Low Power CMOS. IEEE Trans. Very Large Scale Integr. Syst. Paul Zuber, Othman Bahlous, Thomas Ilnseher, Michael Ritter, Walter Stechele
2008	B	`conf`	A comparison of embedded reconfigurable video-processing architectures. FPL Christopher Claus, Walter Stechele, Matthias Kovatsch, Josef Angermeier, Jürgen Teich
2008	B	`conf`	A multi-platform controller allowing for maximum Dynamic Partial Reconfiguration throughput. FPL Christopher Claus, Bin Zhang, Walter Stechele, Lars Braun, Michael Hübner, Jürgen Becker
2008	A	`conf`	Design Flows, Communication Based Design and Architectures in Automotive Electronic Systems. DATE Jürgen Becker, Michael Hübner, Robert Esser, Andreas Herkersdorf, Walter Stechele, Vera Lauer
2008	B	`conf`	Fine grain reconfigurable architectures. FPL Josef Angermeier, Mateusz Majer, Jürgen Teich, Lars Braun, Tobias Schwalb, Philipp Graf, Michael Hübner, Jürgen Becker, Enno Lübbers, Marco Platzner, Christopher Claus, Walter Stechele, Andreas Herkersdorf, Markus Rullmann, Renate Merker
2008	A	`conf`	Hardware/software architecture of an algorithm for vision-based real-time vehicle detection in dark environments. DATE Nicolas Alt, Christopher Claus, Walter Stechele
2008	—	`conf`	Learning Classifier Tables for Autonomic Systems on Chip. GI Jahrestagung (2) Johannes Zeppenfeld, Abdelmajid Bouajila, Walter Stechele, Andreas Herkersdorf
2008	—	`conf`	Luminance Correction in Stereo Correspondence Based Structure from Motion. WIAMIS Colin Estermann, Walter Stechele, Robert Kutka, Andreas Hutter
2008	—	`conf`	Reconfigurable HW/SW Architecture of a Real-Time Driver Assistance System. ARC Josef Angermeier, Ulrich Batzer, Mateusz Majer, Jürgen Teich, Christopher Claus, Walter Stechele
2008	—	`conf`	Workshop "Adaptive and Organic Systems". GI Jahrestagung (2) Andreas Herkersdorf, Walter Stechele, Christian Müller-Schloer, Hartmut Schmeck
2007	J	`jnl`	A Coprocessor for Accelerating Visual Information Processing CoRR Walter Stechele, L. Alvado Cárcel, Stephan Herrmann, J. Lidón Simón
2007	A	`conf`	A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration. IPDPS Christopher Claus, Florian Helmut Müller, Johannes Zeppenfeld, Walter Stechele
2007	—	`conf`	A review of different object recognition methods for the application in driver assistance systems. WIAMIS Andreas Laika, Walter Stechele
2007	J	`jnl`	Autovision - A Run-time Reconfigurable MPSoC Architecture for Future Driver Assistance Systems (Autovision - Eine zur Laufzeit rekonfigurierbare MPSoC Architektur für zukünftige Fahrerassistenzsysteme). it Inf. Technol. Christopher Claus, Walter Stechele, Andreas Herkersdorf
2007	—	`conf`	Physical Configuration On-Line Visualization of Xilinx Virtex-II FPGAs. ISVLSI Michael Hübner, Lars Braun, Jürgen Becker, Christopher Claus, Walter Stechele
2007	A	`conf`	Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance system. DATE Christopher Claus, Johannes Zeppenfeld, Florian Helmut Müller, Walter Stechele
2006	—	`conf`	An Architecture for Runtime Evaluation of SoC Reliability. GI Jahrestagung (1) Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel, Abdelmajid Bouajila, Walter Stechele, Andreas Herkersdorf
2006	A	`conf`	AutoVision: flexible processor architecture for video-assisted driving. DATE Andreas Herkersdorf, Walter Stechele
2006	—	`conf`	Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro. ARCS Workshops Christopher Claus, Florian Helmut Müller, Walter Stechele
2006	—	`conf`	Dynamically Reconfigurable Systems-on-Chip. Dynamically Reconfigurable Architectures Walter Stechele
2006	—	`conf`	Error Detection Techniques Applicable in an Architecture Framework and Design Methodology for Autonomic SoCs. BICC Abdelmajid Bouajila, Andreas Bernauer, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, Walter Stechele
2006	—	`conf`	Multithreaded virtual-memory-enabled reconfigurable hardware accelerators. FPT Miljan Vuletic, Paolo Ienne, Christopher Claus, Walter Stechele
2006	C	`conf`	Organic Computing at the System on Chip Level. VLSI-SoC Abdelmajid Bouajila, Johannes Zeppenfeld, Walter Stechele, Andreas Herkersdorf, Andreas Bernauer, Oliver Bringmann, Wolfgang Rosenstiel
2005	A	`conf`	A Coprocessor for Accelerating Visual Information Processing. DATE Walter Stechele, L. Alvado Cárcel, Stephan Herrmann, J. Lidón Simón
2005	—	`conf`	Optimization Potential of CMOS Power by Wire Spacing. GI Jahrestagung (1) Paul Zuber, Florian Helmut Müller, Walter Stechele
2005	A	`conf`	Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization. DATE Paul Zuber, Armin Windschiegl, Raúl Medina Beltrán de Otálora, Walter Stechele, Andreas Herkersdorf
2005	—	`conf`	The Optimal Wire Order for Low Power CMOS. PATMOS Paul Zuber, Peter Gritzmann, Michael Ritter, Walter Stechele
2005	—	`conf`	Towards a Framework and a Design Methodology for Autonomic SoC. ICAC Gabriel Mihai Lipsa, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, Walter Stechele
2005	—	`conf`	Towards a Framework and a Design Methodology for Autonomous SoC. ARCS Workshops Gabriel Mihai Lipsa, Andreas Herkersdorf, Wolfgang Rosenstiel, Oliver Bringmann, Walter Stechele
2004	—	`conf`	Towards a Dynamically Reconfigurable System-on-Chip Platform for Video Signal Processing. ARCS Workshops Walter Stechele, Stephan Herrmann, Andreas Herkersdorf
2003	—	`conf`	Performance Optimization of Color Segmentation Algorithms. SIP Walter Stechele
2002	—	`conf`	A wire load model considering metal layer properties. ICECS Armin Windschiegl, Torsten Mahnke, Michael Eiermann, Walter Stechele, Paul Zuber
2002	—	`conf`	An MPEG-7 tool for compression and streaming of XML data. ICME (1) Ulrich Niedermeier, Jörg Heuer, Andreas Hutter, Walter Stechele, André Kaup
2002	—	`conf`	Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment. PATMOS Torsten Mahnke, Walter Stechele, Wolfgang Hoeld
2002	—	`conf`	Efficiency of dual supply voltage logic synthesis for low power in consideration of varying delay constraint strictness. ICECS Torsten Mahnke, Sebastian Panenka, Martin Embacher, Walter Stechele, Wolfgang Hoeld
2002	—	`conf`	Efficient power modeling techniques for combinational and sequential RTL macroblocks. ICECS Michael Eiermann, Walter Stechele
2002	—	`conf`	Exploiting Metal Layer Characteristics for Low-Power Routing. PATMOS Armin Windschiegl, Paul Zuber, Walter Stechele
2002	—	`conf`	Impact of technology evolution on dual supply voltage scaling and gate resizing in power-driven logic synthesis. ICECS Torsten Mahnke, Walter Stechele, Martin Embacher, Wolfgang Hoeld
2002	B	`conf`	MPEG-7 Binary Format for XML Dat. DCC Ulrich Niedermeier, Jörg Heuer, Andreas Hutter, Walter Stechele
2002	A	`conf`	Novel modeling techniques for RTL power estimation. ISLPED Michael Eiermann, Walter Stechele
2000	C	`conf`	A coprocessor architecture implementing the MPEG-4 visual core profile for mobile multimedia applications. ISCAS Andreas Hutter, Georg Giebel, Walter Stechele
1999	J	`jnl`	A video segmentation algorithm for hierarchical object representations and its implementation. IEEE Trans. Circuits Syst. Video Technol. Stephan Herrmann, Hubert Mooshofer, Harald Dietrich, Walter Stechele
1997	—	`conf`	A flexible VLSI architecture for variable block size segment matching with luminance correction. ASAP Peter M. Kuhn, Andreas Weisgerber, Robert Poppenwimmer, Walter Stechele