Walter Anheier

35 papers A 1B 1C 6Misc 4Journal 5Unranked 16

Year	Rank	Type	Title / Venue / Authors
2016	J	`jnl`	Genetic-Algorithm-based Test Pattern Generation for Crosstalk Faults between On-Chip Aggressor and Victim. J. Circuits Syst. Comput. Kishore K. Duganapalli, Ajoy Kumar Palit, Walter Anheier
2015	C	`conf`	TPG for Crosstalk Faults between On-Chip Aggressor and Victim Using Genetic Algorithms. DDECS Kishore K. Duganapalli, Ajoy Kumar Palit, Walter Anheier
2010	—	`ch.`	Efficient Training Algorithm for Neuro-Fuzzy Network and its Application to Nonlinear Sensor Characteristic Linearization. Intelligent Systems for Automated Learning and Adaptation Ajoy Kumar Palit, Walter Anheier
2010	C	`conf`	Fault diagnosis of crosstalk induced glitches and delay faults. DDECS Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier
2010	Misc	`conf`	Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults. VLSI Design Shehzad Hasan, Ajoy Kumar Palit, Walter Anheier
2009	—	`ch.`	Electrical Load Forecasting Using a Neural-Fuzzy Approach. Natural Intelligence for Scheduling, Planning and Packing Problems Ajoy Kumar Palit, Walter Anheier, Dobrivoje Popovic
2009	A	`conf`	Timing Arc based logic analysis for false noise reduction. ICCAD Murthy Palla, Jens Bargfrede, Stephan Eggersglüß, Walter Anheier, Rolf Drechsler
2008	—	`conf`	Adaptive Branch and Bound Using SAT to Estimate False Crosstalk. ISQED Murthy Palla, Jens Bargfrede, Klaus Koch, Walter Anheier, Rolf Drechsler
2008	J	`jnl`	Crosstalk fault modeling in defective pair of interconnects. Integr. Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier
2007	C	`conf`	XSIM: An Efficient Crosstalk Simulator for Analysis and Modeling of Signal Integrity Faults in Both Defective and Defect-free Interconnects. DDECS Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier
2006	—	`conf`	Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects. DFT Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier
2006	—	`conf`	Modeling of Crosstalk Fault in Defective Interconnects. PATMOS Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier
2006	C	`conf`	Reduction of Crosstalk Pessimism using Tendency Graph Approach. ICCD Murthy Palla, Klaus Koch, Jens Bargfrede, Manfred Glesner, Walter Anheier
2006	—	`conf`	Vergleich und Optimierung von Algorithmen zur Modulo-Multiplikation auf Smartcards. MBMV Sascha Kneip, Walter Anheier
2005	—	`conf`	A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips. Asian Test Symposium Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel
2005	Misc	`conf`	ABCD Modeling of Crosstalk Coupling Noise to Analyze the Signal Integrity Losses on the Victim Interconnect in DSM Chips. VLSI Design Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel
2004	—	`conf`	Modeling and Analysis of Crosstalk Coupling Effect on the Victim Interconnect Using the ABCD Network Model. DFT Ajoy Kumar Palit, Volker Meyer, Walter Anheier, Jürgen Schlöffel
2002	B	`conf`	Backpropagation based training algorithm for Takagi-Sugeno type MIMO neuro-fuzzy network to forecast electrical load time series. FUZZ-IEEE Ajoy Kumar Palit, Gerhard Doeding, Walter Anheier, Dobrivoje Popovic
2002	—	`conf`	Non-robust delay test pattern enhancement. ICECS Volker Meyer, Walter Anheier, Arne Sticht
2001	—	`conf`	Integer division in residue number system. ICECS Badreddine Rejeb, Heiko Henkelmann, Walter Anheier
2001	—	`conf`	Investigations of on-line/off-line tests for sensors. ICECS Michael Fischell, Walter Anheier
2001	—	`conf`	Non-robust delay test pattern generation based on stuck-at TPG. ICECS Volker Meyer, Walter Anheier, Arne Sticht
2000	J	`jnl`	On Random Pattern Testability of Cryptographic VLSI Cores. J. Electron. Test. Andreas Schubert, Walter Anheier
1999	—	`conf`	Efficient VLSI implementation of modern symmetric block ciphers. ICECS Andreas Schubert, Walter Anheier
1999	—	`conf`	Effiziente Methoden zum Zahlenvergleich und zur Vorzeichenerkennung in Restklassensystemen. MBMV Heiko Henkelmann, C. Bruennlein, Walter Anheier
1999	—	`conf`	Implementation of sign detection in RNS using mixed radix representation. ICECS Heiko Henkelmann, Walter Anheier
1999	—	`conf`	On random pattern testability of cryptographic VLSI cores. ETW Andreas Schubert, Walter Anheier
1999	J	`jnl`	Quality Determination for Gate Delay Fault Tests Considering Three-State Elements. J. Electron. Test. Frank Poehl, Walter Anheier
1998	Misc	`conf`	A Residue Number Arithmetic based Circuit for Pipelined Computation of Autocorrelation Coefficients of Speech Signal. VLSI Design Ansgar Drolshagen, Walter Anheier, C. Chandra Sekhar
1997	—	`conf`	Processor Elements for the Standard Cell Implementation of Residue Number Systems. ASAP Ansgar Drolshagen, Heiko Henkelmann, Walter Anheier
1995	C	`conf`	Distributed automatic test pattern generation with a parallel FAN algorithm. ICCD Stefan Radtke, Jens Bargfrede, Walter Anheier
1994	C	`conf`	A New Strategy for Test Pattern Generation in Sequential Circuits. ISCAS Beom-Ik Cheon, Walter Anheier, Rainer Laur
1994	J	`jnl`	An image analysis system for automatic data acquisition from colored scanned maps. Mach. Vis. Appl. Norbert Ebi, Bernd Lauterbach, Walter Anheier
1994	Misc	`conf`	Segmentation of Scanned Maps in Uniform Color Spaces. MVA Bernd Lauterbach, Walter Anheier
1993	—	`conf`	Segmentierung farbiger kartographischer Vorlagen in empfindungsgemäßen Farbräumen. DAGM-Symposium B. Lauerbach, Walter Anheier