Wai-Shing Luk

36 papers A* 1A 4B 1C 1Journal 14Unranked 15
YearRankTypeTitle / Venue / Authors
2026 J jnl
LOFMPL: An Open-source Logic Optimization Framework with MFFC-based Hypergraph Partition and Reinforcement Learning for Large Circuits.
ACM Trans. Design Autom. Electr. Syst.
Kaixiang Zhu, Zhen Li, Jide Zhang, Wai-Shing Luk, Lingli Wang
2026 — conf
Novel Multi-Corner Delay Padding using Path Relationship Analysis and Dual Decomposition.
ASP-DAC
Kaixiang Zhu, Jiangnan Li, Lingli Wang, Wai-Shing Luk
2026 — conf
UltraMalloc: Efficient FPGA-based Memory Allocation Framework Optimized for HBM.
ASP-DAC
Yuwei Qu, Yiqing Mao, Yanxing Jin, Wai-Shing Luk, Lingli Wang
2025 J jnl
COFFA: A Co-Design Framework for Fused-Grained Reconfigurable Architecture Towards Efficient Irregular Loop Handling.
IEEE Trans. Computers
Yuan Dai, Xuchen Gao, Yunhui Qiu, Jingyuan Li, Yuhang Cao, Yiqing Mao, Sichao Chen, Wenbo Yin, Wai-Shing Luk, Lingli Wang
2025 — conf
Towards Efficient Data Parallelism on Spatial CGRA via Constraint Satisfaction and Graph Coloring.
ASP-DAC
Yuan Dai, Xuchen Gao, Chen Shen, Bingbing Peng, Wenbo Yin, Wai-Shing Luk, Lingli Wang
2025 — conf
Yield-driven Clock Skew Scheduling Based on Generalized Extreme Value Distribution.
ASP-DAC
Kaixiang Zhu, Wai-Shing Luk, Lingli Wang
2024 B conf
CFEACT: A CGRA-based Framework Enabling Agile CNN and Transformer Accelerator Design.
FPL
Yiqing Mao, Xuchen Gao, Jiahang Lou, Yunhui Qiu, Wenbo Yin, Wai-Shing Luk, Lingli Wang
2024 — conf
FPGA Routing Optimization Based on Multi-Level MUX Architecture.
ICFPT
Xizheng Li, Kaichuang Shi, Wai-Shing Luk, Hao Zhou, Lingli Wang
2024 — conf
HBMalloc: Dynamic Memory Management in High-Level Synthesis for FPGA HBM.
ICFPT
Yiqing Mao, Yanxing Jin, Wai-Shing Luk, Lingli Wang
2024 — conf
MDCRA: A Reconfigurable Accelerator Framework for Multiple Dataflow Lanes.
ASAP
Shaoyang Sun, Boyin Jin, Jiahang Lou, Jiangnan Li, Yuhang Cao, Jingyuan Li, Chen Shen, Yuan Dai, Wenbo Yin, Wai-Shing Luk, Lingli Wang
2021 — conf
LETA: A lightweight exchangeable-track accelerator for efficientnet based on FPGA.
FPT
Jingbo Gao, Yu Qian, Yihan Hu, Xitian Fan, Wai-Shing Luk, Wei Cao, Lingli Wang
2020 J jnl
FULL-KV: Flexible and Ultra-Low-Latency In-Memory Key-Value Store System Design on CPU-FPGA.
IEEE Trans. Parallel Distributed Syst.
Yunhui Qiu, Jinyu Xie, Hankun Lv, Wenbo Yin, Wai-Shing Luk, Lingli Wang, Bowei Yu, Hua Chen, Xianjun Ge, Zhijian Liao, Xiaozhong Shi
2018 J jnl
Cut Redistribution and Insertion for Advanced 1-D Layout Design via Network Flow Optimization.
IEEE Trans. Very Large Scale Integr. Syst.
Ye Zhang, Wenlong Lyu, Wai-Shing Luk, Fan Yang, Hai Zhou, Dian Zhou, David Z. Pan, Xuan Zeng
2017 J jnl
An Effective Layout Decomposition Method for DSA with Multiple Patterning in Contact-Hole Generation.
ACM Trans. Design Autom. Electr. Syst.
Yunfeng Yang, Wai-Shing Luk, Hai Zhou, David Z. Pan, Dian Zhou, Changhao Yan, Xuan Zeng
2017 C conf
Layout decomposition for hybrid E-beam and DSA double patterning lithography.
ISCAS
Yunfeng Yang, Fan Yang, Wai-Shing Luk, Changhao Yan, Xuan Zeng, Xiangdong Hu
2017 — conf
Network flow based cut redistribution and insertion for advanced 1D layout design.
ASP-DAC
Ye Zhang, Wai-Shing Luk, Fan Yang, Changhao Yan, Hai Zhou, Dian Zhou, Xuan Zeng
2016 J jnl
Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Yunfeng Yang, Wai-Shing Luk, David Z. Pan, Hai Zhou, Changhao Yan, Dian Zhou, Xuan Zeng
2015 J jnl
Layout Decomposition with Pairwise Coloring and Adaptive Multi-Start for Triple Patterning Lithography.
ACM Trans. Design Autom. Electr. Syst.
Ye Zhang, Wai-Shing Luk, Yunfeng Yang, Hai Zhou, Changhao Yan, David Z. Pan, Xuan Zeng
2015 — conf
Layout decomposition co-optimization for hybrid e-beam and multiple patterning lithography.
ASP-DAC
Yunfeng Yang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng, Dian Zhou
2015 J jnl
Multi-parameter clock skew scheduling.
Integr.
Xingbao Zhou, Wai-Shing Luk, Hai Zhou, Fan Yang, Changhao Yan, Xuan Zeng
2013 A conf
Layout decomposition with pairwise coloring for multiple patterning lithography.
ICCAD
Ye Zhang, Wai-Shing Luk, Hai Zhou, Changhao Yan, Xuan Zeng
2013 J jnl
SmipRef: An efficient method for multi-domain clock skew scheduling.
Integr.
Yanling Zhi, Wai-Shing Luk, Hai Zhou, Xuan Zeng
2012 J jnl
Yield-Driven Clock Skew Scheduling for Arbitrary Distributions of Critical Path Delays.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Yanling Zhi, Wai-Shing Luk, Yi Wang, Changhao Yan, Xuan Zeng
2011 A conf
An efficient algorithm for multi-domain clock skew scheduling.
DATE
Yanling Zhi, Wai-Shing Luk, Hai Zhou, Changhao Yan, Hengliang Zhu, Xuan Zeng
2010 A conf
Fast and lossless graph division method for layout decomposition using SPQR-tree.
ICCAD
Wai-Shing Luk, Huiping Huang
2009 J jnl
Characterizing Intra-Die Spatial Correlation Using Spectral Density Fitting Method.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Qiang Fu, Wai-Shing Luk, Jun Tao, Changhao Yan, Xuan Zeng
2009 J jnl
Intra-Die Spatial Correlation Extraction with Maximum Likelihood Estimation Method for Multiple Test Chips.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Qiang Fu, Wai-Shing Luk, Jun Tao, Xuan Zeng, Wei Cai
2008 — conf
Characterizing Intra-Die Spatial Correlation Using Spectral Density Method.
ISQED
Qiang Fu, Wai-Shing Luk, Jun Tao, Changhao Yan, Xuan Zeng
2008 A* conf
Timing yield driven clock skew scheduling considering non-Gaussian distributions of critical path delays.
DAC
Yi Wang, Wai-Shing Luk, Xuan Zeng, Jun Tao, Changhao Yan, Jiarong Tong, Wei Cai, Jia Ni
2007 — conf
Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic.
ASP-DAC
Xuexin Liu, Wai-Shing Luk, Yu Song, Pushan Tang, Xuan Zeng
2007 — conf
WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design.
ASP-DAC
Peng Zhang, Wai-Shing Luk, Yu Song, Jiarong Tong, Pushan Tang, Xuan Zeng
1997 J jnl
Sampling with Hammersley and Halton Points.
J. Graphics, GPU, & Game Tools
Tien-Tsin Wong, Wai-Shing Luk, Pheng-Ann Heng
1997 A conf
Two New Quorum Based Algorithms for Distributed Mutual Exclusion.
ICDCS
Wai-Shing Luk, Tien-Tsin Wong
1997 J jnl
Waveform Krylov Subspace Methods on a Massively Parallel Computer.
Int. J. High Speed Comput.
Wai-Shing Luk, Omar Wing
1995 — conf
The Use of Inexact ODE Solver in Waveform Relaxation Methods on a Massively Parallel Computer.
PP
Wai-Shing Luk, Omar Wing
1994 — conf
Aberth's Method for the Parallel Iterative Finding of Polynomial Zeros.
APL
Tien Chi Chen, Wai-Shing Luk