Wai-Kei Mak - RankMe

98 papers A* 4A 14B 4C 2Journal 33Unranked 40

Year	Rank	Type	Title / Venue / Authors
2026	—	`conf`	A Scalable and High-Quality Qubit Mapping and Shuttling Framework for Neutral Atom Quantum Devices. ASP-DAC Sung-Ying Hsieh, Wai-Kei Mak
2026	—	`conf`	An Effective Placement Framework for Designs with Half-Row-Extended Cells. ASP-DAC Po-Yi Wu, Tzu-Sheng Hung, Wai-Kei Mak, Ting-Chi Wang
2026	J	`jnl`	An Efficient and Effective Optimization Algorithm for Buffer and Splitter Insertion in AQFP Circuits. ACM Trans. Design Autom. Electr. Syst. Bing-Huan Wu, Wai-Kei Mak
2026	—	`conf`	Timing-Aware End-to-End Circuit Compilation Framework for Modular Quantum Systems. ISPD Ching-Yao Huang, Wai-Kei Mak
2025	A	`conf`	An Efficient Routing Optimization Framework for Silicon-Based Spin-Qubit Devices. ICCAD Ching-Yao Huang, Wai-Kei Mak
2024	—	`conf`	A Bounding Box-based Net Partitioning Method for Double-sided Routing. ACM Great Lakes Symposium on VLSI Fang-Yu Hsu, Tzu-Chuan Lin, Wai-Kei Mak, Ting-Chi Wang
2024	A	`conf`	An Effective ECO Methodology for Reducing Back-side Design Rule Violations in Double-sided Signal Routing. ICCAD Che-Ping Tsai, Fang-Yu Hsu, Wai-Kei Mak, Ting-Chi Wang
2024	B	`conf`	An Effective Netlist Planning Approach for Double-sided Signal Routing. ASPDAC Tzu-Chuan Lin, Fang-Yu Hsu, Wai-Kei Mak, Ting-Chi Wang
2024	B	`conf`	CTQr: Control and Timing-Aware Qubit Routing. ASPDAC Ching-Yao Huang, Wai-Kei Mak
2024	J	`jnl`	Efficient Qubit Routing Using a Dynamically Extract-and-Route Framework. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ching-Yao Huang, Wai-Kei Mak
2024	—	`conf`	Optimization for Buffer and Splitter Insertion in AQFP Circuits with Local and Group Movement. ISPD Bing-Huan Wu, Wai-Kei Mak
2024	J	`jnl`	Placement Flow Study and Detailed Placement for Hybrid-Row-Height Designs. ACM Trans. Design Autom. Electr. Syst. Wei-Kai Fang, Wai-Kei Mak
2024	B	`conf`	Row Planning and Placement for Hybrid-Row-Height Designs. ASPDAC Ching-Yao Huang, Wai-Kei Mak
2023	J	`jnl`	Drain-to-Drain Abutment-Aware Detailed Placement Refinement for Power Staple Insertion Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Jin Xie, Wai-Kei Mak
2023	—	`conf`	Hybrid-Row-Height Design Placement Legalization Considering Cell Variants. ACM Great Lakes Symposium on VLSI Syuan-Han Liang, Tsu-Ling Hsiung, Wai-Kei Mak, Ting-Chi Wang
2022	A	`conf`	Generation of Mixed-Driving Multi-Bit Flip-Flops for Power Optimization. ICCAD Meng-Yun Liu, Yu-Cheng Lai, Wai-Kei Mak, Ting-Chi Wang
2022	—	`conf`	HybridGP: Global Placement for Hybrid-Row-Height Designs. ASP-DAC Kuan-Yu Chen, Hsiu-Chu Hsu, Wai-Kei Mak, Ting-Chi Wang
2022	—	`conf`	Linear-time Mixed-Cell-Height Legalization for Minimizing Maximum Displacement. ISPD Chung-Hsien Wu, Wai-Kei Mak, Chris Chu
2022	A	`conf`	Reinforcement Learning and DEAR Framework for Solving the Qubit Mapping Problem. ICCAD Ching-Yao Huang, Chi-Hsiang Lien, Wai-Kei Mak
2021	A	`conf`	A Novel Clock Tree Aware Placement Methodology for Single Flux Quantum (SFQ) Logic Circuits. ICCAD Ching-Cheng Wang, Wai-Kei Mak
2021	—	`conf`	Manufacturing-Aware Power Staple Insertion Optimization by Enhanced Multi-Row Detailed Placement Refinement. ASP-DAC Yu-Jin Xie, Kuan-Yu Chen, Wai-Kei Mak
2021	—	`conf`	Multiple-Layer Multiple-Patterning Aware Placement Refinement for Mixed-Cell-Height Designs. ISPD Bo-Yang Chen, Chi-Chun Fang, Wai-Kei Mak, Ting-Chi Wang
2021	J	`jnl`	Pin Assignment Optimization for Multi-2.5D FPGA-Based Systems With Time-Multiplexed I/Os. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Chen Liao, Wai-Kei Mak
2018	A	`conf`	A practical detailed placement algorithm under multi-cell spacing constraints. ICCAD Yu-Hsiang Cheng, Ding-wei Huang, Wai-Kei Mak, Ting-Chi Wang
2018	—	`conf`	Pin Assignment Optimization for Multi-2.5D FPGA-based Systems. ISPD Wan-Sin Kuo, Shi-Han Zhang, Wai-Kei Mak, Richard Sun, Yoon Kah Leow
2018	J	`jnl`	Self-Aligned Double Patterning-Aware Detailed Routing With Double Via Insertion and Via Manufacturability Consideration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yixiao Ding, Chris Chu, Wai-Kei Mak
2017	J	`jnl`	A routing framework for technology migration with bump encroachment. Integr. Po-Yi Wu, Wai-Kei Mak, Ting-Chi Wang, Cheng Zhuo, Kassan Unda, Yiyu Shi
2017	A	`conf`	Making split fabrication synergistically secure and manufacturable. ICCAD Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran
2017	A	`conf`	Making split fabrication synergistically secure and manufacturable. ICCAD Lang Feng, Yujie Wang, Jiang Hu, Wai-Kei Mak, Jeyavijayan Rajendran
2017	J	`jnl`	Minimum Implant Area-Aware Placement and Threshold Voltage Refinement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wai-Kei Mak, Wan-Sin Kuo, Shi-Han Zhang, Seong-I Lei, Chris Chu
2017	—	`conf`	Mixed-Cell-Height Standard Cell Placement Legalization. ACM Great Lakes Symposium on VLSI Chung-Yao Hung, Peng-Yi Chou, Wai-Kei Mak
2017	—	`conf`	Optimizing DSA-MP decomposition and redundant via insertion with dummy vias. ASP-DAC Chung-Yao Hung, Peng-Yi Chou, Wai-Kei Mak
2017	—	`conf`	Pin Accessibility-Driven Detailed Placement Refinement. ISPD Yixiao Ding, Chris Chu, Wai-Kei Mak
2017	J	`jnl`	Self-Aligned Double Patterning Lithography Aware Detailed Routing With Color Preassignment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yixiao Ding, Chris Chu, Wai-Kei Mak
2016	—	`conf`	Minimum implant area-aware placement and threshold voltage refinement. ASP-DAC Seong-I Lei, Wai-Kei Mak, Chris Chu
2016	J	`jnl`	Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seong-I Lei, Wai-Kei Mak
2016	A*	`conf`	Self-aligned double patterning-aware detailed routing with double via insertion and via manufacturability consideration. DAC Yixiao Ding, Chris C. N. Chu, Wai-Kei Mak
2015	—	`conf`	A fast parallel approach for common path pessimism removal. ASP-DAC Chung-Hao Tsai, Wai-Kei Mak
2015	A*	`conf`	Detailed routing for spacer-is-metal type self-aligned double/quadruple patterning lithography. DAC Yixiao Ding, Chris C. N. Chu, Wai-Kei Mak
2015	J	`jnl`	Flexible Packed Stencil Design With Multiple Shaping Apertures and Overlapping Shots for E-beam Lithography. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chris C. N. Chu, Wai-Kei Mak
2015	J	`jnl`	Highly Efficient and Effective Approach for Synchronization-Function-Level Parallel Multicore Instruction-Set Simulations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jyun-Hao Chang, Hsin-I Wu, Hsien-Lun Pai, Ren-Song Tsay, Wai-Kei Mak
2014	—	`conf`	A novel wirelength-driven packing algorithm for FPGAs with adaptive logic modules. ASP-DAC Sheng-Kai Wu, Po-Yi Hsu, Wai-Kei Mak
2014	—	`conf`	Double patterning-aware detailed routing with mask usage balancing. ISQED Seong-I Lei, Chris Chu, Wai-Kei Mak
2014	J	`jnl`	E-Beam Lithography Character and Stencil Co-Optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wai-Kei Mak, Chris Chu
2014	—	`conf`	Flexible packed stencil design with multiple shaping apertures for e-beam lithography. ASP-DAC Chris Chu, Wai-Kei Mak
2014	A*	`conf`	Throughput Optimization for SADP and E-beam based Manufacturing of 1D Layout. DAC Yixiao Ding, Chris Chu, Wai-Kei Mak
2013	—	`conf`	A separation and minimum wire length constrained maze routing algorithm under nanometer wiring rules. ASP-DAC Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen
2013	J	`jnl`	Fast Fixed-Outline 3-D IC Floorplanning With TSV Co-Placement. IEEE Trans. Very Large Scale Integr. Syst. Cha-Ru Li, Wai-Kei Mak, Ting-Chi Wang
2013	J	`jnl`	MANA: A Shortest Path Maze Algorithm Under Separation and Minimum Length NAnometer Rules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak, Sheng-Hsiung Chen
2013	J	`jnl`	Simultaneous Constrained Pin Assignment and Escape Routing Considering Differential Pairs for FPGA-PCB Co-Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Seong-I Lei, Wai-Kei Mak
2012	J	`jnl`	ALMmap: Technology Mapping for FPGAs With Adaptive Logic Modules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Yi Liang, Tien-Yu Kuo, Shao-Huan Wang, Wai-Kei Mak
2012	J	`jnl`	ISPD11: Power-Driven Flip-Flop Merging and Relocation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shao-Huan Wang, Yu-Yi Liang, Tien-Yu Kuo, Wai-Kei Mak
2012	J	`jnl`	Pad Assignment for Die-Stacking System-in-Package Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wai-Kei Mak, Yu-Chen Lin, Chris Chu, Ting-Chi Wang
2012	J	`jnl`	Rethinking the Wirelength Benefit of 3-D Integration. IEEE Trans. Very Large Scale Integr. Syst. Wai-Kei Mak, Chris Chu
2011	—	`conf`	Cut-demand based routing resource allocation and consolidation for routability enhancement. ASP-DAC Fong-Yuan Chang, Sheng-Hsiung Chen, Ren-Song Tsay, Wai-Kei Mak
2011	J	`jnl`	FOARS: FLUTE Based Obstacle-Avoiding Rectilinear Steiner Tree Construction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Gaurav Ajwani, Chris Chu, Wai-Kei Mak
2011	—	`conf`	Power-driven flip-flop merging and relocation. ISPD Shao-Huan Wang, Yu-Yi Liang, Tien-Yu Kuo, Wai-Kei Mak
2011	J	`jnl`	SafeChoice: A Novel Approach to Hypergraph Clustering for Wirelength-Driven Placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jackey Z. Yan, Chris C. N. Chu, Wai-Kei Mak
2011	B	`conf`	Simultaneous Constrained Pin Assignment and Escape Routing for FPGA-PCB Codesign. FPL Seong-I Lei, Wai-Kei Mak
2010	—	`conf`	FOARS: FLUTE based obstacle-avoiding rectilinear steiner tree construction. ISPD Gaurav Ajwani, Chris Chu, Wai-Kei Mak
2010	—	`conf`	SafeChoice: a novel clustering algorithm for wirelength-driven placement. ISPD Jackey Z. Yan, Chris Chu, Wai-Kei Mak
2010	—	`conf`	Temperature-constrained fixed-outline floorplanning for die-stacking system-in-package design. ACM Great Lakes Symposium on VLSI De-Yu Liu, Wai-Kei Mak, Ting-Chi Wang
2009	—	`conf`	Accurate closed-form parameterized block-based statistical timing analysis applying skew-normal distribution. ISQED Chun-Yu Chuang, Wai-Kei Mak
2009	A	`conf`	How to consider shorts and guarantee yield rate improvement for redundant wire insertion. ICCAD Fong-Yuan Chang, Ren-Song Tsay, Wai-Kei Mak
2009	A	`conf`	Pad assignment for die-stacking System-in-Package design. ICCAD Yu-Chen Lin, Wai-Kei Mak, Chris Chu, Ting-Chi Wang
2009	—	`conf`	Signal skew aware floorplanning and bumper signal assignment technique for flip-chip. ASP-DAC Cheng-Yu Wang, Wai-Kei Mak
2008	J	`jnl`	Guest Editorial: Field Programmable Technology. J. Signal Process. Syst. George A. Constantinides, Wai-Kei Mak, Theerayod Wiangtong
2008	J	`jnl`	Low-power gated and buffered clock network construction. ACM Trans. Design Autom. Electr. Syst. Wei-Chung Chao, Wai-Kei Mak
2007	—	`conf`	Optimal Buffering of FPGA Interconnect for Expected Delay Optimization. FPT Yi-Ru He, Wai-Kei Mak
2007	—	`conf`	Voltage Island Generation under Performance Requirement for SoC Designs. ASP-DAC Wai-Kei Mak, Jr-Wei Chen
2006	—	`ed.`	2006 IEEE International Conference on Field Programmable Technology, FPT 2006, Bangkok, Thailand, December 13-15, 2006 FPT George A. Constantinides, Wai-Kei Mak, Phaophak Sirisuk, Theerayod Wiangtong
2006	—	`conf`	A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers. ASP-DAC Chien-Chang Chen, Wai-Kei Mak
2005	—	`conf`	Modern FPGA constrained placement. ASP-DAC Wai-Kei Mak
2004	—	`conf`	Force-Directed Performance-Driven Placement Algorithm for FPGAs. ISVLSI Hao Li, Wai-Kei Mak, Srinivas Katkoori
2004	J	`jnl`	I/O placement for FPGAs with multiple I/O standards. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wai-Kei Mak
2004	J	`jnl`	Power minimization algorithms for LUT-based FPGA technology mapping. ACM Trans. Design Autom. Electr. Syst. Hao Li, Srinivas Katkoori, Wai-Kei Mak
2003	—	`conf`	Clustering based acyclic multi-way partitioning. ACM Great Lakes Symposium on VLSI Eric S. H. Wong, Evangeline F. Y. Young, Wai-Kei Mak
2003	—	`conf`	Efficient LUT-based FPGA technology mapping for power minimization. ASP-DAC Hao Li, Wai-Kei Mak, Srinivas Katkoori
2003	A	`conf`	I/O placement for FPGAs with multiple I/O standards. FPGA Wai-Kei Mak
2003	J	`jnl`	Temporal logic replication for dynamically reconfigurable FPGA partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wai-Kei Mak, Evangeline F. Y. Young
2002	J	`jnl`	Min-cut partitioning with functional replication fortechnology-mapped circuits using minimum area overhead. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wai-Kei Mak
2002	—	`conf`	Temporal logic replication for dynamically reconfigurable FPGA partitioning. ISPD Wai-Kei Mak, Evangeline F. Y. Young
2001	—	`conf`	Faster and more accurate wiring evaluation in interconnect-centric floorplanning. ACM Great Lakes Symposium on VLSI Hung-Ming Chen, D. F. Wong, Wai-Kei Mak, Hannah Honghua Yang
2001	—	`conf`	Min-cut partitioning with functional replication for technology mapped circuits using minimum area overhead. ISPD Wai-Kei Mak
2000	J	`jnl`	A fast hypergraph min-cut algorithm for circuit partitioning. Integr. Wai-Kei Mak, D. F. Wong
1999	—	`conf`	A fast hypergraph minimum cut algorithm. ISCAS (6) Wai-Kei Mak, D. F. Wong
1999	J	`jnl`	Monte Carlo bounding techniques for determining solution quality in stochastic programs. Oper. Res. Lett. Wai-Kei Mak, David P. Morton, R. Kevin Wood
1998	A	`conf`	Performance-Driven Board-Level Routing for FPGA-Based Logic Emulation (Abstract). FPGA Wai-Kei Mak, D. F. Wong
1998	C	`conf`	Performance-driven board-level routing for FPGA-based logic emulation. ICCD Wai-Kei Mak, D. F. Wong
1997	J	`jnl`	Board-level multiterminal net routing for FPGA-based logic emulation. ACM Trans. Design Autom. Electr. Syst. Wai-Kei Mak, D. F. Wong
1997	C	`conf`	Channel Segmentation Design for Symmentrical FPGAs. ICCD Wai-Kei Mak, D. F. Wong
1997	J	`jnl`	Minimum replication min-cut partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wai-Kei Mak, Martin D. F. Wong
1997	J	`jnl`	On optimal board-level routing for FPGA-based logic emulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wai-Kei Mak, Martin D. F. Wong
1996	A	`conf`	Minimum replication min-cut partitioning. ICCAD Wai-Kei Mak, D. F. Wong
1995	A	`conf`	Board-level multi-terminal net routing for FPGA-based logic emulation. ICCAD Wai-Kei Mak, D. F. Wong
1995	A*	`conf`	On Optimal Board-Level Routing for FPGA-Based Logic Emulation. DAC Wai-Kei Mak, D. F. Wong
1993	—	`conf`	Dilation-5 Embedding of 3-Dimensional Grids into Hypercubes. SPDP Mee Yee Chan, Francis Y. L. Chin, Chris Chu, Wai-Kei Mak
1990	—	`conf`	Implementation of the Ficus Replicated File System. USENIX Summer Richard G. Guy, John S. Heidemann, Wai-Kei Mak, Thomas W. Page Jr., Gerald J. Popek, Dieter Rothmeier