Wai-Chung Tang

16 papers A* 1A 2C 1Misc 1Journal 2Unranked 8
YearRankTypeTitle / Venue / Authors
2014 A conf
A scalable routability-driven analytical placer with global router integration for FPGAs (abstract only).
FPGA
Ka-Chun Lam, Wai-Chung Tang, Evangeline F. Y. Young
2014 Misc conf
Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire.
VLSID
Xing Wei, Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yi Diao, Yu-Liang Wu
2013 — conf
Mountain-mover: An intuitive logic shifting heuristic for improving timing slack violating paths.
ASP-DAC
Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert
2012 A conf
Almost every wire is removable: A modeling and solution for removing any circuit wire.
DATE
Xiaoqing Yang, Tak-Kei Lam, Wai-Chung Tang, Yu-Liang Wu
2012 — conf
ECO timing optimization with negotiation-based re-routing and logic re-structuring using spare cells.
ASP-DAC
Xing Wei, Wai-Chung Tang, Yi Diao, Yu-Liang Wu
2012 J jnl
ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme.
ACM Trans. Design Autom. Electr. Syst.
Tak-Kei Lam, Wai-Chung Tang, Xiaoqing Yang, Yu-Liang Wu
2012 J jnl
Postgrid Clock Routing for High Performance Microprocessor Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze
2012 — conf
WRIP: logic restructuring techniques for wirelength-driven incremental placement.
ACM Great Lakes Symposium on VLSI
Xing Wei, Wai-Chung Tang, Yu-Liang Wu, Cliff C. N. Sze, Charles J. Alpert
2011 — conf
Grid-to-ports clock routing for high performance microprocessor designs.
ISPD
Haitong Tian, Wai-Chung Tang, Evangeline F. Y. Young, Cliff C. N. Sze
2011 — conf
On applying erroneous clock gating conditions to further cut down power.
ASP-DAC
Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu
2010 — conf
Logic synthesis for low power using clock gating and rewiring.
ACM Great Lakes Symposium on VLSI
Tak-Kei Lam, Steve Yang, Wai-Chung Tang, Yu-Liang Wu
2008 — conf
A Quantitative Study of the Routing Architecture Exploring Routing Locality Property for Better Performance and Routability.
ERSA
Wai-Chung Tang, Catherine L. Zhou, Yu-Liang Wu
2008 — —
Improving FPGA designs with incremental logic resynthesis and shortcut-based routing architecture.
Wai-Chung Tang
2007 C conf
Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring.
ISCAS
Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu
2007 A* conf
How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs.
DAC
Catherine L. Zhou, Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu
2005 — conf
FPGA technology mapping optimization by rewiring algorithms.
ISCAS (6)
Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu, Shih-Chieh Chang