Víctor Viñals Yúfera

15 papers A* 1Misc 1Journal 11Unranked 2
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Complexity-Effective Local Delta Prefetcher.
IEEE Trans. Computers
Agustín Navarro-Torres, Biswabandan Panda, Jesús Alastruey-Benedé, Pablo Ibáñez, Víctor Viñals Yúfera, Alberto Ros
2023 J jnl
BALANCER: bandwidth allocation and cache partitioning for multicore processors.
J. Supercomput.
Agustín Navarro-Torres, Jesús Alastruey-Benedé, Pablo Ibáñez, Víctor Viñals Yúfera
2022 A* conf
Berti: an Accurate Local-Delta Data Prefetcher.
MICRO
Agustín Navarro-Torres, Biswabandan Panda, Jesús Alastruey-Benedé, Pablo Ibáñez, Víctor Viñals Yúfera, Alberto Ros
2020 J jnl
Accelerating Sequence Alignments Based on FM-Index Using the Intel KNL Processor.
IEEE ACM Trans. Comput. Biol. Bioinform.
Jose Manuel Herruzo, Sonia González-Navarro, Pablo Ibáñez-Marín, Víctor Viñals Yúfera, Jesús Alastruey-Benedé, Oscar G. Plata
2020 J jnl
Automatic Safe Data Reuse Detection for the WCET Analysis of Systems With Data Caches.
IEEE Access
Juan Segarra, Jordi Cortadella, Ruben Gran Tejero, Víctor Viñals Yúfera
2019 J jnl
A fault-tolerant last level cache for CMPs operating at ultra-low voltage.
J. Parallel Distributed Comput.
Alexandra Ferrerón-Labari, Jesús Alastruey-Benedé, Darío Suárez Gracia, Teresa Monreal Arnal, Pablo Ibáñez-Marín, Víctor Viñals Yúfera
2017 — conf
A tool for synthesizing power-efficient and custom-tailored wavelength-routed optical rings.
ASP-DAC
Marta Ortín-Obón, Luca Ramini, Víctor Viñals Yúfera, Davide Bertozzi
2017 J jnl
Contrasting Laser Power Requirements of Wavelength-Routed Optical NoC Topologies Subject to the Floorplanning, Placement, and Routing Constraints of a 3-D-Stacked System.
IEEE Trans. Very Large Scale Integr. Syst.
Marta Ortín-Obón, Mahdi Tala, Luca Ramini, Víctor Viñals Yúfera, Davide Bertozzi
2016 J jnl
Analysis of network-on-chip topologies for cost-efficient chip multiprocessors.
Microprocess. Microsystems
Marta Ortín-Obón, Darío Suárez Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals Yúfera
2014 J jnl
Revisiting LP-NUCA Energy Consumption: Cache Access Policies and Adaptive Block Dropping.
ACM Trans. Archit. Code Optim.
Darío Suárez Gracia, Alexandra Ferrerón-Labari, Luis Montesano Del Campo, Teresa Monreal Arnal, Víctor Viñals Yúfera
2013 — conf
Shrinking L1 Instruction Caches to Improve Energy-Delay in SMT Embedded Processors.
ARCS
Alexandra Ferrerón-Labari, Marta Ortín-Obón, Darío Suárez Gracia, Jesús Alastruey-Benedé, Víctor Viñals Yúfera
2012 J jnl
Effcient Handling of Lock Hand-off in DSM Multiprocessors with Buffering Coherence Controllers.
J. Comput. Sci. Technol.
Benjamín Sahelices, Agustín De Dios Hernández, Pablo Ibáñez, Víctor Viñals Yúfera, José María Llabería
2012 J jnl
LP-NUCA: Networks-in-Cache for High-Performance Low-Power Embedded Processors.
IEEE Trans. Very Large Scale Integr. Syst.
Darío Suárez Gracia, Giorgos Dimitrakopoulos, Teresa Monreal Arnal, Manolis Katevenis, Víctor Viñals Yúfera
2009 J jnl
Store Buffer Design for Multibanked Data Caches.
IEEE Trans. Computers
Enrique F. Torres, Pablo Ibáñez, Víctor Viñals Yúfera, José María Llabería
2007 Misc conf
A proposal to introduce power and energy notions in computer architecture laboratories.
WCAE
Alicia Asín Pérez, Darío Suárez Gracia, Víctor Viñals Yúfera