Víctor Viñals

61 papers A* 5A 5B 5C 4Journal 23Unranked 19

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	Reuse Detector: Improving the Management of STT-RAM SLLCs. CoRR Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro, Pablo Ibáñez, Daniel Chaver, Víctor Viñals, Juan Carlos Saez, Manuel Prieto-Matías, Luis Piñuel, Teresa Monreal, José María Llabería
2023	A*	`conf`	Compression-Aware and Performance-Efficient Insertion Policies for Long-Lasting Hybrid LLCs. HPCA Carlos Escuin, Asif Ali Khan, Pablo Ibáñez, Teresa Monreal, Jerónimo Castrillón, Víctor Viñals
2023	—	`conf`	MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array. ICECS Carlos Escuin, Fernando García-Redondo, Mahdi Zahedi, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, José María Llabería, James Myers, Julien Ryckaert, Dwaipayan Biswas, Francky Catthoor
2022	J	`jnl`	Forecasting lifetime and performance of a novel NVM last-level cache with compression. CoRR Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals
2022	—	`conf`	HyCSim: A rapid design space exploration tool for emerging hybrid last-level caches. DroneSE/RAPIDO@HiPEAC Carlos Escuin, Asif Ali Khan, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, Jerónimo Castrillón
2022	J	`jnl`	L2C2: Last-Level Compressed-Cache NVM and a Procedure to Forecast Performance and Lifetime. CoRR Carlos Escuin, Pablo Ibáñez, Teresa Monreal, José M. Llabería, Víctor Viñals
2022	—	`conf`	peRISCVcope: A Tiny Teaching-Oriented RISC-V Interpreter. DCIS Darío Suárez Gracia, Alejandro Valero, Ruben Gran Tejero, María Villarroya-Gaudó, Víctor Viñals
2021	J	`jnl`	A generic framework to integrate data caches in the WCET analysis of real-time systems. J. Syst. Archit. Juan Segarra, Ruben Gran Tejero, Víctor Viñals
2021	J	`jnl`	Near-optimal replacement policies for shared caches in multicore processors. J. Supercomput. Javier Díaz, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, José M. Llabería
2019	B	`conf`	Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding. DCC Jose Manuel Herruzo, Sonia González-Navarro, Pablo Ibáñez, Víctor Viñals, Jesús Alastruey-Benedé, Oscar G. Plata
2019	—	`conf`	Exposing Abstraction-Level Interactions with a Parallel Ray Tracer. WCAE@ISCA Alejandro Valero, Darío Suárez Gracia, Ruben Gran Tejero, Luis M. Ramos, Agustín Navarro-Torres, Adolfo Muñoz, Joaquín Ezpeleta, José Luis Briz, Ana C. Murillo, Eduardo Montijano, Javier Resano, María Villarroya-Gaudó, Jesús Alastruey-Benedé, Enrique F. Torres, Pedro Álvarez, Pablo Ibáñez, Víctor Viñals
2019	J	`jnl`	ReD: A reuse detector for content selection in exclusive shared last-level caches. J. Parallel Distributed Comput. Javier Díaz, Teresa Monreal, Pablo Ibáñez, José M. Llabería, Víctor Viñals
2018	J	`jnl`	Reuse Detector: Improving the Management of STT-RAM SLLCs. Comput. J. Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro, Pablo Ibáñez, Daniel Chaver, Víctor Viñals, Juan Carlos Saez, Manuel Prieto-Matías, Luis Piñuel, Teresa Monreal Arnal, José María Llabería
2016	J	`jnl`	Reactive circuits: Dynamic construction of circuits for reactive traffic in homogeneous CMPs. J. Parallel Distributed Comput. Marta Ortín-Obón, Darío Suárez Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals
2015	J	`jnl`	A predictable hardware to exploit temporal reuse in real-time and embedded systems. J. Syst. Archit. Ruben Gran, Juan Segarra, A. Pedro-Zapater, Luis C. Aparicio, Víctor Viñals, Clemente Rodríguez
2015	J	`jnl`	ACDC: Small, Predictable and High-Performance Data Cache. ACM Trans. Embed. Comput. Syst. Juan Segarra, Clemente Rodríguez, Ruben Gran, Luis C. Aparicio, Víctor Viñals
2015	—	`conf`	Partitioning Strategies of Wavelength-Routed Optical Networks-on-Chip for Laser Power Minimization. SiPhotonics@HiPEAC Marta Ortín, Luca Ramini, Marco Balboni, Lorenzo Zuolo, Maddalena Nonato, Víctor Viñals, Davide Bertozzi
2014	—	`conf`	A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip. ACM Great Lakes Symposium on VLSI Marta Ortín-Obón, Luca Ramini, Hervé Tatenguem Fankem, Víctor Viñals, Davide Bertozzi
2014	—	`conf`	Augmenting manycore programmable accelerators with photonic interconnect technology for the high-end embedded computing domain. NOCS Marco Balboni, Marta Ortín-Obón, Alessandro Capotondi, Hervé Tatenguem Fankem, Alberto Ghiribaldi, Luca Ramini, Víctor Viñals, Andrea Marongiu, Davide Bertozzi
2014	C	`conf`	Block Disabling Characterization and Improvements in CMPs Operating at Ultra-low Voltages. SBAC-PAD Alexandra Ferrerón-Labari, Darío Suárez Gracia, Jesús Alastruey-Benedé, Teresa Monreal Arnal, Víctor Viñals
2014	J	`jnl`	Capturing the sensitivity of optical network quality metrics to its network interface parameters. Concurr. Comput. Pract. Exp. Marta Ortín-Obón, Luca Ramini, Víctor Viñals, Davide Bertozzi
2014	A	`conf`	Dynamic construction of circuits for reactive traffic in homogeneous CMPs. DATE Marta Ortín, Darío Suárez Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals
2013	—	`conf`	Characterization and cost-efficient selection of NoC topologies for general purpose CMPs. INA-OCMC@HiPEAC Marta Ortín, Alexandra Ferreron, Jorge Albericio, Darío Suárez Gracia, María Villarroya-Gaudó, Cruz Izu, Víctor Viñals
2013	J	`jnl`	Exploiting reuse locality on inclusive shared last-level caches. ACM Trans. Archit. Code Optim. Jorge Albericio, Pablo Ibáñez, Víctor Viñals, José María Llabería
2013	J	`jnl`	Optimizing a combined WCET-WCEC problem in instruction fetching for real-time systems. J. Syst. Archit. Ruben Gran Tejero, Juan Segarra, Clemente Rodríguez, Luis C. Aparicio, Víctor Viñals
2013	A*	`conf`	The reuse cache: downsizing the shared last-level cache. MICRO Jorge Albericio, Pablo Ibáñez, Víctor Viñals, José M. Llabería
2012	A	`conf`	A Small and Effective Data Cache for Real-Time Multitasking Systems. IEEE Real-Time and Embedded Technology and Applications Symposium Juan Segarra, Clemente Rodríguez, Ruben Gran Tejero, Luis C. Aparicio, Víctor Viñals
2012	J	`jnl`	ABS: A low-cost adaptive controller for prefetching in a banked shared last-level cache. ACM Trans. Archit. Code Optim. Jorge Albericio, Ruben Gran Tejero, Pablo Ibáñez, Víctor Viñals, José María Llabería
2011	—	`conf`	Filtering Directory Lookups in CMPs with Write-Through Caches. Euro-Par (1) Ana Bosque, Víctor Viñals, Pablo Ibáñez, José María Llabería
2011	J	`jnl`	Filtering directory lookups in CMPs. Microprocess. Microsystems Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería
2011	J	`jnl`	Improving the WCET computation in the presence of a lockable instruction cache in multitasking real-time systems. J. Syst. Archit. Luis C. Aparicio, Juan Segarra, Clemente Rodríguez, Víctor Viñals
2011	J	`jnl`	Multi-level Adaptive Prefetching based on Performance Gradient Tracking. J. Instr. Level Parallelism Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals
2010	B	`conf`	Combining Prefetch with Instruction Cache Locking in Multitasking Real-Time Systems. RTCSA Luis C. Aparicio, Juan Segarra, Clemente Rodríguez, Víctor Viñals
2010	C	`conf`	Filtering Directory Lookups in CMPs. DSD Ana Bosque, Víctor Viñals, Pablo Ibáñez, José M. Llabería
2009	—	`conf`	A Methodology to Characterize Critical Section Bottlenecks in DSM Multiprocessors. Euro-Par Benjamín Sahelices, Pablo Ibáñez, Víctor Viñals, José María Llabería
2009	A	`conf`	Light NUCA: A proposal for bridging the inter-cache latency gap. DATE Darío Suárez Gracia, Teresa Monreal, Fernando Vallejo, Ramón Beivide, Víctor Viñals
2008	B	`conf`	Avoiding the WCET Overestimation on LRU Instruction Cache. RTCSA Luis C. Aparicio, Juan Segarra, Clemente Rodríguez, J. L. Villarroel, Víctor Viñals
2008	—	`conf`	Low-Cost Adaptive Data Prefetching. Euro-Par Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals
2008	C	`conf`	Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. SBAC-PAD Jesús Alastruey, Teresa Monreal, Francisco J. Cazorla, Víctor Viñals, Mateo Valero
2007	—	`conf`	Characterization of Apache web server with Specweb2005. MEDEA@PACT Ana Bosque, Pablo Ibáñez, Víctor Viñals, Per Stenström, José María Llabería
2007	J	`jnl`	Data prefetching in a cache hierarchy with high bandwidth and capacity. SIGARCH Comput. Archit. News Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals
2007	A	`conf`	Microarchitectural Support for Speculative Register Renaming. IPDPS Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero
2006	—	`conf`	Data prefetching in a cache hierarchy with high bandwidth and capacity. MEDEA@PACT Luis M. Ramos, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals
2006	J	`jnl`	Software Demand, Hardware Supply. IEEE Micro Jesús Alastruey, José Luis Briz, Pablo Ibáñez, Víctor Viñals
2006	—	`conf`	Speculative early register release. Conf. Computing Frontiers Jesús Alastruey, Teresa Monreal, Víctor Viñals, Mateo Valero
2006	—	`conf`	Speeding-Up Synchronizations in DSM Multiprocessors. Euro-Par Agustín De Dios Hernández, Benjamín Sahelices Fernández, Pablo Ibáñez, Víctor Viñals, José M. Llabería
2005	J	`jnl`	Hardware support for early register release. Int. J. High Perform. Comput. Netw. Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero
2005	A*	`conf`	Store Buffer Design in First-Level Multibanked Data Caches. ISCA Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería
2005	J	`jnl`	Tradeoffs in buffering speculative memory state for thread-level speculation in multiprocessors. ACM Trans. Archit. Code Optim. María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas
2004	—	`conf`	Contents Management in First-Level Multibanked Data Caches. Euro-Par Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería
2004	J	`jnl`	Late Allocation and Early Release of Physical Registers. IEEE Trans. Computers Teresa Monreal, Víctor Viñals, José González, Antonio González, Mateo Valero
2003	—	`conf`	Counteracting Bank Misprediction in Sliced First-Level Caches. Euro-Par Enrique F. Torres, Pablo Ibáñez, Víctor Viñals, José María Llabería
2003	A*	`conf`	Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors. HPCA María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas
2003	—	`conf`	Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation. IEEE PACT María Jesús Garzarán, Milos Prvulovic, Víctor Viñals, José María Llabería, Lawrence Rauchwerger, Josep Torrellas
2002	B	`conf`	Hardware Schemes for Early Register Release. ICPP Teresa Monreal, Víctor Viñals, Antonio González, Mateo Valero
2001	C	`conf`	Hardware Prefetching in Bus-Based Multiprocessors: Pattern Characterization and Cost-Effective Hardware. PDP María Jesús Garzarán, José Luis Briz, Pablo E. Ibáñez, Víctor Viñals
2000	J	`jnl`	Dynamic Register Renaming Through Virtual-Physical Registers. J. Instr. Level Parallelism Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
2000	B	`conf`	Modeling load address behaviour through recurrences. ISPASS Luis M. Ramos, Pablo E. Ibáñez, Víctor Viñals, José M. Llabería
1999	A*	`conf`	Delaying Physical Register Allocation through Virtual-Physical Registers. MICRO Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals
1998	A	`conf`	Characterization and Improvement of Load/Store Cache-based Prefetching. International Conference on Supercomputing Pablo Ibáñez, Víctor Viñals, José Luis Briz, María Jesús Garzarán
1996	—	`conf`	Performance Assessment of Contents Management in Multilevel On-Chip Caches. EUROMICRO Pablo Ibáñez, Víctor Viñals